CN103391090B - A kind of circuit of realizing three kinds of state recognitions of input signal - Google Patents
A kind of circuit of realizing three kinds of state recognitions of input signal Download PDFInfo
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- CN103391090B CN103391090B CN201310302278.XA CN201310302278A CN103391090B CN 103391090 B CN103391090 B CN 103391090B CN 201310302278 A CN201310302278 A CN 201310302278A CN 103391090 B CN103391090 B CN 103391090B
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Abstract
The invention discloses a kind of circuit of realizing three kinds of state recognitions of input signal, there is high frequency sampled signal input and signal input part, the first switch, second switch, the first triode and the second triode, described the first switch is used for providing high level input switch, and described second switch is used for providing low level input switch. The present invention can identify three kinds of states, inputs effective hardware circuit without designing respectively identification high level and low level again, and input port can be multiplexing, shortened the duration of occupying system resources.
Description
Technical field
The present invention relates to circuit recognition technology, relate in particular to a kind of input signal three kinds of state recognitions of realizingCircuit.
Background technology
At present, most circuit can only be realized the identification of two kinds of signals, i.e. high level and low level state,For the third state-vacant state, be generally to realize identification, be by vacant state under normal circumstancesOverlapping with the one in high level or low level, think a kind of state, as only effective to high level inputFig. 1 a shown in circuit and only low level is inputted to the circuit shown in effective Fig. 1 b.
The existing technical problem of above-mentioned technology is: 1) circuit can not be identified three kinds of states; 2) must divideHigh level She Ji do not identified and low level is inputted effective hardware circuit; 3) input port can not be multiplexing,Occupying system resources is more.
Summary of the invention
In view of this, the present invention proposes a kind of circuit of realizing three kinds of state recognitions of input signal, to solveIn prior art, can not identify three kinds of states, must design respectively the input of identification high level and low level effectivelyThe problem that hardware circuit, input port can not be multiplexing, occupying system resources is more.
For achieving the above object, technical scheme of the present invention is achieved in that
Realize a circuit for three kinds of state recognitions of input signal, wherein, there is the input of high frequency sampled signalEnd and signal input part, the first switch, second switch, the first triode and the second triode, described theOne switch is used for providing high level input switch, and described second switch is used for providing low level input switch;
Described the first triode has the first electrode, the second electrode and third electrode, described the second triodeThere is the 4th electrode, the 5th electrode and the 6th electrode, obtain described high frequency sampling by described the first electrodeAfter the input signal of signal input part, after described the second electrode, described the 4th electrode, pass through the described the 5thElectrode output, described the 6th electrode grounding; Described signal input part connects described the 4th electrode;
The high level voltage that described the first switch is controlled and the described third electrode of described the first triodeOn to draw voltage be same voltage.
The above-mentioned circuit of realizing three kinds of state recognitions of input signal, wherein, described the first triode is PNPType triode, described the second triode is NPN type triode.
The above-mentioned circuit of realizing three kinds of state recognitions of input signal, wherein, described high frequency sampled signal inputThe signal frequency of end input is higher than 5 times of the signal frequency of described signal input part.
The above-mentioned circuit of realizing three kinds of state recognitions of input signal, wherein, described signal input part is high electricityAt ordinary times, described output output low level; When described signal input part is low level, described output is defeatedGo out high level; When described signal input part is vacant state, described output output sampling clock, described in5 times～10 times of the high level voltage frequency that the frequency of sampling clock is controlled for described the first switch.
The above-mentioned circuit of realizing three kinds of state recognitions of input signal, wherein, described the first switch closure, instituteWhen stating second switch and opening, be high level or vacant state; Described the first switch opens, described second opensWhile closing closure, be low level or vacant state; When described the first switch and described second switch are all opened,For vacant state.
With respect to prior art, the present invention has following advantage:
Can identify three kinds of states, without design identification high level and low level input are effectively hard respectively againPart circuit, input port can be multiplexing, shortened the duration of occupying system resources.
Brief description of the drawings
The accompanying drawing that forms a part of the present invention is used to provide a further understanding of the present invention, of the present inventionSchematic description and description is used for explaining the present invention, does not form inappropriate limitation of the present invention. ?In accompanying drawing:
Fig. 1 a only inputs effective circuit diagram to high level in prior art;
Fig. 1 b only inputs effective circuit diagram to low level in prior art;
Fig. 2 is the circuit structure diagram that the present invention realizes the circuit embodiments of three kinds of state recognitions of input signal;
Fig. 3 a is the first switch institute of the present invention's circuit embodiments of realizing three kinds of state recognitions of input signalThe oscillogram of the input signal of controlling;
Fig. 3 b is the second switch institute of the present invention's circuit embodiments of realizing three kinds of state recognitions of input signalThe oscillogram of the input signal of controlling;
Fig. 3 c is the output signal that the present invention realizes the circuit embodiments of three kinds of state recognitions of input signalOscillogram;
When Fig. 3 d is the output sampling of the present invention's circuit embodiments of realizing three kinds of state recognitions of input signalThe waveform schematic diagram of clock.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried outDescribe clearly and completely, obviously, described embodiment is only the present invention's part embodiment, andNot whole embodiment. Based on the embodiment in the present invention, those of ordinary skill in the art are not doingGo out the every other embodiment obtaining under creative work prerequisite, all belong to the scope of protection of the invention.
It should be noted that, in the situation that not conflicting, the spy in embodiment and embodiment in the present inventionLevy and can mutually combine.
Basic thought of the present invention is: a kind of circuit that can support three kinds of state recognitions is provided, withoutDesign identification high level and low level are inputted effective hardware circuit respectively, and input port can be multiplexing, contractingThe duration of short occupying system resources.
Below in conjunction with accompanying drawing, each preferred embodiment of the present invention is described further:
With reference to Fig. 2, the present invention realizes the circuit of three kinds of state recognitions of input signal, has high frequency sampling letterNumber input SAMP_CLK and signal input part IN, the first switch SW 4, second switch SW3,The first triode Q4 and the second triode Q3, the first switch SW 4 is for high level input switch is provided,Second switch SW3 is used for providing low level input switch.
The first triode Q4 has the first electrode, the second electrode and third electrode, of the present invention preferredIn embodiment, the first triode Q4 is positive-negative-positive, and the first electrode is base stage b, and the second electrode is current collectionUtmost point c, third electrode is emitter e. The second triode Q3 is NPN type, has the 4th electrode,Five electrodes and the 6th electrode, preferably, the 4th electrode is base stage b, the 5th electrode is colelctor electrode c, theSix electrodes are emitter e. Obtain high frequency sampled signal input SAMP_CLK by the first electrode bInput signal after, after the second electrode c, the 4th electrode b by the 5th electrode c output, the 6th electricityUtmost point e ground connection, signal input part IN meets the 4th electrode b. With reference to Fig. 2, between each triode, pass through electricityResistance connects, and is connected input between the c utmost point of the first triode Q4 and input IN by the R8 of 20KBetween end IN and the b utmost point of the second triode Q3, be connected the second triode Q3 tool by the R7 of 20KThere is the pull-up resistor R9 of 20K, in addition, high frequency sampled signal input SAMP_CLK and the or threeBetween utmost point pipe Q4, there is the R10 of 2K. Certainly, above-mentioned resistance value size is not limited to the number of enumeratingValue.
The high level voltage VDD that the first switch SW 4 is controlled and the third electrode of the first triode Q4On to draw voltage VDD be same voltage, this key point 1 for indicating in figure.
The signal frequency of high frequency sampled signal input SAMP_CLK input is higher than the letter of signal input part5 times of number frequency, the signal frequency of SAMP_CLK input is larger, and the resolution ratio of circuit is just higher,This key point 2 for indicating in figure.
The first switch SW 4 closures, when second switch SW3 opens, signal input IN be high level orVacant state; The first switch SW 4 is opened, and when second switch SW3 is closed, signal input IN is lowLevel or vacant state; When the first switch SW 4 and second switch SW3 all open, it is vacant state.With reference to Fig. 3 a, Fig. 3 b and Fig. 3 c, in the time that signal input part is high level, output OUT output is lowLevel signal; In the time that signal input part IN is low level, output OUT exports high level; Work as signalWhen input IN is vacant state, output OUT exports sampling clock, and the frequency of sampling clock is5 times～10 times of the high level voltage frequency that one switch is controlled, such as the frequency of the input voltage of SW4Rate is 100Hz, and the frequency of sampling clock is 500Hz～1000Hz.
The frequency of sampling clock is random predetermined, and its waveform is with reference to shown in Fig. 3 d. According to or door theory,When signal intensity, sampling pulse can be clamped by signal, in addition, according to the frequency of composite signal and state, canTo judge the state of signal.
If regard circuit of the present invention as an input data processing module, through notebook data processing module placeOutput signal after reason can be used as the input signal of other programming modules.
In sum, continuous signal is transformed to discontinuous high-frequency signal by the present invention, can identify highLevel, low level and unsettled three kinds of states, without design identification high level and low level input have respectively againThe hardware circuit of effect, input port can be multiplexing, shortened the duration of occupying system resources.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all at thisWithin the spirit and principle of invention, any amendment of doing, be equal to replacement, improvement etc., all should be included inWithin protection scope of the present invention.
Claims (5)
1. a circuit of realizing three kinds of state recognitions of input signal, is characterized in that, has high frequency and adoptsSample signal input part (SAMP_CLK) and signal input part (IN), the first switch (SW4), secondSwitch (SW3), the first triode (Q4) and the second triode (Q3), described the first switch (SW4)Be used for providing high level input switch, described second switch (SW3) is for providing low level input switch;
Described the first triode (Q4) has the first electrode, the second electrode and third electrode, and described secondTriode (Q3) has the 4th electrode, the 5th electrode and the 6th electrode, obtains by described the first electrodeAfter the input signal of described high frequency sampled signal input, after described the second electrode, described the 4th electrodeBy described the 5th electrode output, described the 6th electrode grounding; Described signal input part connects described the 4th electricityThe utmost point;
The high level voltage that described the first switch (SW4) is controlled and described the first triode (Q4)On described third electrode, drawing voltage is same voltage;
Wherein, when described signal input part (IN) is high level, output (OUT) output low level;When described signal input part (IN) is low level, described output (OUT) output high level; DescribedWhen signal input part (IN) is vacant state, described output (OUT) output sampling clock.
2. the circuit of realizing according to claim 1 three kinds of state recognitions of input signal, its feature existsIn, described the first triode (Q4) is positive-negative-positive triode, described the second triode (Q3) isNPN type triode.
3. the circuit of realizing according to claim 1 three kinds of state recognitions of input signal, its feature existsIn, the signal frequency of described high frequency sampled signal input (SAMP_CLK) input is higher than described signal5 times of the signal frequency of input (IN).
4. the circuit of realizing according to claim 3 three kinds of state recognitions of input signal, its feature existsIn, the high level voltage frequency that the frequency of described sampling clock is controlled for described the first switch (SW4)5 times～10 times.
5. the circuit of realizing according to claim 4 three kinds of state recognitions of input signal, its feature existsIn, described the first switch (SW4) closure, when described second switch (SW3) is opened, is high levelOr vacant state; Described the first switch (SW4) is opened, when described second switch (SW3) is closed,For low level or vacant state; Described the first switch (SW4) and described second switch (SW3) are all beatenWhile opening, it is vacant state.
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| CN201310302278.XA CN103391090B (en) | 2013-07-15 | 2013-07-15 | A kind of circuit of realizing three kinds of state recognitions of input signal |
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| CN201310302278.XA CN103391090B (en) | 2013-07-15 | 2013-07-15 | A kind of circuit of realizing three kinds of state recognitions of input signal |
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| CN103391090A CN103391090A (en) | 2013-11-13 |
| CN103391090B true CN103391090B (en) | 2016-05-11 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104808561B (en) * | 2015-04-25 | 2017-06-20 | 航天科技控股集团股份有限公司 | Multistate switch state collecting device and method |
| CN108733587A (en) * | 2017-04-20 | 2018-11-02 | 中兴通讯股份有限公司 | Sub- equipment localization method and system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3159247B2 (en) * | 1997-09-29 | 2001-04-23 | 日本電気株式会社 | Input circuit |
| CN2842887Y (en) * | 2005-05-23 | 2006-11-29 | 海尔集团公司 | Multi plexing communication interface circuit |
| CN102201807A (en) * | 2011-04-11 | 2011-09-28 | 长沙景嘉微电子有限公司 | Simple tristate input circuit |
| CN202093346U (en) * | 2011-05-30 | 2011-12-28 | 深圳市博巨兴实业发展有限公司 | Status selection circuit for IO (input/output) port of single-chip microcomputer |
| CN102931971A (en) * | 2012-11-07 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Three-state control signal input/output (IO) circuit |
| CN202872406U (en) * | 2012-09-19 | 2013-04-10 | 青岛海信移动通信技术股份有限公司 | Interface multiplexing circuit and mobile terminal |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7609090B2 (en) * | 2006-08-23 | 2009-10-27 | Stmicroelectronics Pvt. Ltd. | High speed level shifter |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3159247B2 (en) * | 1997-09-29 | 2001-04-23 | 日本電気株式会社 | Input circuit |
| CN2842887Y (en) * | 2005-05-23 | 2006-11-29 | 海尔集团公司 | Multi plexing communication interface circuit |
| CN102201807A (en) * | 2011-04-11 | 2011-09-28 | 长沙景嘉微电子有限公司 | Simple tristate input circuit |
| CN202093346U (en) * | 2011-05-30 | 2011-12-28 | 深圳市博巨兴实业发展有限公司 | Status selection circuit for IO (input/output) port of single-chip microcomputer |
| CN202872406U (en) * | 2012-09-19 | 2013-04-10 | 青岛海信移动通信技术股份有限公司 | Interface multiplexing circuit and mobile terminal |
| CN102931971A (en) * | 2012-11-07 | 2013-02-13 | 长沙景嘉微电子股份有限公司 | Three-state control signal input/output (IO) circuit |
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