CN107968075B - 半导体封装以及制造方法 - Google Patents

半导体封装以及制造方法 Download PDF

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CN107968075B
CN107968075B CN201710084745.4A CN201710084745A CN107968075B CN 107968075 B CN107968075 B CN 107968075B CN 201710084745 A CN201710084745 A CN 201710084745A CN 107968075 B CN107968075 B CN 107968075B
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die
semiconductor package
buffer layer
wafer
thermal
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CN107968075A (zh
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邱瑞杰
黄智文
赖宥丞
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WIN Semiconductors Corp
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Abstract

一种半导体封装，包含有：一晶粒，包含至少一穿孔以及至少一热穿孔；一接地导线，直接形成于该晶粒的一背面下，该接地导线与该晶粒的该背面相接触，以及直接与该晶粒上的该至少一穿孔连接；一缓冲层，形成于该晶粒的一正面上，用来吸收施加于该晶粒上的一应力，以保护该晶粒；以及一模封部，形成于该缓冲层的一正面上，用来覆盖在该缓冲层的该正面上。

Description

半导体封装以及制造方法
【技术领域】
本发明系指一种半导体封装以及制造方法，尤指一种可防止晶粒受到损害，且小尺寸、低成本的半导体封装以及制造方法。
【背景技术】
随着科技演进，无线通讯科技已成为人类日常生活中重要的一部份，各式的电子通讯装置(如智能型手机、穿戴式装置、平板计算机…等)皆利用无线射频前端模块以进行无线射频讯号的接收与发送。
自从小尺寸成为电子通讯产品的需求考虑后，同样的，小尺寸也成为了无线射频的前端模块的设计要求，而近年来，晶圆级封装(WLP)技术因为小面积电子装置的制造而受到欢迎。图9为先前技术中以WLP技术制造无线射频的前端模块的示意图，依据WLP制程，当单晶微波集成电路(MMIC)的一晶圆MWF形成时，将一盖晶圆(Cap Wafer)CWF与晶圆MWF接合，其中晶圆MWF包含有多个晶粒DE，而盖晶圆CWF与晶圆MWF之间所形成的气腔AC可避免晶粒受到损害。此时于盖晶圆CWF接合于晶圆MWF上后进行切割制程，再将接合的晶圆(即晶圆MWF及盖晶圆CWF)分割为多个MMIC半导体封装PK，即可获得具有小面积的MMIC半导体封装PK的结果。
然而，将盖晶圆CWF接合在晶圆MWF上成本高昂，且MMIC半导体封装PK厚度也相对较大。因此，如何保护晶粒，同时又可以降低生产成本就成了业界所努力的目标之一。
【发明内容】
因此，本发明主要目的之一在于提供一种小尺寸与低成本的半导体封装以及制造方法，以改进先前技术的缺点。
本发明实施例揭露一种半导体封装，包含有一晶粒，其中该晶粒包含至少一穿孔与至少一热穿孔；一接地导线，直接形成于该晶粒的一背面下，该接地导线与该晶粒的该背面相接触，以及直接与该晶粒上的该至少一穿孔连接；一讯号导线，直接形成于该晶粒的该背面下，该讯号导线与该晶粒的该背面相接触，直接与该晶粒上的该至少一热穿孔连接；一缓冲层，形成于该晶粒的一正面上，用来吸收施加于该晶粒上的一应力，以保护该晶粒，并且使该晶粒不接触该模封部以避免不必要的寄生电容效应以及讯号损失；以及一模封部，形成于该缓冲层上。
本发明实施例另揭露一种制造方法，用来制造多个半导体封装，该方法的步骤包含，于一晶圆背面形成讯号导线与接地导线，其中该晶圆包含多个晶粒，且每一晶粒包含至少一穿孔与至少一热穿孔；于该晶圆上形成一缓冲层；于该缓冲层上形成一模封部，以及进行一切割制程(Singulation Process)以将该晶圆、该缓冲层及该模封部分割为多个半导体封装。
本发明实施例另揭露一种制造方法，用来制造多个半导体封装，该方法的步骤包含，将讯号导线与接地导线形成于一晶粒背面，其中该晶粒包含至少一穿孔与至少一热穿孔；于该晶粒上形成一缓冲层；于该缓冲层上形成一模封部，以及进行一切割制程以形成多个半导体封装。
【附图说明】
图1为本发明实施例一半导体封装的剖面示意图。
图2为本发明实施例一热穿孔的示意图。
图3至图7为制造图1的半导体封装的制程。
图8为本发明实施例一半导体封装的剖面示意图。
图9为已知以晶圆级封装技术制造射频前端模块的示意图。
图10为本发明实施例一半导体封装的剖面示意图。
图11为制造图10的半导体封装的制程。
其中的附图标记说明如下：
10、80、12、PK 半导体封装
100、300、DE 晶粒
102 接地导线
104 讯号导线
106 缓冲层
108 模封部
200、810 正面金属片
202 砷化镓基板
204 第一背面金属片
206 第二背面金属片
208 模封部
HVA 热穿孔
VA 穿孔
G1 间隙
NCH 凹槽
WF、MWF 晶圆
AC 气腔
CWF 盖晶圆
TP 胶带
SE 晶粒侧边边缘
BE_m 模封部底部边缘
BE_die 晶粒底部边缘
【具体实施方式】
图1为本发明实施例一半导体封装10的剖面示意图，半导体封装10可为一无线通讯装置的一射频(Radio Frequency，RF)前端模块(Front End Module，FEM)，其由一晶圆级封装(Wafer Level Packaging，WLP)技术制造。半导体封装10包含有一晶粒100、一接地导线102、讯号导线104、一缓冲层106以及一模封部108。晶粒100可由一砷化镓(GaAs)制程所制造，其可为应用于高频或射频领域的一单晶微波集成电路(Monotholic MicrowaveIntegrated Circuit，MMIC)。晶粒100包含热穿孔HVA及穿孔VA，其中热穿孔HVA可用来传递一射频(或一直流)讯号，而穿孔VA用来提供接地，接地导线102与讯号导线104直接形成于晶粒100的一背面，而与晶粒100的背面(直接)相互接触。除此之外，接地导线102与穿孔VA直接连接，而讯号导线104与热穿孔HVA直接连接。
另外，模封部108为一模封塑料(如环氧树脂)所制成，其依据一模封制程形成于晶粒100之上。需注意的是，晶粒100于模封制程时会受到一压力或一应力，为了避免该压力或应力损坏晶粒100，在晶粒100与模封部108之间形成有缓冲层106。换句话说，于晶粒100的一正面形成缓冲层106，并于缓冲层106上形成模封部108，其中缓冲层106可由一弹性材料所制成，该弹性材料可选自由聚酰亚胺(PI)、聚二溴苯醚(PBO)、苯并环丁烯(BCB)及硅化氮(Silicon Nitride，SiN2)所构成的群组的其中之一，以吸收/分散于该模封制程时，施于晶粒100上的该应力。
除此之外，于导线102与讯号导线104间形成有一间隙G1，为便于组装以防止其短路，间隙G1需具有足够的宽度，如大于150微米(μm)。在一实施例中，间隙G1可为300微米(μm)。
更进一步地，为达到半导体封装10较佳的接地与散热效能，接地导线102的面积需够大。于一实施例中，接地导线102的面积大于150*150平方微米(μm2)，于另一实施例中，接地导线102的面积大于晶粒背面的面积的50％。
另一方面，热穿孔HVA包含一中空结构，举例来说，请参考图2，图2为本发明实施例一热穿孔HVA的示意图。热穿孔HVA包含一正面金属片200、一砷化镓基板202，一第一背面金属片204与一第二背面金属片206。如图2所示，于热穿孔HVA的一中心处形成有一中空的凹槽NCH，而中空的热穿孔HVA可承受来自于晶粒100于一背板组装程序(Back Side AssemblyProcess)时所施加的应力或压力，此外，覆盖于正面中空部的正面金属片200亦可承受因模封制程的应力，以保护该晶粒。
关于半导体封装10的制造步骤，请参考图3至图7，图3至图7绘示半导体封装10的制程。如图3所示，缓冲层106形成于包含晶粒300的一晶圆WF上，此时晶粒300内尚未形成穿孔与热穿孔。如图4所示，而晶圆WF的晶粒100内已形成有穿孔VA与热穿孔HVA。如图5所示，将讯号导线104与接地导线102直接形成于晶圆WF的一背面，即将讯号导线104与接地导线102直接形成于晶粒100之下。讯号导线104与接地导线102可由沉积(Deposition)而形成，例如使用金(Au)或金锡合金(AuSn)的无电镀法(Electroless Plating)。需注意的是，图5中的虚线代表一分割制程的一切割边缘，而将于该切割边缘下的部份讯号导线104移除，以防止讯号导线104于分割制程时损坏。
图6为一模封制程示意图。需注意的是，于模封制程中，一显著的压力或应力将会施加于晶圆WF上，因缓冲层106由弹性材料制成，因此缓冲层106可吸收或分散该应力，以避免晶圆WF损害，另外，因为缓冲层106可保护晶圆WF，所以不需要透过盖晶圆来形成气腔。除此之外，形成模封部108的成本较为低廉(相较于以盖晶圆形成该气腔)，并且可降低整体厚度。
图7为进行一分割制程或一晶圆切割制程的示意图，于分割制程中，将晶圆WF、缓冲层106与模封部108分割为多个半导体封装10时，较佳地，可使晶粒100的面积与半导体封装10的面积相同，如此可缩小半导体封装10的面积，在此情况下，模封部108的侧边边缘可对齐于晶粒100的侧边边缘。另外，于分割制程中，晶圆WF可切割为棋盘状，而成为多个矩形的半导体封装10(即半导体封装10被切割成矩形)。于完成半导体封装10后，可对半导体封装10进行一组装程序，如将半导体封装10设置/安装于电子装置的电路板上(如印刷电路板)。
需注意的是，半导体封装10中的模封部108不与导线(即讯号导线104或接地导线102)直接接触，以避免非必要的寄生电容或是电感效应，因此，半导体封装10可获得较佳的射频表现。
如上述可知，本发明利用模封部108以减少厚度及半导体封装10的制造成本，利用缓冲层106以吸收(或分散)施加于晶粒100上的压力或应力，以避免晶粒100受到损害，缓冲层106亦隔离射频讯号，使射频讯号(的走线)不与模封部108直接接触，如此一来，可进一步避免非必要的射频寄生效应与讯号损失。另外，接地导线102与讯号导线104直接形成于晶粒100的背面，使其不需要额外的压层印刷电路板(Laminate Printed Circuit Board，Laminate PCB)。相较于先前技术，因不需要使用盖晶圆来形成气腔，半导体封装10具有缩小尺寸及降低制作成本的优点。
需注意的是，前述实施例是用以说明本发明的概念，本领域具通常知识者当可据以做不同的修饰，而不限于此。举例来说，该半导体封装可包含至少一金属片。请参考图8，图8为本发明实施例一半导体封装80的剖面示意图。半导体封装80相似于半导体封装10，故将相同的组件沿用相同的符号。与半导体封装10不同的是，半导体封装80另包含一金属片810，金属片810设置于晶粒100的正面，而缓冲层106形成于金属片810与模封部108之间，其中金属片810可承受模封制程时施于晶粒100上的压力/应力，因而保护晶粒100不致损伤。
除此之外，模封部/模封塑料的侧边边缘不限于与晶粒100的侧边边缘对齐，模封部108亦可覆盖于晶粒100的侧边边缘。举例来说，请参考图10，图10为本发明实施例一半导体封装12的剖面示意图，半导体封装12相似于半导体封装10，故相同的组件沿用相同的符号。不同于半导体封装10的是，半导体封装12中的一模封部208覆盖晶粒100的侧边边缘SE，除此之外，由图10可知，模封部208的底部边缘BE_m与晶粒100的底部边缘BE_die对齐。
详细来说，关于半导体封装12的制造步骤，请参考图11，图11绘示制造半导体封装12的制程。如图11所示，首先于晶粒100内形成穿孔VA与热穿孔HVA，且于晶粒100正面上形成缓冲层106，并直接于晶粒100的背面下形成讯号导线104与接地导线102，接着将一胶带TP粘贴于晶粒100上，其中胶带TP除了可防止模封塑料溢漏，更可使模封塑料不与讯号导线104及接地导线102相接触，除此之外，于模封制程中，将模封塑料覆盖于胶带TP与晶粒100的正面上，而可形成模封部208，而形成于晶粒100上的缓冲层106，可以保护晶粒100不受模封制程时的模封压力与应力所损害，于模封塑料成形后，可撕除该背面的胶带。最后，将模封部208切割/分割形成为多个矩形半导体封装12。于多个矩形半导体封装12形成后，对其进行该组装，以将半导体封装12设置/装置于电子装置的电路板上。而与此领域的液态配置模封法(Molding Fluid Dispensing Method)不同的是，半导体封装12的模封部208不易与半导体封装12的背面下的导线相接触，此外，该模封塑料不溢漏至讯号导线104与接地导线102之间的该间隙，因此可避免不必要的寄生电容或电感效应，使得半导体封装12的射频表现增强。
由上述可知，晶粒的正面上的射频讯号会经由热穿孔直接传递至晶粒的背面。由于缓冲层可隔离晶粒与模封塑料，该射频讯号不会与模封部相接触。另外，于模封制程中，晶粒的正面上的模封塑料在溢至晶粒背面前会被挡住，如此一来，模封部不会与芯片背面的导线或金属相接触，以及该模封塑料不溢漏至该讯号导线104与该接地导线102之间的该间隙，进而避免不必要的寄生效应与讯号损失。
先前技术中，射频讯号路径所经的导线(与焊线)无法完全被隔离，使其接触于模封塑料，因而形成不必要的寄生电容与寄生电感效应，而降低该射频表现。
除此之外，此领域的该热穿孔结构难于一标准回焊制程实施。因电路表现考虑，于此领域中需要尽可能的缩小热穿孔与接地间的该间隙，为了克服该回焊制程的问题，将热穿孔的该间隙增加至大于150微米(μm)，且将该热穿孔的一焊盘(Pad)加大至大于150*150平方微米(μm2)。由于该背面金属的该电感性的降低，可得到较佳的质量因子(QualityFactor)，因此，可以将该影响于设计阶段纳入考虑并成为设计项部分，藉由如此施作，可将该回焊制程应用于半导体封装上用以大量生产。
由上述可知，本发明直接于晶粒背面下形成讯号导线与接地导线；于模封部与晶粒之间形成缓冲层，以吸收施加于该晶粒的应力；并于晶粒内形成热穿孔与穿孔以缩小半导体封装的面积。相较于先前技术，本发明的半导体封装具有缩小面积与降低制造成本的优点。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (16)

1.一种半导体封装，包含有：
一晶粒，包含至少一穿孔以及多个热穿孔，其中该多个热穿孔用来传递射频讯号，该多个热穿孔中的一热穿孔包含一中空结构，该中空结构为开放式的中空结构；
一接地导线，直接形成于该晶粒的一背面下，该接地导线与该晶粒的该背面相接触，以及直接与该晶粒上的该至少一穿孔连接；
一讯号导线，直接形成于该晶粒的该背面下，该讯号导线与该晶粒的该背面相接触，以及直接与该晶粒上的该热穿孔连接；
一缓冲层，形成于该晶粒的一正面上，用来吸收施加于该晶粒上的一应力，
以保护该晶粒；以及
一模封部，形成于该缓冲层的一正面上，用来覆盖在该缓冲层的该正面上；
其中，该模封部不与该讯号导线或该接地导线相接触；
其中，该缓冲层用来吸收一模封制程施加于该晶粒上的一应力，以避免该模封制程对该晶粒造成损坏，该模封制程用来形成该模封部。
2.如权利要求1所述的半导体封装，其中，该缓冲层是选自由聚酰亚胺，聚二溴苯醚，苯并环丁烯及硅化氮所构成的群组的其中之一。
3.如权利要求1所述的半导体封装，其中，在该接地导线与该讯号导线之间形成有一间隙。
4.如权利要求3所述的半导体封装，其中，该间隙大于50微米。
5.如权利要求3所述的半导体封装，该模封部不溢漏至讯号导线与接地导线之间的间隙。
6.如权利要求1所述的半导体封装，该接地导线内的面积大于100*100平方微米。
7.如权利要求1所述的半导体封装，其中，该接地导线的面积大于该晶粒的该背面的面积的50％。
8.如权利要求1所述的半导体封装，其中，该接地导线的面积大于该讯号导线的面积。
9.如权利要求1所述的半导体封装，其中，该模封部的一侧边边缘对齐于该晶粒的一侧边边缘。
10.如权利要求1所述的半导体封装，其中，该模封部的一底部边缘对齐该晶粒的一底部边缘。
11.如权利要求1所述的半导体封装，另包含至少一金属片，设置于该晶粒的一正面。
12.如权利要求1所述的半导体封装，其中，该半导体封装由一晶圆级封装技术所制成。
13.一种制造方法，用于制造多个半导体封装，其中，该制造方法于该多个半导体封装的一组装程序前进行，该方法包含：
于一晶圆的一背面下直接形成一讯号导线与一接地导线，其中该晶圆包含复数个晶粒，且每一晶粒包含至少一穿孔及多个热穿孔，其中该多个热穿孔用来传递射频讯号，该多个热穿孔中的一热穿孔包含一中空结构，
该中空结构为与开放式的中空结构；
于该晶圆上形成一缓冲层；
于该缓冲层上形成一模封部；以及
分割该晶圆、该缓冲层以及该模封部，以形成该多个半导体封装；
其中，该缓冲层用来吸收一模封制程施加于该晶圆上的一应力，以避免该模封制程对该晶圆造成损坏，该模封制程用来形成该模封部。
14.如权利要求13所述的制造方法，其中，该晶圆由一砷化镓制程所制造。
15.一种制造方法，用于制造多个半导体封装，其中，该制造方法于该多个半导体封装的一组装程序前进行，该方法包含：
于一晶粒的一背面下直接形成一讯号导线与一接地导线，其中该晶粒包含至少一穿孔与多个热穿孔，其中该多个热穿孔用来传递射频讯号，该多个热穿孔中的一热穿孔包含一中空结构，该中空结构为与开放式的中空结构；
于该晶粒的一正面形成一缓冲层；
形成一模封部，以覆盖该缓冲层；以及
进行一切割制程，以形成该多个半导体封装；
其中，该缓冲层用来吸收一模封制程施加于该晶粒上的一应力，以避免该模封制程对该晶粒造成损坏，该模封制程用来形成该模封部。
16.如权利要求15所述的制造方法，另包含：
在形成该模封部前，将一胶带粘贴于该晶粒的该背面；
其中，该模封部形成于该缓冲层之上。
CN201710084745.4A 2016-10-19 2017-02-16 半导体封装以及制造方法 Active CN107968075B (zh)

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