CN107910244A - 采用硅图形衬底生长氮化镓外延方法 - Google Patents

采用硅图形衬底生长氮化镓外延方法 Download PDF

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CN107910244A
CN107910244A CN201711058981.5A CN201711058981A CN107910244A CN 107910244 A CN107910244 A CN 107910244A CN 201711058981 A CN201711058981 A CN 201711058981A CN 107910244 A CN107910244 A CN 107910244A
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梁辉南
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Abstract

本发明公开一种采用硅图形衬底生长氮化镓外延方法,按照如下步骤进行:采用掩膜或者蚀刻在硅衬底上表面的横向和竖向形成等距的多条线条,所述线条高1~10μm、宽100~500μm,各线条之间的间距为1~3cm;采用金属有机物化学气相沉积法在硅衬底的上表面由下至上依次生长氮化铝缓冲层、铝镓氮渐变缓冲层、氮化镓缓冲层、氮化铝隔离层及铝镓氮器件层,所述铝镓氮渐变缓冲层由四层AlxGa1‑xN构成,由下至上每层AlxGa1‑xN结构的X值分别为0.8、0.6、0.4、0.2,铝镓氮渐变缓冲层的厚度为3~4.5μm,氮化镓缓冲层的厚度为1~2μm,所述氮化铝隔离层的厚度为1~10nm,铝镓氮器件层的厚度为20~40nm。

Description

采用硅图形衬底生长氮化镓外延方法
技术领域
本发明涉及半导体材料领域,尤其涉及一种操作简单、可有效解决外延生长过程中因应力而发生的断裂、弯曲等问题、降低产品生产成本的采用硅图形衬底生长氮化镓外延方法。
背景技术
目前,氮化镓功率器件已成为功率器件行业最前沿的热点和产业焦点,其生产中的关键技术之一是制备优良的氮化镓材料。虽然以碳化硅、蓝宝石为衬底,进行金属有机物化学气相沉积(MOCVD)外延生长可制备氮化镓材料,但是碳化硅、蓝宝石价格昂贵以及后续器件加工的设备兼容性问题,制约了氮化镓材料的大批量工业化生产。硅衬底具有成本低、晶圆尺寸大等优点。但是以硅为衬底进行金属有机物化学气相沉积(MOCVD)外延生长制备氮化镓材料,会在生长过程的以下几个阶段形成应力和演变:1)初期的加热升温过程中硅衬底表面和背面的温度差形成张应力;2)随着外延生长因为晶格不匹配导致的压应力逐渐取代温差引起的张应力;3)在外延生长末期压应力达到最大值;4)在降温过程中因为热膨胀不匹配导致的张应力逐渐抵消压应力。以上各个阶段的外延应力变化会直接导致外延裂纹及弯曲,无法应用于后续的电子器件加工,而硅衬底与氮化镓之间的高位错密度亦可导致氮化镓外延材料质量降低以及随之而来的低击穿电压。因此以硅为衬底进行金属有机物化学气相沉积(MOCVD)外延生长,首先需要解决缓解外延生长过程中应力及高位错密度这一技术难题。
现有的技术解决方案之一如图1所示,是采用金属有机物化学气相沉积法在硅衬底01的上表面由下至上依次生长氮化铝缓冲层02、多层(三组)铝镓氮渐变缓冲层03、氮化镓缓冲层04、氮化铝隔离层05及铝镓氮器件层06,第一铝镓氮渐变缓冲层为四层AlxGa1-xN(0.1≤X≤0.9)结构,由下至上,每层AlxGa1-xN 结构的X值逐渐减小;第二铝镓氮渐变缓冲层,生长在第一渐变缓冲层上,亦为四层AlxGa1-xN,由下至上每层AlxGa1-xN结构的X值逐渐增大;第三铝镓氮渐变缓冲层,生长在第二渐变缓冲层上,亦为四层AlxGa1-xN,由下至上每层AlxGa1-xN结构的X值又逐渐减小。该方法可以有效减小外延过程中的应力以及有效降低在外延生长末期的最大压应力,从而有效降低外延裂纹的产生,降低表面氮化镓缓冲层的位错密度,同时还提高了氮化镓外延结构的厚度(>5μm),满足功率器件对硅基氮化镓外延结构的高击穿电压要求(>600V)。但是,多组铝镓渐变缓冲层的生长操作复杂,器件加工时需要按尺寸将整个氮化镓材料划线切割,不利于加工,有时会因为切割等问题而导致氮化镓材料整体报废,损失较大。
发明内容
本发明是为了解决现有技术所存在的上述技术问题,提供一种操作简单、可有效解决外延生长过程中因应力而发生的断裂、弯曲等问题、降低产品生产成本的采用硅图形衬底生长氮化镓外延方法。
本发明的技术解决方案是:一种采用硅图形衬底生长氮化镓外延方法,其特征在于按照如下步骤进行:
a. 采用掩膜或者蚀刻在硅衬底上表面的横向和竖向形成等距的多条线条,所述线条高1~10μm、宽100~500μm,各线条之间的间距为1~3cm;
b. 采用金属有机物化学气相沉积法在硅衬底的上表面由下至上依次生长氮化铝缓冲层、铝镓氮渐变缓冲层、氮化镓缓冲层、氮化铝隔离层及铝镓氮器件层,所述铝镓氮渐变缓冲层由四层AlxGa1-xN构成,由下至上每层AlxGa1-xN结构的X值分别为0.8、0.6、0.4、0.2,所述铝镓氮渐变缓冲层的厚度为3μm~4.5μm,所述氮化镓缓冲层的厚度为1μm~2μm,所述氮化铝隔离层的厚度为1nm~10nm,所述铝镓氮器件层的厚度为20nm~40nm。
本发明通过采用图形化硅衬底,可以把纵向外延生长限制在衬底图形的单个区域(1~3 cm×1~3 cm)内,无需复杂的多组铝镓氮渐变缓冲层的生长,只需简单操作,就能够有效降低大尺寸外延的内部应力,从而降低外延裂纹的产生,降低表面氮化镓缓冲层的位错密度,有效提高氮化镓外延结构质量;可以按照器件规格在1~3 cm×1~3 cm范围内确定图形化方格尺寸,切割器件时只需按照图形化的线条切割硅衬底即可,加工简单,可降低产品生产成本。
附图说明
图1是现有技术中氮化镓外延的结构示意图。
图2是本发明实施例的硅衬底表面图案示意图。
图3是本发明实施例1的硅衬底图案截面示意图。
图4是本发明实施例2的硅衬底图案截面示意图。
图5是本发明实施例硅基氮化镓外延的结构示意图。
具体实施方式:
实施例1:
a. 如图2、图3所示:采用掩膜在所述硅(111)衬底1上表面的横向和竖向形成等距的多条SiO2线条2,线条2高于硅(111)衬底1上表面1μm、宽100μm,横向线条2之间的间距为1cm,竖向线条2之间的间距为3cm,横竖线条2交叉在硅(111)衬底1上表面形成均布的多个1 cm×3 cm方格;
b. 如图5所示:采用金属有机物化学气相沉积法在硅(111)衬底1的上表面由下至上纵向依次生长氮化铝缓冲层、铝镓氮渐变缓冲层4、氮化镓缓冲层5、氮化铝隔离层6及铝镓氮器件层7,所述铝镓氮渐变缓冲层4由四层AlxGa1-xN构成,由下至上每层AlxGa1-xN结构的X值分别为0.8、0.6、0.4、0.2,氮化铝缓冲层的厚度同现有技术,可为20 nm,铝镓氮渐变缓冲层的厚度为3μm,氮化镓缓冲层的厚度为1μm,氮化铝隔离层的厚度为1nm,铝镓氮器件层的厚度为20nm,即氮化镓外延只生长在硅(111)衬底1上表面均布的多个1 cm×3 cm方格内。
实施例2:
本发明的采用硅图形衬底生长氮化镓外延方法,按照如下步骤进行:
a. 如图2、图4所示:采用刻蚀在硅(111)衬底1上表面的横向和竖向形成等距的多条线条2,线条2低于硅(111)衬底1上表面10μm、宽500μm,横向线条2之间的间距为3cm,竖向线条2之间的间距为3cm,横竖线条2交叉在硅(111)衬底1上表面形成均布的多个3 cm×3 cm方格;
b. 如图5所示:采用金属有机物化学气相沉积法在硅(111)衬底1的上表面由下至上纵向依次生长氮化铝缓冲层、铝镓氮渐变缓冲层4、氮化镓缓冲层5、氮化铝隔离层6及铝镓氮器件层7,所述铝镓氮渐变缓冲层4由四层AlxGa1-xN构成,由下至上每层AlxGa1-xN结构的X值分别为0.8、0.6、0.4、0.2,氮化铝缓冲层的厚度同现有技术,可为30 nm,铝镓氮渐变缓冲层的厚度为4.5μm,氮化镓缓冲层的厚度为2μm,氮化铝隔离层的厚度为10nm,铝镓氮器件层的厚度为40nm,即氮化镓外延只生长在硅(111)衬底1上表面均布的多个1 cm×3 cm方格内。
实施例3:
a. 如图2、图3所示:采用掩膜在所述硅(111)衬底1上表面的横向和竖向形成等距的多条SiO2线条2,线条2高于硅(111)衬底1上表面5μm、宽300μm,横向线条2之间的间距为2cm,竖向线条2之间的间距为1cm,横竖线条2交叉在硅(111)衬底1上表面形成均布的多个2 cm×1 cm方格;
b. 如图5所示:采用金属有机物化学气相沉积法在硅(111)衬底1的上表面由下至上纵向依次生长氮化铝缓冲层、铝镓氮渐变缓冲层4、氮化镓缓冲层5、氮化铝隔离层6及铝镓氮器件层7,所述铝镓氮渐变缓冲层4由四层AlxGa1-xN构成,由下至上每层AlxGa1-xN结构的X值分别为0.8、0.6、0.4、0.2,氮化铝缓冲层的厚度同现有技术,可为25 nm,铝镓氮渐变缓冲层的厚度为4.5μm,氮化镓缓冲层的厚度为2μm,氮化铝隔离层的厚度为5nm,铝镓氮器件层的厚度为30nm,即氮化镓外延只生长在硅(111)衬底1上表面均布的多个2 cm×1 cm方格内。

Claims (1)

1.一种采用硅图形衬底生长氮化镓外延方法,其特征在于按照如下步骤进行:
a. 采用掩膜或者蚀刻在硅衬底(1)上表面的横向和竖向形成等距的多条线条(2),所述线条(2)高1~10μm、宽100~500μm,各线条(2)之间的间距为1~3cm;
b. 采用金属有机物化学气相沉积法在硅衬底(1)的上表面由下至上依次生长氮化铝缓冲层(3)、铝镓氮渐变缓冲层(4)、氮化镓缓冲层(5)、氮化铝隔离层(6)及铝镓氮器件层(7),所述铝镓氮渐变缓冲层(4)由四层AlxGa1-xN构成,由下至上每层AlxGa1-xN结构的X值分别为0.8、0.6、0.4、0.2,所述铝镓氮渐变缓冲层的厚度为3μm~4.5μm,所述氮化镓缓冲层的厚度为1μm~2μm,所述氮化铝隔离层的厚度为1nm~10nm,所述铝镓氮器件层的厚度为20nm~40nm。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109830535A (zh) * 2018-11-23 2019-05-31 厦门市三安集成电路有限公司 具有纳米台阶递变层的高阻氮化镓基缓冲层及制备方法
WO2019228424A1 (zh) * 2018-05-30 2019-12-05 厦门市三安集成电路有限公司 GaN基外延结构及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060012806A (ko) * 2004-08-04 2006-02-09 삼성전기주식회사 질화물 반도체 결정성장방법 및 질화물 반도체 소자제조방법
CN103400913A (zh) * 2013-07-22 2013-11-20 南昌黄绿照明有限公司 一种用于生长六方相GaN的矩形图形化硅衬底
CN104018214A (zh) * 2014-06-10 2014-09-03 广州市众拓光电科技有限公司 一种用于GaN半导体材料外延的矩形图形化Si衬底AlN模板及其制备方法
CN104362080A (zh) * 2014-09-24 2015-02-18 南昌大学 Si衬底上选择性生长GaN基薄膜材料的方法
CN105720088A (zh) * 2014-12-03 2016-06-29 梁辉南 硅基氮化镓外延结构及其制造方法
US20170011911A1 (en) * 2010-11-16 2017-01-12 Rohm Co., Ltd. Nitride semiconductor element and nitride semiconductor package

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060012806A (ko) * 2004-08-04 2006-02-09 삼성전기주식회사 질화물 반도체 결정성장방법 및 질화물 반도체 소자제조방법
US20170011911A1 (en) * 2010-11-16 2017-01-12 Rohm Co., Ltd. Nitride semiconductor element and nitride semiconductor package
CN103400913A (zh) * 2013-07-22 2013-11-20 南昌黄绿照明有限公司 一种用于生长六方相GaN的矩形图形化硅衬底
CN104018214A (zh) * 2014-06-10 2014-09-03 广州市众拓光电科技有限公司 一种用于GaN半导体材料外延的矩形图形化Si衬底AlN模板及其制备方法
CN104362080A (zh) * 2014-09-24 2015-02-18 南昌大学 Si衬底上选择性生长GaN基薄膜材料的方法
CN105720088A (zh) * 2014-12-03 2016-06-29 梁辉南 硅基氮化镓外延结构及其制造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019228424A1 (zh) * 2018-05-30 2019-12-05 厦门市三安集成电路有限公司 GaN基外延结构及其制备方法
CN109830535A (zh) * 2018-11-23 2019-05-31 厦门市三安集成电路有限公司 具有纳米台阶递变层的高阻氮化镓基缓冲层及制备方法
CN109830535B (zh) * 2018-11-23 2021-04-16 厦门市三安集成电路有限公司 具有纳米台阶递变层的高阻氮化镓基缓冲层及制备方法

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