TW201910568A - 磊晶晶圓 - Google Patents

磊晶晶圓 Download PDF

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TW201910568A
TW201910568A TW106126446A TW106126446A TW201910568A TW 201910568 A TW201910568 A TW 201910568A TW 106126446 A TW106126446 A TW 106126446A TW 106126446 A TW106126446 A TW 106126446A TW 201910568 A TW201910568 A TW 201910568A
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wafer
edge region
epitaxial
side wall
epitaxial wafer
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TWI636165B (zh
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葉伯淳
蔡侃學
鄒權煒
李亨元
劉學興
何漢傑
傅毅耕
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財團法人工業技術研究院
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Priority to TW106126446A priority Critical patent/TWI636165B/zh
Priority to CN201710874142.4A priority patent/CN109390383A/zh
Priority to US15/723,390 priority patent/US10074533B1/en
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Abstract

本發明提供一種磊晶晶圓,其包括:一包含中間區及邊緣區的矽晶圓,該邊緣區環繞該中間區並具有一階梯狀剖面;以及一氮化物磊晶層,形成於該矽晶圓上;其中,該階梯狀剖面的寬度介於10與1500微米之間且其高度介於1與500微米之間。

Description

磊晶晶圓
本發明係關於磊晶晶圓,特別是一種邊緣區形成階梯狀剖面的磊晶晶圓。
由於氮化鎵(GaN)材料具有寬能帶間隙、高電子遷移率、崩潰電壓等良好性質,近年來已被廣泛應用於高功率及高頻電子元件的製作。這些氮化物材料通常是以磊晶技術成長於矽晶圓上,而形成所謂的矽上氮化物(Nitride-on-Si)磊晶晶圓(epitaxial wafer或epi-wafer)。
然而,氮化物磊晶層與矽晶圓的組成材料不同,兩者之間的晶格排列和熱膨脹係數等差異或不匹配將導致所形成磊晶晶圓的諸多缺陷,例如,彎翹(Bowing)、滑移線(Slip line)、裂痕(Crack)等。雖已有習知技術嘗試解決此問題,但成效有限;因此,有必要發展新的磊晶晶圓技術,以改善上述的問題。
本發明之一實施例提供一種磊晶晶圓,其包括:一包含中間區及邊緣區的矽晶圓,該邊緣區環繞該中間區並具有一階梯狀剖面;以及一氮化物磊晶層,形成於該矽晶圓上;其中,該階梯狀 剖面的寬度介於10與1500微米之間且其高度介於1與500微米之間。
依據本發明之一實施例的磊晶晶圓結構,可有效減少晶圓與磊晶層之間,晶格不匹配及熱膨脹係數差異所致的諸多缺陷。
100‧‧‧矽晶圓
110‧‧‧中間區
120‧‧‧邊緣區
121、123、125‧‧‧階底
122、124、126‧‧‧側牆
130‧‧‧磊晶層
W‧‧‧寬度
H‧‧‧高度
第1圖為根據本發明之一實施例之矽晶圓的結構示意圖,其中第1A圖為俯視平面圖,第1B圖為側視剖面圖,第1C圖為其邊緣區之局部放大圖。
第2A圖及第2B圖為根據本發明之一實施例之磊晶晶圓的剖面示意圖。
第3圖為習知技術所製成磊晶晶圓的表面實況圖(左圖),相較於以本發明技術所製成磊晶晶圓的表面實況圖(右圖)。
第4A圖及第4B圖為根據本發明之一實施例之矽晶圓的邊緣區之局部放大圖。
第5圖為根據本發明另一實施例之矽晶圓的邊緣區之局部放大圖。
第6圖為根據本發明另一實施例之矽晶圓的俯視平面圖。
第7圖為根據本發明又一實施例之矽晶圓的剖面圖。
為對本發明之特徵、目的及功能有更進一步的認知與瞭解, 茲配合圖式詳細說明本發明的實施例如後。在所有的說明書及圖示中,將採用相同的元件編號以指定相同或類似的元件。
在各個實施例的說明中,當一元素被描述是在另一元素之「上方/上」或「下方/下」,係指直接地或間接地在該另一元素之上或之下的情況,其可能包含設置於其間的其他元素;所謂的「直接地」係指其間並未設置其他中介元素。「上方/上」或「下方/下」等的描述係以圖式為基準進行說明,但亦包含其他可能的方向轉變。所謂的「第一」、「第二」、及「第三」係用以描述不同的元素,這些元素並不因為此類謂辭而受到限制。為了說明上的便利和明確,圖式中各元素的厚度或尺寸,係以誇張或省略或概略的方式表示,且各元素的尺寸並未完全為其實際的尺寸。
第1圖為根據本發明之一實施例之矽晶圓100的結構示意圖,其中第1A圖為其俯視平面圖,而第1B圖為其側視剖面圖。如圖所示,該矽晶圓100包含一中間區110及一邊緣區120,其中該邊緣區120為位於該矽晶圓100圓周的周邊區域,其環繞並圈圍該中間區110。該矽晶圓100可以是6吋、8吋或12吋晶圓,亦即其晶圓直徑至少為6吋。該邊緣區120的寬度介於10與1500微米之間;也就是說,該邊緣區120可視為一個將該中間區110圈圍起來的窄細環狀物。以8吋矽晶圓100為例,倘若該邊緣區120的寬度W為100微米,則該邊緣區120佔該矽晶圓100很小比例的表面面積(大約只有0.2%),而且是位於該矽晶圓100的最外邊緣,因此將不會影響該矽晶圓100的可產出晶粒數。
本發明所揭露的晶圓將用以成長磊晶層於其上,而形成所謂的磊晶晶圓,特別是晶圓與磊晶層的組成材料不同的磊晶晶圓,例如,矽上氮化物晶圓,其為氮化物磊晶層成長於矽晶圓上。在本實施例中,氮化物磊晶層130可形成於該矽晶圓100的上表面上, 如第2A圖所示,且該氮化物磊晶層130通常為多層結構,例如,其局部放大於第2B圖的GaN/Al0.25Ga0.75N/u-GaN/AlxGa1-xN/AlN;其中,GaN為氮化鎵,Al0.25Ga0.75N為氮化鎵鋁,u-GaN為無摻雜的(undoped)氮化鎵,AlxGa1-xN為鋁成分比例x的氮化鎵鋁,且AlN為氮化鋁。上述的多層結構磊晶層僅是為了說明上的方便所提供的例子,但不因此而限制本發明,其可依據所欲製作電子或光電元件而做適當的設計或調整。
由於晶圓與磊晶層的組成材料不同,兩者之間的晶格排列和熱膨脹係數等差異或不匹配將導致所形成磊晶晶圓的諸多缺陷,例如,彎翹、滑移線、裂痕等。為解決諸如上述之問題,習知技術揭露有先在標準的8吋矽晶圓上成長多層結構的應力緩衝及/或補償層(Strain buffer/compensation layers),例如第2B圖所示的AlxGa1-xN/AlN,再於上述緩衝及/或補償層上成長多層結構的氮化鎵磊晶層,例如第2B圖所示的GaN/Al0.25Ga0.75N/u-GaN,所製成的磊晶晶圓表面實況如第3圖的左側所示,在非中間區可觀察到許多滑移線及裂痕。
反觀本發明之一實施例,該邊緣區120具有一階梯狀剖面;如第1B圖右側之區域A,其局部放大圖請參閱第1C圖,該邊緣區120的剖面為一階的階梯,其包含階底121及側牆122。該階底121的寬度W即為該邊緣區120的寬度,如上所述約介於10與1500微米之間;該側牆122的高度H即為該邊緣區120與該中間區110的厚度差,約介於1與500微米之間。以製作有階底寬度W=500微米及側牆高度H=200微米的邊緣區之8吋矽晶圓為例,於其上成長相同結構的氮化鎵磊晶層,所製成的磊晶晶圓表面實況如第3圖的右側所示,可觀察到滑移線及裂痕等缺陷明顯減小,相較於沒有階梯狀邊緣區的矽晶圓。由此結果可知,矽晶圓邊緣 區的階梯狀剖面具有抑制氮化物磊晶成長過程中,滑移線增生以及釋放晶圓邊緣區應力的功效,從而降低矽上氮化物磊晶元件的製程難度並提升其元件特性。
雖然上述說明是以矽上氮化物磊晶晶圓為實施對象,但並不因此而限制本發明;只要是不同組成材料的晶圓與磊晶層所形成的磊晶晶圓,依據本發明之一實施例的階梯狀剖面的晶圓邊緣區之技術,皆可有效減少晶圓與磊晶層之間,晶格不匹配及熱膨脹係數差異所致的諸多缺陷。本發明技術適用於大尺寸晶圓,例如,直徑6吋以上;就目前的製作技術而言,矽晶圓及碳化矽(SiC)晶圓才有直徑6吋以上的商業晶圓產品,而本發明說明則以矽晶圓為主要實施例。
如第1C圖所示該邊緣區120之局部剖面放大圖,該側牆122垂直於該階底121;但本發明不以此為限,該側牆122亦可不垂直於該階底121,而使該側牆122與該階底121形成鈍角(如第4A圖所示)或銳角(如第4B圖所示)。該邊緣區12的階梯狀剖面可藉由電漿乾蝕刻(Plasma dry etching)、化學溼蝕刻(Chemical wet etching)、或機械研磨(Mechanical grinding)等習知技術來製作;特別是電漿乾蝕刻技術,可用以精確製作該側牆122與該階底121所需的夾角角度。
在其他的實施例中,該邊緣區120可以是二階以上的階梯狀剖面,例如第5圖所示之該邊緣區120局部放大圖,其包含第一階底123、第一側牆124、第二階底125、及第二側牆126,亦具有減少晶圓與磊晶層之間晶格不匹配及熱膨脹係數差異所致諸多缺陷的功效。此外,雖然如第1A圖所示,該中間區110的輪廓(或該中間區110與該邊緣區120的界面)為圓形,但本發明不以此為限;該中間區110的輪廓亦可以是多邊形或如第6圖所示的齒輪 狀(gear wheel)。除此之外,本實施例的其餘部份皆與如第1圖的描述相同,在此不再贅述。
此外,在如第1圖及第2圖所示的實施例中,該邊緣區120的階梯狀剖面係形成於該矽晶圓100的正面或上表面,且該氮化物磊晶層130成長於該矽晶圓100的正面上,但本發明不以此為限;在又一實施例中,該邊緣區120的階梯狀剖面可形成於該矽晶圓100的背面或下表面,而該氮化物磊晶層130則成長於該矽晶圓100的正面上,如第7圖所示。除此之外,本實施例的其餘部份皆與如第1圖的描述相同,在此不再贅述。
唯以上所述者,僅為本發明之較佳實施例,當不能以之限制本發明的範圍。即大凡依本發明申請專利範圍所做之均等變化及修飾,仍將不失本發明之要義所在,亦不脫離本發明之精神和範圍,故都應視為本發明的進一步實施狀況。

Claims (9)

  1. 一種磊晶晶圓,包括:一矽晶圓,包括一中間區及一邊緣區,該邊緣區環繞該中間區並具有一階梯狀剖面;以及一氮化物磊晶層,形成於該矽晶圓上;其中,該邊緣區的寬度介於10與1500微米之間且該邊緣區與該中間區的高度差介於1與500微米之間。
  2. 如申請專利範圍第1項所述之磊晶晶圓,其中,該矽晶圓具有一第一表面及一相對該第一表面的第二表面,該中間區及該邊緣區位於該第一表面上,且該氮化物磊晶層係形成於該第一表面上。
  3. 如申請專利範圍第1項所述之磊晶晶圓,其中,該矽晶圓具有一第一表面及一相對該第一表面的第二表面,該中間區及該邊緣區位於該第二表面上,且該氮化物磊晶層係形成於該第一表面上。
  4. 如申請專利範圍第1項所述之磊晶晶圓,其中,該矽晶圓的直徑至少為6吋。
  5. 如申請專利範圍第1項所述之磊晶晶圓,其中,該中間區的輪廓為圓形、多邊形、或齒輪狀。
  6. 如申請專利範圍第1項所述之磊晶晶圓,其中,該階梯狀剖面包括一階,該階具有一階底及一側牆,該側牆垂直於該階底。
  7. 如申請專利範圍第1項所述之磊晶晶圓,其中,該階梯狀剖面包括一階,該階具有一階底及一側牆,該側牆不垂直於該階底。
  8. 如申請專利範圍第1項所述之磊晶晶圓,其中,該階梯狀剖面包括二階,該二階各具有一階底及一側牆,該側牆垂直於該階底。
  9. 如申請專利範圍第1項所述之磊晶晶圓,其中,該階梯狀剖面包括二階,該二階各具有一階底及一側牆,該側牆不垂直於該階底。
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Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
US4769689A (en) * 1984-12-13 1988-09-06 American Telephone And Telegraph Company, At&T Bell Laboratories Stress relief in epitaxial wafers
US6417108B1 (en) 1998-02-04 2002-07-09 Canon Kabushiki Kaisha Semiconductor substrate and method of manufacturing the same
TW449937B (en) 1999-02-26 2001-08-11 Matsushita Electronics Corp Semiconductor device and the manufacturing method thereof
US6391748B1 (en) 2000-10-03 2002-05-21 Texas Tech University Method of epitaxial growth of high quality nitride layers on silicon substrates
US7258931B2 (en) 2002-08-29 2007-08-21 Samsung Electronics Co., Ltd. Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination
US7001791B2 (en) 2003-04-14 2006-02-21 University Of Florida GaN growth on Si using ZnO buffer layer
US7256148B2 (en) 2005-05-12 2007-08-14 International Business Machines Corporation Method for treating a wafer edge
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JP4974051B2 (ja) * 2007-02-01 2012-07-11 住友電気工業株式会社 半導体素子の製造方法
JP4395812B2 (ja) 2008-02-27 2010-01-13 住友電気工業株式会社 窒化物半導体ウエハ−加工方法
JP2009283650A (ja) * 2008-05-22 2009-12-03 Sumco Corp 半導体ウェーハの再生方法
JP5040977B2 (ja) * 2009-09-24 2012-10-03 住友電気工業株式会社 窒化物半導体基板、半導体装置およびそれらの製造方法
CN102623299A (zh) * 2011-01-31 2012-08-01 洲磊科技股份有限公司 一种晶圆接合的晶粒制程方法
KR20130062736A (ko) * 2011-12-05 2013-06-13 삼성전자주식회사 실리콘 기판, 이를 채용한 에피 구조체 및 실리콘 기판의 제조 방법
US9136430B2 (en) * 2012-08-09 2015-09-15 Samsung Electronics Co., Ltd. Semiconductor buffer structure, semiconductor device including the same, and method of manufacturing semiconductor device using semiconductor buffer structure
CN105070668B (zh) * 2015-08-06 2019-03-12 武汉新芯集成电路制造有限公司 一种晶圆级芯片封装方法

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