CN107886980A - Simulated cache device circuit - Google Patents
Simulated cache device circuit Download PDFInfo
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- CN107886980A CN107886980A CN201711141680.9A CN201711141680A CN107886980A CN 107886980 A CN107886980 A CN 107886980A CN 201711141680 A CN201711141680 A CN 201711141680A CN 107886980 A CN107886980 A CN 107886980A
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- electric capacity
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Abstract
Present disclose provides a kind of simulated cache device circuit, including：First source follower M1；And the second source follower M2, the second source follower M2With the first source follower M1Series connection, wherein, the first source follower M1Grid and the second source follower M2Gate connected in parallel be connected to signal input part, the first source follower M1Source electrode and the second source follower M2Drain electrode connection, the second source follower M2Source electrode be connected with signal output part.
Description
Technical field
A kind of this disclosure relates to simulated cache device circuit.
Background technology
With the fast development of electronic technology, simulated cache device circuit is widely used in communication, artificial intelligence and data
Signal transacting etc..Because the function that the environment and needs of application are realized becomes increasingly complex, to the knot of simulated cache device circuit
Structure design requirement more and more higher.
However, during present inventive concept is realized, inventor has found mistake of the simulated cache device circuit in data storage
Cheng Zhong, not only power consumption is big, and area occupied is big, and speed is slow, is also difficult to realize high accuracy caching under conditions of multiple read.
The content of the invention
Present disclose provides a kind of simulated cache device circuit, including：
First source follower M1, and the second source follower M2, the second source follower M2With first source
Pole follower M1Series connection, wherein, the first source follower M1Grid and the second source follower M2Grid simultaneously
Connection is connected to signal input part, the first source follower M1Source electrode and the second source follower M2Drain electrode connection,
The second source follower M2Source electrode be connected with signal output part.
Alternatively, above-mentioned first source follower M1Drain electrode be connected with high level signal, the second source follower M2
Source ground.
Alternatively, above-mentioned first source follower M1Source electrode and the first source follower M1Substrate connection, it is described
Second source follower M2Source electrode and the second source follower M2Substrate connection.
Alternatively, above-mentioned second source follower M2Threshold voltage be higher than the first source follower M1Threshold value electricity
Pressure.
Alternatively, foregoing circuit also includes：Common source transistors M as steady current source4, and gate transistor M altogether3, its
In, the steady current source common source transistors M4With the gate transistor M altogether3Series connection forms cascode structure, second source
Pole follower M2Source ground include：The second source follower M2Source electrode and the transistor M3Drain electrode connection, institute
State transistor M3Source electrode and the transistor M4Drain electrode connection, the transistor M4Source ground.
Alternatively, above-mentioned transistor M3Grid access the first bias voltage, the transistor M4Grid access it is second inclined
Put voltage.
Alternatively, foregoing circuit also includes：First electric capacity C1With the second electric capacity C2, wherein：The first electric capacity C1Upper pole
Plate and the first source follower M1Grid and the second source follower M2Grid connection, first electric capacity
C1Bottom crown and the second electric capacity C2Top crown and the signal input part connection, the second electric capacity C2Upper pole
Plate and the first electric capacity C1Bottom crown and the signal input part connection, the second electric capacity C2Bottom crown ground connection.
Alternatively, foregoing circuit also includes：Input switch K1Corresponding transistor M5, the transistor M5Source electrode and institute
State the first electric capacity C1Bottom crown and the second electric capacity C2Top crown connection, the transistor M5Drain electrode and the letter
The connection of number input.
Alternatively, foregoing circuit also includes：Switch K2Corresponding transistor M6With switch K3Corresponding transistor M7, wherein：It is described
Switch K2With switching K3Parallel connection, the transistor M6Source electrode and the transistor M7Drain electrode and the first electric capacity C1Lining
Bottom connects, the transistor M6Drain electrode and the transistor M7Source electrode and high level signal connection, the transistor M6's
Grid receives the first clock signal, the transistor M7Source electrode and the transistor M6Drain electrode and high level signal connection,
The transistor M7Drain electrode and the transistor M6Source electrode and the first electric capacity C1Substrate connection, the transistor
M7Substrate and the first electric capacity C1Bottom crown connection.
Alternatively, foregoing circuit also includes：3rd electric capacity C3And switch K2nCorresponding transistor M8, wherein：Described
Three electric C3The bottom crown of appearance receives first clock signal, the transistor M8Grid receive first clock signal
Reverse signal, the 3rd electric capacity C3Top crown and the transistor M8Source electrode connection, export second clock signal, it is described
Transistor M7Grid receive the second clock signal.
Alternatively, foregoing circuit also includes：Switch K4Corresponding transistor M9, wherein：The transistor M9Source electrode with it is described
Second source follower M2Source electrode connection, the transistor M9Drain electrode and the first electric capacity C1Bottom crown connection, work as institute
State transistor M6, the transistor M7And the transistor M9During closure, the first electric capacity C1Store second source electrode with
With device M2Voltage difference between grid source electrode.
Alternatively, foregoing circuit also includes：Switch K5Corresponding transistor M10, the second source follower M2Source electrode with
Signal output part connection includes：The second source follower M2Source electrode and the transistor M10Drain electrode connection, transistor
M10Source electrode be connected with signal output part.
Alternatively, above-mentioned transistor M6, the transistor M7And the transistor M9Disconnect, the transistor M5With institute
State transistor M10During closure, the voltage of the signal input part is identical with the magnitude of voltage of the signal output part.
Alternatively, above-mentioned transistor M10Source electrode be connected with signal output part including：The transistor M10Source electrode and
One load connection, first carrying ground.
Brief description of the drawings
In order to be more fully understood from the disclosure and its advantage, referring now to the following description with reference to accompanying drawing, wherein：
Fig. 1 diagrammatically illustrates the simulated cache device circuit diagram according to the embodiment of the present disclosure；And
Fig. 2 diagrammatically illustrates the Low dark curient bootstrap switch circuit for simulated cache device according to the embodiment of the present disclosure
Figure.
Embodiment
Hereinafter, it will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are simply exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, the description to known features and technology is eliminated, with
Avoid unnecessarily obscuring the concept of the disclosure.
Term as used herein is not intended to limit the disclosure just for the sake of description specific embodiment.Used here as
Word " one ", " one (kind) " and "the" etc. should also include " multiple ", the meaning of " a variety of ", unless context clearly refers in addition
Go out.In addition, term " comprising " as used herein, "comprising" etc. indicate the presence of the feature, step, operation and/or part,
But it is not excluded that in the presence of or other one or more features of addition, step, operation or parts.
All terms (including technology and scientific terminology) as used herein have what those skilled in the art were generally understood
Implication, unless otherwise defined.It should be noted that term used herein should be interpreted that with consistent with the context of this specification
Implication, without should by idealization or it is excessively mechanical in a manner of explain.
, in general should be according to this using in the case of being similar to that " in A, B and C etc. at least one " is such and stating
Art personnel are generally understood that the implication of the statement to make an explanation (for example, " having system at least one in A, B and C "
Should include but is not limited to individually with A, individually with B, individually with C, with A and B, with A and C, with B and C, and/or
System with A, B, C etc.).Using in the case of being similar to that " in A, B or C etc. at least one " is such and stating, it is general come
Say be generally understood that the implication of the statement to make an explanation (for example, " having in A, B or C at least according to those skilled in the art
The system of one " should include but is not limited to individually with A, individually with B, individually with C, with A and B, with A and C, with
B and C, and/or system etc. with A, B, C).It should also be understood by those skilled in the art that substantially arbitrarily represent two or more
The adversative conjunction and/or phrase of optional project, either in specification, claims or accompanying drawing, shall be construed as
Give including one of these projects, the possibility of these projects either one or two projects.For example, " A or B " should for phrase
It is understood to include " A " or " B " or " A and B " possibility.
It should be appreciated that when it is said that part ' attach ' into another part, it is another to be that the part is directly connected to
Individual part may have intermediate member.On the contrary, when it is said that part " being directly connected to " is arrived into another part, then it represents that no
Intermediate member be present.
Embodiment of the disclosure provides a kind of simulated cache device circuit, and the circuit includes：First source follower M1, with
And the second source follower M2, the second source follower M2With the first source follower M1Series connection, wherein, the first source follower
M1Grid and the second source follower M2Gate connected in parallel be connected to signal input part, the first source follower M1Source electrode
With the second source follower M2Drain electrode connection, the second source follower M2Source electrode be connected with signal output part.
A kind of simulated cache device circuit that the embodiment of the present disclosure provides, during data storage, simulated cache device electricity
The function of efficiently caching mass data is realized on road, and the circuit can be realized in low-power consumption, small area and under conditions of can repeatedly reading
The function of storing in high precision.
The simulated cache device circuit diagram according to disclosure illustrative embodiments is described below with reference to Fig. 1~Fig. 2.Its
In, Fig. 1 diagrammatically illustrates the simulated cache device circuit diagram according to the embodiment of the present disclosure, and Fig. 2 is diagrammatically illustrated according to this public affairs
Open the simulated cache device on-off circuit figure of embodiment.
Simulated cache device circuit diagram as shown in Figure 1, the circuit include：First source follower M1, and the second source electrode
Follower M2, the second source follower M2With the first source follower M1Series connection.
According to the embodiment of the present disclosure, the first source follower M1With the second source follower M2Such as can all be MOS crystal
Pipe, wherein, MOS transistor includes grid, source electrode and drain electrode etc., and MOS source followers are widely used in various functions
In circuit, for example, source follower generally may be used as high speed input-buffer, source follower can provide high input impedance,
Low output impedance and wide signal bandwidth, therefore source follower is highly suitable for designing cache circuit.
Usually used MOS transistor includes nmos pass transistor and PMOS transistor, and two kinds of transistors are all enhanced
Transistor, nmos pass transistor and PMOS transistor both can as the magnitude of voltage in the buffer unit buffer circuit in circuit or its
His various signals, can also be used as the switch of circuit.
In the disclosed embodiments, the first source follower M1Such as can be nmos pass transistor, the second source follower M2
Such as can also be nmos pass transistor.Wherein, the second source follower M2With the first source follower M1Series connection.
In the disclosed embodiments, the second source follower M2With the first source follower M1Series connection, including, the first source electrode
Follower M1Grid and the second source follower M2Gate connected in parallel be connected to signal input part, the first source follower M1
Source electrode and the second source follower M2Drain electrode connection, the second source follower M2Source electrode be connected with signal output part.
In the disclosed embodiments, the first source follower M1Grid and the second source follower M2Gate connected in parallel
It is connected to signal input part Vin, such as the first source follower M can be connected1Grid and the second source follower M2Grid
Pole, then it is parallel-connected to signal input part Vin。
In the disclosed embodiments, the first source follower M that connects is passed through1With the second source follower M2, and connect first
Source follower M1Grid and the second source follower M2Grid, be parallel-connected to the signal input part V of circuitin, make
Obtain the first source follower M1With the second source follower M2Source voltage all as same grid voltage changes, therefore can
Stably to control the second source follower M2Drain electrode and source voltage difference remain unchanged, eliminate the second source follower M2Lead
The channel-length modulation of cause, improve the linearity of source follower.
According to the embodiment of the present disclosure, the first source follower M1Drain electrode be connected with high level signal, the second source electrode follows
Device M2Source ground.
In the disclosed embodiments, high level signal for example can be as the supply voltage V of circuitDD, i.e. the first source electrode with
With device M1Drain electrode access supply voltage VDD, the second source follower M2Source ground can for example connect earth signal GND.
According to the embodiment of the present disclosure, the first source follower M1Source electrode and the first source follower M1Substrate connection, the
Two source follower M2Source electrode and the second source follower M2Substrate connection.
In the disclosed embodiments, the first source follower M1Source electrode and the first source follower M1Substrate connection, can
With the first source follower of injunction M1Source electrode and substrate between voltage be zero, the second source follower M2Source electrode and
Two source follower M2Substrate connection, can be with the second source follower of injunction M2Source electrode and substrate between voltage be zero.
In the disclosed embodiments, the voltage between the source electrode and substrate of source follower is zero, can prevent source electrode with
With the threshold voltage of device with input voltage VinChange and change, improve the linearity of source follower.
According to the embodiment of the present disclosure, the second source follower M2Threshold voltage be higher than the first source follower M1Threshold value
Voltage.
In the disclosed embodiments, the second source follower M2Can be the resistance to piezoelectric crystal of thick grid, the second source follower M2
Gate than the first source follower M1Gate it is big so that the second source follower M2Threshold voltage than first
Source follower M1Threshold voltage it is high.
For example, the second source follower M2The thick resistance to piezoelectric crystals of grid 3.3V can be used so that the second source follower M2's
Threshold voltage is than the first source follower M1Threshold voltage it is high, ensure the linearity of source follower with this, moreover it is possible to ensure source
Pole follower is operated in saturation region.
According to the embodiment of the present disclosure, the circuit also includes：Common source transistors M as steady current source4, and grid are brilliant altogether
Body pipe M3, wherein, the common source transistors M of steady current source4Gate transistor M together3Series connection forms cascode structure.
In the disclosed embodiments, transistor M3With transistor M4Series connection includes, transistor M3Source electrode and transistor M4's
Drain electrode connection.
According to the embodiment of the present disclosure, transistor M is used3With transistor M4The mode of series connection, transistor M can be maintained substantially4
Drain voltage it is constant, that is, be further ensured that circuital current is stable, so as to ensure the linearity of source follower.
According to the embodiment of the present disclosure, the second source follower M2Source ground include：Second source follower M2Source electrode
With transistor M3Drain electrode connection, transistor M3Source electrode and transistor M4Drain electrode connection, transistor M4Source ground.
In the disclosed embodiments, transistor M4Source ground, e.g. transistor M4Source electrode connection earth signal GND.
According to the embodiment of the present disclosure, transistor M3Grid access the first bias voltage Vbias_1, transistor M4Grid connect
Enter the second bias voltage Vbias_2。
In the disclosed embodiments, transistor M3Substrate connection earth signal GND, transistor M4Substrate connection earth signal
GND。
According to the embodiment of the present disclosure, the circuit also includes the first electric capacity C1With the second electric capacity C2.Wherein, the first electric capacity C1's
Top crown and the first source follower M1Grid and the second source follower M2Grid connection, the first electric capacity C1Lower pole
Plate and the second electric capacity C2Top crown and signal input part connection.
In the disclosed embodiments, the first electric capacity C1With the second electric capacity C2Such as can MOS transistor, by MOS transistor
Source electrode be connected with substrate and used as electric capacity, specifically, the first electric capacity C1With the second electric capacity C2It can be PMOS transistor.
In the disclosed embodiments, the first electric capacity C1Top crown (i.e. the substrate of MOS transistor) followed with the first source electrode
Device M1Grid and the second source follower M2Grid connection, the first electric capacity C1Bottom crown (i.e. the grid of MOS transistor)
With the second electric capacity C2Top crown (drain electrode of MOS transistor and source electrode) and signal input part VinConnection.
According to the embodiment of the present disclosure, the second electric capacity C2Top crown and the first electric capacity C1Bottom crown and signal input part
Connection, the second electric capacity C2Bottom crown ground connection.
In the disclosed embodiments, the second electric capacity C2Top crown and the first electric capacity C1Bottom crown and signal input part
VinConnection, for example, the second electric capacity C2The drain electrode of (MOS transistor) reconnects the first electric capacity C after being connected with source electrode1(MOS crystal
Pipe) grid, the second electric capacity C2The grid connection earth signal GND of (MOS transistor).
In the disclosed embodiments, the first electric capacity C1Such as can to the running parameter of each device of storage circuit, such as
The second source follower M can be stored2Magnitude of voltage between grid and source electrode, the second electric capacity C2Such as can be to storage circuit
Input parameter, such as can be with the result of calculation of storage program computing, such as the intermediate result that caching convolutional neural networks calculate.
According to the embodiment of the present disclosure, such as, it is necessary to store network parameter and middle meter in the algorithm of convolutional neural networks
Result is calculated, wherein results of intermediate calculations accounts for the overwhelming majority, and those network parameters and results of intermediate calculations are to storage speed and storage
Required precision is higher, but it does not have very harsh requirement for storage time, equally, and does not need non-volatile storage
Means, as long as ensureing in its defined storage time by use.Shared in addition, weights in convolutional neural networks be present,
This just realizes that multiple read functions propose requirement to storage buffer in certain time precision, for depositing for this kind of data
Storage, switching capacity are undoubtedly most suitable memory.
In the disclosed embodiments, MOS transistor is used as electric capacity, and bigger electricity can be obtained by smaller area
Capacitance, there is the effect of small area storage.
According to the embodiment of the present disclosure, the circuit also includes：Input switch K1Corresponding transistor M5, wherein, transistor M5's
Source electrode and the first electric capacity C1Bottom crown and the second electric capacity C2Top crown connection, transistor M5Drain electrode and signal input part
Connection.
In the disclosed embodiments, transistor M5Such as can be nmos pass transistor, transistor M5Source electrode and the first electric capacity
C1Bottom crown and the second electric capacity C2Top crown connection, transistor M5Drain electrode be connected to signal input part Vin, transistor M5's
Substrate connection earth signal GND.
According to the embodiment of the present disclosure, the circuit also includes：Switch K2Corresponding transistor M6With switch K3Corresponding transistor M7。
In the disclosed embodiments, transistor M6For example, nmos pass transistor, transistor M7For example, PMOS transistor, its
In, switch K2 is in parallel with switch K3, transistor M6Source electrode and transistor M7Drain electrode and the first electric capacity C1Substrate connection,
Transistor M6Drain electrode and transistor M7Source electrode and high level signal VDDConnection, transistor M6Grid receive the first clock
Signal K2, transistor M6Substrate connection earth signal GND.
In the disclosed embodiments, the first clock signal K2For example, there is the clock voltage of certain sequential.Such as when first
Clock signal K2 is circuit transistor M in SBR6Input voltage signal.
According to the embodiment of the present disclosure, transistor M7Source electrode and transistor M6Drain electrode and high level signal VDDConnection,
Transistor M7Drain electrode and transistor M6Source electrode and the first electric capacity C1Substrate connection, transistor M7Substrate and first electricity
Hold C1Bottom crown connection.
According to the embodiment of the present disclosure, such as transistor M6With transistor M7Parasitic capacitance, the first electric capacity C be present1Top crown
Partial pressure effects be present, by transistor M7Substrate and the first electric capacity C1Bottom crown connection, partial pressures effect is eliminated with this, carried
The linearity of high source follower.
As shown in Fig. 2 the circuit also includes：3rd electric capacity C3And switch K2nCorresponding transistor M8。
In the disclosed embodiments, such as can be using PMOS transistor as the 3rd electric capacity C3Use, transistor M8For example,
Nmos pass transistor, the 3rd electric capacity C3Bottom crown receive the first clock signal K2, transistor M8Grid receive the first clock signal
K2Reverse signal K2n, transistor M8Substrate connection earth signal GND.
In the disclosed embodiments, in order to avoid circuit is in the preparatory stage, due to transistor M7Drain voltage it is higher,
Cause transistor M7Generation electric leakage can not be fully disconnected when being used as switch, influences the precision of circuit, can be by the first clock
Signal K2It is input to the 3rd electric capacity C3Bottom crown, by the first clock signal K2Reverse signal K2nIt is input to transistor M8Grid
Pole.
In the disclosed embodiments, the 3rd electric capacity C3Top crown and transistor M8Source electrode connection, output second clock letter
Number.
According to the embodiment of the present disclosure, transistor M7Grid receive second clock signal K3。
By second clock signal K3Input transistors M7Grid, second clock signal K3Sequential and the first clock
Signal K2 is on the contrary, amplitude can arrive VDD, prevent transistor M7Leak electricity when off.
According to the embodiment of the present disclosure, the circuit also includes：Switch K4Corresponding transistor M9。
In the disclosed embodiments, transistor M9For example, nmos pass transistor, wherein, transistor M9Source electrode and the second source
Pole follower M2Source electrode connection, transistor M9Drain electrode and the first electric capacity C1Bottom crown connection, transistor M9Substrate connection
Earth signal GND.
As transistor M6, transistor M7And transistor M9During closure, the first electric capacity C1Store the second source follower M2Grid
Voltage difference between source electrode.
In the disclosed embodiments, when circuit is in the preparatory stage, transistor M6, transistor M7And transistor M9Closure
When, the first electric capacity C1Store the second source follower M2Grid and source electrode between voltage difference.
According to the embodiment of the present disclosure, the circuit also includes：Switch K5Corresponding transistor M10。
In the disclosed embodiments, transistor M10Such as can be nmos pass transistor.Wherein, the second source follower M2's
Source electrode be connected with signal output part including：Second source follower M2Source electrode and transistor M10Drain electrode connection, transistor M10
Source electrode and signal output part VoutConnection, transistor M10Substrate connection earth signal GND.
According to the embodiment of the present disclosure, when circuit is in memory phase, transistor M6, transistor M7And transistor M9Disconnect,
Transistor M5With transistor M10During closure, the voltage V of signal input partinWith signal output part VoutMagnitude of voltage it is identical.
According to the embodiment of the present disclosure, transistor M10Source electrode be connected with signal output part including：Transistor M10Source electrode with
First load CLoadConnection, the first load CLoadGround connection.
In the disclosed embodiments, by switching K5Constantly opening and closing, it is possible to achieve the multiple reading of circuit output voltage value,
And transistor M9In the second electric capacity C2With transistor M10Between, the opening and closing of switch will not cause the second electric capacity C2Electric leakage.
In the disclosed embodiments, the first electric capacity C when the error main source of the circuit is circuit input sample1Upper pole
The partial pressure effects and input sample error of plate voltage, both error symbols are identical, and the embodiment of the present disclosure can owe to adopt by input
Sample loading mode so that input sample error symbol is with partial pressure effects error symbol on the contrary, a part of loss of significance is offset, so as to improve
The caching precision of cache circuit.
According to the embodiment of the present disclosure, during data storage, efficiently caching largely counts simulated cache device circuit realiration
According to function, the circuit can realize in low-power consumption, small area and under conditions of can repeatedly reading the function of storing in high precision, simulation
Cache circuit resource is played and maximally utilized, and improves buffer efficiency.
A kind of implementation process of the embodiment of the present disclosure can be as follows：
The disclosure realizes the storage and reading of voltage by two stages of clock control.It is the preparatory stage first, switchs K2、
Switch K3And switch K4Closure, switch K1With switch K5Disconnect, at this moment electric capacity C1On store between output point and supply voltage
Difference, i.e. the second source follower M2Voltage difference between (nmos pass transistor) grid source electrode；And in memory phase, disconnection switch
K2, switch K3And switch K4, closure switch K1Input voltage is sampled, is at this moment closed again output switch K5, output voltage
Guarantee is identical with input voltage numerical value, specific as follows：
By transistor M2And M4Current equation during saturation region is operated in, due to transistor M3With transistor M4Form altogether
Source common gate structure, channel length effect can be effectively eliminated, therefore：
In formula, VGSFor the gate-source voltage of transistor, VthFor the threshold voltage of transistor, μnFor electron hole mobility,
CoxFor grid specific capacitance,For grid breadth length ratio.
Here make
As depicted in figs. 1 and 2, the M in disclosure circuit configuration2(nmos pass transistor) and M4(nmos pass transistor), has：
ID=kn2(VGS2-Vth2)2=kn4(VGS4-Vth4)2
And then it is available, within the preparatory stage, have：
kn2(VDD-Vout-Vth2)2=kn4(Vbias_2-Vth4)2
Order
Then above formula is changed into
k(VDD-Vout-Vth2)=Vbias_2-Vth4
Now, have
At this moment, for remembering the electric capacity C of current state1The voltage at both ends is
And in memory phase, have
ID=kn2(Vin+ΔV-Vout-Vth2)2=kn4(Vbias_2-Vth4)2
Bring k values, Jin Eryou into：
kVin-Vth4+Vbias_2-kVout=Vbias_2-Vth4
Obtained after simplifying
Vout=Vin
A kind of simulated environment and data of the embodiment of the present disclosure are as follows：
In order to compare simulated cache device that the disclosure proposed compared to traditional buffer (be, for example, traditional source electrode follow it is slow
Storage and unit gain buffer) advantage in simulation convolution Application of Neural Network, using Simc CMOS0.18 μm techniques,
Selection emulation tool Cadence is compared simulation analysis to circuit.
Table 1 show buffer quiescent dissipation data and compared.Supply voltage V in circuit simulationDD=1.8V, after improvement
The simulated cache device unit proposed under structural condition to the disclosure carries out the emulation of quiescent dissipation, obtains the operating current on main line
For 2 μ A, therefore the structure quiescent dissipation is 3.6 μ W.Compared to traditional buffer power consumption in milliwatt magnitude, what the disclosure proposed
Simulated cache device circuit power consumption has reached microwatt magnitude.
Table 1
| Disclosure simulated cache device | Traditional source electrode follows buffer | Unit gain buffer | |
| Power consumption | 3.6μW | 3.3mW | 7.34mW |
Table 2 show the comparison of buffer precision.Because different structure circuit input voltage memory range is different,
Therefore the precision refers to the worst error in the range of storage time and voltage caching.As can be seen that because the disclosure employs
A variety of precision optimizing methods (such as by input lack sampling (predistortion) can output result it is more accurate), the disclosure
Circuit structure caching precision on advantageously.
Table 2
Table 3 show the comparison that different circuit structures correspond to chip area.As can be seen that disclosure simulated cache device circuit
As a result of mos capacitance as parameter and the storage of input, while the open loop knot without closed loop, without operational amplifier is used
Structure, substantial amounts of area is saved.
Table 3
| Disclosure simulated cache device | Traditional source electrode follows buffer | Unit gain buffer | |
| Chip area | 935μm2 | 9700μm2 | 6059μm2 |
Table 4 show the contrast of the storage times of different circuit structures, settling time and multiple read functions.Due to tradition
Buffer architecture do not consider the storage of input value, therefore can not be suitable for convolutional neural networks to intermediate result and parameter value
Storage pooling feature requirement；In addition, within the 0.5ms times, disclosure simulated cache device equally can guarantee that the caching within 1%
Error.It is noted that due to the disclosure simulated cache device towards neutral net median and parameter value storage it is corresponding
The smaller therefore relatively low power consumption of load capacitance meet that 1pF foundation meets application demand.
Table 4
Above-mentioned several different circuit structure comparative descriptions, the simulated cache device circuit based on source follower of the disclosure
Structure is in power consumption, area, precision, cache-time and repeatedly all has preferably performance on read functions, suitable for analog roll
Parameter value and intermediate result value caching in product neutral net.
Embodiment of the disclosure is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the present disclosure.Although respectively describing each embodiment more than, but it is not intended that each reality
Use can not be advantageously combined by applying the measure in example.The scope of the present disclosure is defined by the appended claims and the equivalents thereof.Do not take off
From the scope of the present disclosure, those skilled in the art can make a variety of alternatives and modifications, and these alternatives and modifications should all fall at this
Within scope of disclosure.
Claims (14)
1. a kind of simulated cache device circuit, including：
First source follower M1；And
Second source follower M2, the second source follower M2With the first source follower M1Series connection,
Wherein, the first source follower M1Grid and the second source follower M2Gate connected in parallel be connected to letter
Number input, the first source follower M1Source electrode and the second source follower M2Drain electrode connection, second source
Pole follower M2Source electrode be connected with signal output part.
2. circuit according to claim 1, wherein：
The first source follower M1Drain electrode be connected with high level signal；
The second source follower M2Source ground.
3. circuit according to claim 1, wherein：
The first source follower M1Source electrode and the first source follower M1Substrate connection；
The second source follower M2Source electrode and the second source follower M2Substrate connection.
4. circuit according to claim 1, wherein：
The second source follower M2Threshold voltage be higher than the first source follower M1Threshold voltage.
5. circuit according to claim 2, wherein：
The circuit also includes：Common source transistors M as steady current source4, and gate transistor M altogether3, wherein, the steady
Current source common source transistors M4With the gate transistor M altogether3Series connection forms cascode structure；
The second source follower M2Source ground include：The second source follower M2Source electrode and the transistor
M3Drain electrode connection, the transistor M3Source electrode and the transistor M4Drain electrode connection, the transistor M4Source electrode connect
Ground.
6. circuit according to claim 5, wherein：
The transistor M3Grid access the first bias voltage；
The transistor M4Grid access the second bias voltage.
7. circuit according to claim 1, in addition to：First electric capacity C1With the second electric capacity C2, wherein：
The first electric capacity C1Top crown and the first source follower M1Grid and the second source follower M2
Grid connection, the first electric capacity C1Bottom crown and the second electric capacity C2Top crown and the signal input part connect
Connect；
The second electric capacity C2Top crown and the first electric capacity C1Bottom crown and the signal input part connection, it is described
Second electric capacity C2Bottom crown ground connection.
8. circuit according to claim 7, in addition to：Transistor M corresponding to input switch K15, the transistor M5Source
Pole and the first electric capacity C1Bottom crown and the second electric capacity C2Top crown connection, the transistor M5Drain electrode with
The signal input part connection.
9. circuit according to claim 8, in addition to：Switch K2Corresponding transistor M6With switch K3Corresponding transistor M7, its
In：
The switch K2With the switch K3Parallel connection, the transistor M6Source electrode and the transistor M7Drain electrode and described
One electric capacity C1Substrate connection, the transistor M6Drain electrode and the transistor M7Source electrode and high level signal connection, institute
State transistor M6Grid receive the first clock signal；
The transistor M7Source electrode and the transistor M6Drain electrode and high level signal connection, the transistor M7Leakage
Pole and the transistor M6Source electrode and the first electric capacity C1Substrate connection, the transistor M7Substrate and described the
One electric capacity C1Bottom crown connection.
10. circuit according to claim 9, in addition to：3rd electric capacity C3And switch K2nCorresponding transistor M8, wherein：
The 3rd electric capacity C3Bottom crown receive first clock signal, the transistor M8Grid receive described first
The reverse signal of clock signal；
The 3rd electric capacity C3Top crown and the transistor M8Source electrode connection, export second clock signal；
The transistor M7Grid receive the second clock signal.
11. circuit according to claim 7, in addition to：Switch K4Corresponding transistor M9, wherein：
The transistor M9Source electrode and the second source follower M2Source electrode connection, the transistor M9Drain electrode and institute
State the first electric capacity C1Bottom crown connection；
As the transistor M6, the transistor M7And the transistor M9During closure, the first electric capacity C1Store described
Two source follower M2Voltage difference between grid source electrode.
12. circuit according to claim 1, wherein：
The circuit also includes：Switch K5Corresponding transistor M10；
The second source follower M2Source electrode be connected with signal output part including：The second source follower M2Source electrode
With the transistor M10Drain electrode connection, transistor M10Source electrode be connected with signal output part.
13. circuit according to claim 7, wherein：
The transistor M6, the transistor M7And the transistor M9Disconnect, the transistor M5With the transistor M10Close
During conjunction, the voltage of the signal input part is identical with the magnitude of voltage of the signal output part.
14. circuit according to claim 12, wherein, the transistor M10Source electrode be connected with signal output part including：
The transistor M10Source electrode and first load connect, first carrying ground.
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| CN110350876A (en) * | 2019-07-29 | 2019-10-18 | 深圳市锐能微科技有限公司 | Preamplifier, difference preamplifier and integrated circuit |
| CN110601682A (en) * | 2019-08-30 | 2019-12-20 | 深圳先进技术研究院 | Switching circuit, switching device, integrator, and switched capacitor circuit |
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| CN107886980B (en) | 2020-05-05 |
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