CN107863392A - A kind of SiC mos capacitances and its manufacture method - Google Patents
A kind of SiC mos capacitances and its manufacture method Download PDFInfo
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- CN107863392A CN107863392A CN201610841740.7A CN201610841740A CN107863392A CN 107863392 A CN107863392 A CN 107863392A CN 201610841740 A CN201610841740 A CN 201610841740A CN 107863392 A CN107863392 A CN 107863392A
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910000287 alkaline earth metal oxide Inorganic materials 0.000 claims abstract description 42
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 35
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 35
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 35
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 35
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000000151 deposition Methods 0.000 claims description 35
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 30
- 230000008021 deposition Effects 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 27
- 238000000231 atomic layer deposition Methods 0.000 claims description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims description 15
- 239000001301 oxygen Substances 0.000 claims description 15
- 229910052760 oxygen Inorganic materials 0.000 claims description 15
- 238000004544 sputter deposition Methods 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 14
- 230000006835 compression Effects 0.000 claims description 14
- 238000007906 compression Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 229910052784 alkaline earth metal Inorganic materials 0.000 claims description 12
- 150000001342 alkaline earth metals Chemical class 0.000 claims description 12
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 10
- 238000001816 cooling Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 5
- 239000003513 alkali Substances 0.000 claims 1
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 239000002689 soil Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000003949 trap density measurement Methods 0.000 abstract description 4
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 23
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 20
- 238000004140 cleaning Methods 0.000 description 19
- 239000008367 deionised water Substances 0.000 description 16
- 229910021641 deionized water Inorganic materials 0.000 description 16
- 239000000463 material Substances 0.000 description 14
- 239000012530 fluid Substances 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 7
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 7
- 238000001704 evaporation Methods 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000005527 interface trap Effects 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 235000011114 ammonium hydroxide Nutrition 0.000 description 4
- 238000009835 boiling Methods 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- QAOWNCQODCNURD-UHFFFAOYSA-N sulfuric acid Substances OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
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- 230000008901 benefit Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
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- 239000007788 liquid Substances 0.000 description 3
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 229910018540 Si C Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000005516 deep trap Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000005524 hole trap Effects 0.000 description 2
- 230000037230 mobility Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000003471 anti-radiation Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
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- 238000010894 electron beam technology Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
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- 238000002347 injection Methods 0.000 description 1
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- 239000000203 mixture Substances 0.000 description 1
- 239000007773 negative electrode material Substances 0.000 description 1
- 239000007774 positive electrode material Substances 0.000 description 1
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- 230000008569 process Effects 0.000 description 1
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- 239000013049 sediment Substances 0.000 description 1
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- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
Abstract
The invention discloses a kind of high flat-band voltage stability interface state density SiC mos capacitances and its manufacture method, it is related to microelectronics technology, the SiC mos capacitances include：Negative electrode, SiC substrate, SiC epitaxial layer, II main group alkaline earth metal oxide interface layer, the SiO of arrangement are overlapped successively2Gate dielectric layer and positive electrode, the SiC mos capacitances pass through in SiC epitaxial layer and SiO2Alkaline earth metal oxide interface layer is overlapped between gate dielectric layer, relaxes interfacial stress, reduces dangling bonds, reduction interface state density and bound trap density are reached, interfacial characteristics is improved, improves the purpose of the stability of flatband capacitanse, the quality of SiC mos capacitances is improved and enhances its reliability.
Description
Technical field
The invention belongs to microelectronics technology, is related to the making of semiconductor devices, specifically relevant SiC MOS electricity
Appearance and its manufacture method.
Background technology
Typical Representative of the SiC material as third generation semiconductor, with its excellent physicochemical characteristics turn into make high temperature,
The ideal material of high power, high frequency and highly anti-radiation device.SiC material with Si represent first generation semi-conducting material and with
GaAs compares for the second generation semi-conducting material of representative has the advantages that energy gap is big, critical breakdown electric field is high, thermal conductivity is high,
Therefore the focus of microelectric technique research field is turned into for SiC material and device, the research and development of technique at present.
Compared with other wide bandgap semiconductors, one of SiC material significant advantage is that can pass through the side of hot oxygen
Method directly generates SiO on its surface2, this means that SiC material is to make the SiC MOS devices such as high-power MOS FET and IGBT
Ideal material.But the reason for hindering the development of SiC MOS devices at present have it is following some：First, the SiC compared with Si materials
Surface forms SiO by dry-oxygen oxidation2Speed it is slow, add process costs.Secondly, what is left after SiC thermal oxides is a large amount of
Interface trap so that SiO2/ SiC interface trap density generally compares SiO2/ Si high 1~2 quantity of interface trap density
Level, high interface state density can substantially reduce the mobility of carrier, cause conducting resistance to increase, power attenuation increase.Finally,
Excite a large amount of carrier injection interface traps to cause the unstable of threshold voltage under the conditions of high temperature deviated stress, device can be caused
Reliability becomes very bad, and great potential safety hazard is brought to device and circuit.
At present, industry generally use surface of SiC nitridation pretreatment, the technique such as nitrogen oxides or annealing and side
Method so that SiO2/ SiC interface state density has declined, but and SiO2/ Si interface qualities, which are compared, still no small gap.Together
When, nitrogen dosage is not easy accurately to control so that the content of the nitrogen of the uncontrollable interface of nitrogen treatment, due to nitrogen treatment meeting
Deep Level Traps and a large amount of hole traps are introduced, the stability to be worked when device is long can be influenceed on the contrary.Therefore, what research uses
New technology means are planted to improve SiO2/ SiC interfacial characteristicses, reducing interface state density and improving oxide layer reliability becomes one
The field to be received much concern in individual SiC device research.
The content of the invention
The technical problem that the technical scheme provided according to embodiments of the present invention solves is the surface of SiC nitrogen of SiC mos capacitances
Change pretreatment and introduce Deep Level Traps and a large amount of hole traps, cause SiC and SiO2Between lattice mismatch, influence capacitor
The stability to be worked when part is long.
A kind of SiC mos capacitances of high flat-band voltage stability interface state density are provided according to embodiments of the present invention, wrapped
Include：Negative electrode, SiC substrate, SiC epitaxial layer, II main group alkaline earth metal oxide interface layer, the SiO of arrangement are overlapped successively2Grid
Dielectric layer and positive electrode.
Specifically, SiC mos capacitances, including：Overlap the negative electrode of arrangement, SiC substrate, SiC extensions successively from bottom to up
Layer, II main group alkaline earth metal oxide interface layer, SiO2Gate dielectric layer and positive electrode.
The SiC substrate is provided with SiC epitaxial layer, and the SiC epitaxial layer is provided with II races alkaline earth metal oxide interface
Layer, the alkaline earth metal oxide interface layer are provided with SiO2Gate dielectric layer；
The positive and negative electrode respectively with the SiO2The surface of gate dielectric layer connects with the back side of the SiC substrate.
The SiC substrate is the SiC substrate of heavy doping, and the SiC epitaxial layer is the SiC epitaxial layer being lightly doped.
Specifically, the thickness of SiC substrate is 350 μm~400 μm, preferably 380 μm；Doping concentration is 1 × 1018~1 ×
1019cm-3, preferably 5 × 1018cm-3；The SiC epitaxial layer thickness is 5~100 μm, and doping concentration is 1 × 1015~5 ×
1016cm-3。
Specifically, the SiC substrate, SiC epitaxial layer are N-type SiC material.
Specifically, the thickness of the alkaline earth metal oxide interface layer is 0.5~5nm.
Specifically, described alkaline earth oxide selection BaO, CaO, MgO or SrO；Further is BaO or SrO.
Specifically, the SiO2The thickness of gate dielectric layer is 10nm~100nm.
Specifically, the positive electrode material is Al；The negative electrode material is Ni.
The SiC mos capacitance preparation methods provided according to embodiments of the present invention, comprise the following steps：
Step 1, one layer of SiC epitaxial layer being lightly doped is grown on the one side of SiC substrate, SiC extension prints are made and mix
Miscellaneous concentration is 1 × 1015~5 × 1016cm-3；
Step 2, one layer of alkaline earth metal oxide interface layer is grown in the SiC epitaxial layer of the SiC extensions print；
Step 3, first with the method for atomic layer deposition, one layer is deposited on the alkaline earth metal oxide interface layer
SiO2Gate dielectric layer；Then made annealing treatment in the mixed gas of oxygen and nitrogen；Then carried out in Ar compression rings border cold
But handle, be made and deposited SiO2The print of gate dielectric layer；
Step 4, it deposited SiO described respectively first with the method for magnetron sputtering2The SiO of the print of gate dielectric layer2Grid
Dielectric layer surface splash-proofing sputtering metal Al is as positive electrode, and splash-proofing sputtering metal Ni is as negative electricity on the another side of the SiC substrate
Pole；Then the print for having sputtered electrode is made annealing treatment in Ar compression rings border, completes element manufacturing.
Further, the doping concentration that SiC epitaxial layer is lightly doped described in the step 1 is 1 × 1015~5 ×
1016cm-3；The thickness that SiC epitaxial layer is lightly doped is 5~100 μm.
Further, the thickness that SiC epitaxial layer is lightly doped is 30-80 μm.
Further, the SiC substrate, SiC epitaxial layer is lightly doped is N-type SiC material.
Further, the thickness of the N-type SiC substrate is 350 μm~400 μm, is further 380 μm；Doping concentration is 1
×1018~1 × 1019cm-3cm-3, it is further 5 × 1018cm-3。
Further, growth temperature is 1500-1600 DEG C in the growth course of SiC epitaxial layer in the step 1, further
For 1570 DEG C.
Further, the thickness of alkaline earth metal oxide interface layer described in step 2 is 0.5~5nm.
Further, described alkaline earth oxide selection BaO, CaO, MgO or SrO, are further BaO or SrO.
Further, one layer of institute is grown in the SiC epitaxial layer of the SiC extensions print using the method for atomic layer deposition
The alkaline earth metal oxide interface layer stated.
Further, deposition temperature is 200 DEG C~400 DEG C during alkaline earth metal oxide interface layer is deposited；Form sediment
The product time is 1min~20min.
Further, deposition time is 3-7min during alkaline earth metal oxide interface layer is deposited.
Further, using the method for magnetically controlled sputter method or electron beam evaporation outside the SiC of the SiC extension prints
Prolong one layer of alkaline earth metal layer of surface deposition of layer, then reoxidize the described alkaline earth metal oxide interface layer of generation；
Further, the thickness of the alkaline earth metal layer is 0.3-3nm；The thickness of the alkaline earth metal oxide interface layer
For 0.5-5nm.
Further, magnetron sputtering temperature is room during depositing a floor alkaline earth metal layer using magnetically controlled sputter method
Temperature, preferably 20-35 DEG C, further is 25 DEG C；The magnetron sputtering time is 1-5min, preferably 1min.
Further, evaporating temperature is during depositing one layer of alkaline earth metal layer using the method for electron beam evaporation
1000-1500 DEG C, be further 1000 DEG C；Evaporation time is 1-5min, is further 1min.
Further, the oxidizing temperature that oxidation generates the alkaline earth metal oxide interface layer is 200 DEG C~400 DEG C.
Further, the oxidizing temperature that oxidation generates the alkaline earth metal oxide interface layer is 300 DEG C.
Further, the oxidation generation alkaline earth metal oxide interface layer is carried out in dry oxygen atmosphere.
Further, in addition to step 2A), to SiC epitaxial layer carry out cleaning treatment after, then in the above grow alkaline earth gold
Belong to oxide interface layer.
Further, the cleaning treatment includes the step of order below is carried out：
2A-1, with deionized water N-type SiC epitaxial wafers are cleaned by ultrasonic；
2A-2, cleaned with the concentrated sulfuric acid, be heated to smoldering, after boiling 10min, soak 30min minutes；
2A-3, with deionized water rinsing surface several times；
2A-4, use H2O、H2O25min are soaked for 5: 1: 1 80 DEG C of water-baths of No. 1 cleaning fluid with ammoniacal liquor ratio, and use hydrogen fluoride
After solution cleaning, deionized water rinsing surface is several times；
2A-5, H is used again2O、H2O25min are soaked with 80 DEG C of water-baths of No. 2 cleaning fluids that HCl ratios are 6: 1: 1, and with being fluorinated
After hydrogen solution cleaning, deionized water rinsing surface several times, is dried finally by infrared lamp.
Further, SiO described in step 32The thickness of gate dielectric layer is 10nm~100nm, is further 50~80nm.
Further, the SiO is being deposited2Deposition temperature is 200 DEG C~400 DEG C during gate dielectric layer；During deposit
Between be 0.5h~5h.
Further, the SiO is being deposited2Deposition temperature is 300 DEG C during gate dielectric layer；Deposition time is 2-
3h。
Further, the ratio between volume of oxygen and nitrogen is 10 in the mixed gas of the oxygen and nitrogen:90.
Further, the speed that cooled described in the step 3 in Ar compression rings border during cooling treatment be 3~
5 DEG C/min, be further 5 DEG C/min.
Further, the temperature of the annealing is 950~1050 DEG C；The annealing time is 1~2h.
Further, the temperature of the annealing is 1000 ± 5 DEG C；The annealing time is 2h.
Further, it is 350~400 DEG C that temperature is made annealing treatment described in step 4；The annealing time is 25~30min.
Further, the annealing temperature is 400 ± 5 DEG C；The annealing time is 30min.
Technical scheme provided in an embodiment of the present invention has the advantages that：
1st, due to grown one layer of II main group alkaline earth oxide on SiC epitaxial wafers as SiC and SiO2Between
Boundary layer, the boundary layer alleviates SiC and SiO in traditional Si C mos capacitances2Between lattice mismatch, so as to relax interface
Stress, dangling bonds are reduced, improve interfacial characteristics；
2nd, due to introducing alkaline earth metal oxide interface layer, it instead of SiC and SiO in traditional Si C mos capacitances2Between
Transition zone rich in a large amount of suboxide SiOxCy, greatly reduce the density of nearly interface trap, will cause MOS high temperature,
Under high pressure extreme operating conditions, cause the flatband voltage shift of mos capacitance smaller；
3rd, due to growing oxide layer by the way of deposit so that the speed of growth of oxide layer is improved, and after warp
The deposit after annealing processing of sequence so that the quality of oxide layer of growth is more preferable；
4th, due in SiC epitaxial layer and SiO2Alkaline earth metal oxide interface layer is introduced between gate dielectric layer, is reduced
SiC mos capacitance interface state densities, increase MOS channel mobilities, reduce gate leak current, further increase gate dielectric layer can
By property and the flat-band voltage stability of SiC mos capacitances.
Brief description of the drawings
Fig. 1 is the structural representation of SiC mos capacitances provided in an embodiment of the present invention；
Fig. 2 is the fabrication processing figure of SiC mos capacitances provided in an embodiment of the present invention.
Description of reference numerals：
101st, SiC substrate；102nd, SiC epitaxial layer；201st, alkaline earth metal oxide interface layer；202、SiO2Gate dielectric layer；
301st, positive electrode；302nd, negative electrode.
Embodiment
Below in conjunction with accompanying drawing to a preferred embodiment of the present invention will be described in detail, it will be appreciated that described below is excellent
Select embodiment to be merely to illustrate and explain the present invention, be not intended to limit the present invention.
Fig. 1 is the schematic diagram of SiC mos capacitances provided in an embodiment of the present invention, as shown in figure 1, the embodiment of the present invention
SiC mos capacitances include：SiC substrate 101, SiC epitaxial layer 102, II major element alkaline earth metal oxide interface layer 201,
SiO2Gate dielectric layer (SiO2Dielectric layer or SiO2Oxide layer) 202 and positive and negative electrode 301,302.
Such as Fig. 1, high flat-band voltage stability interface state density SiC mos capacitances provided in an embodiment of the present invention, in SiC
The side of substrate 101 from the inside to the outside successively close overlapping arrangement SiC epitaxial layer 102, alkaline earth metal oxide interface layer 201,
SiO2Gate dielectric layer 202 and positive electrode 301, negative electrode 302 is closely overlapped in the opposite side of SiC substrate 101.
Specifically, SiC substrate 101 is heavy doping SiC substrate, the thickness of SiC substrate is 350-400 μm, doping concentration 1
×1018~1 × 1019cm-3；SiC epitaxial layer 102 is the SiC epitaxial layer gently mixed, and the thickness of SiC epitaxial layer 102 is 5~100 μm, is mixed
Miscellaneous concentration is 1 × 1015~5 × 1016cm-3, the thickness of alkaline earth metal oxide interface layer 201 is 0.3~5nm, SiO2Gate medium
The thickness of layer 202 is 10nm~100nm.
Alkaline earth metal oxide interface layer alleviates SiC and SiO2Between lattice mismatch, relax interfacial stress, reduce outstanding
Key is hung, interface state density and bound trap density is reduced, improves interfacial characteristics, improve the stability of flatband capacitanse, carry
The high quality of SiC mos capacitances simultaneously enhances its reliability.
Fig. 2 is the fabrication processing figure of SiC mos capacitances provided in an embodiment of the present invention, as shown in Fig. 2 including as follows
Two kinds of embodiments：
Embodiment 1
Step 1, N-type SiC epitaxial layer is grown.
It it is 380 μm by thickness, doping concentration is 5 × 1018cm-3N-type SiC substrate material be placed in SiC epitaxial growth reactions
In stove, one layer of N-type SiC epitaxial layer is grown on one side, N-type SiC epitaxial wafers is made, wherein in SiC epitaxial furnaces
1570 DEG C of temperature, doping concentration be 5 × 1015cm-3, until the thickness of the SiC epitaxial layer of growth is 30 μm.
Using thickness as 380 μm in the embodiment of the present invention, doping concentration is 5 × 1018cm-3N-type SiC substrate exemplified by carry out
Illustrate, other thickness are 350-400 μm；Doping concentration is 1 × 1018~1 × 1019cm-3N-type SiC substrate material be applied to
The present invention.
Step 2, the N-type SiC epitaxial wafers grown are pre-processed.
2.1 are cleaned by ultrasonic with deionized water to N-type SiC epitaxial wafers；
2.2 are cleaned with the concentrated sulfuric acid, are heated to smoldering, and after boiling 10min, soak 30min minutes；
2.3 use deionized water rinsing surface several times；
2.4 use H2O、H2O25min are soaked for 5: 1: 1 80 DEG C of water-baths of No. 1 cleaning fluid with ammoniacal liquor ratio, and it is molten with hydrogen fluoride
After liquid cleaning, deionized water rinsing surface is several times；
2.5 use H again2O、H2O25min are soaked for 6: 1: 1 80 DEG C of water-baths of No. 2 cleaning fluids with HCl ratios, and use hydrogen fluoride
After solution cleaning, deionized water rinsing surface several times, is dried finally by infrared lamp.
Except it is above-mentioned to the preprocess method of N-type SiC epitaxial wafers in addition to, the cleaning of the conventional epitaxial wafer of other in this area
Pretreatment mode is applied to the present invention.
Step 3, alkaline earth metal oxide interface layer is grown.
Pretreated N-type SiC epitaxial wafers are placed in atomic layer deposition apparatus, using atomic layer deposition (also known as atom
Layer deposition, Atomic layer deposition, ALD) method deposit the thick BaO boundary layers of one layer of 1nm, deposition temperature is
300 DEG C, deposition time 5min；
The thickness of the alkaline-earth metal oxide layer of atomic layer deposition strategy deposit is used to enter by taking 1nm as an example in the embodiment of the present invention
Row explanation, other thickness 0.5-5nm are applied to the present invention；Atomic layer deposition strategy deposit alkaline-earth metal oxide layer temperature with
300 DEG C, the time illustrated by taking 5min as an example, 200-400 DEG C of other deposition temperatures, deposition time 1-20min be applied to this
Invention.
Step 4, deposit growth SiO2Gate dielectric layer and annealing.
4.1 deposit the thick SiO of one layer of 50nm using the method for atomic layer deposition (ALD) on BaO boundary layers2Gate medium
Layer, deposition temperature are 300 DEG C, deposition time 2h；
Print after 4.2 pairs of deposits, under conditions of temperature is 1000 ± 5 DEG C, in the mixed gas of oxygen and nitrogen
2h is made annealing treatment, wherein the ratio between volume of oxygen and nitrogen is 10:90；Then cooling treatment is carried out in Ar compression rings border again,
Room temperature is cooled to, cooldown rate is 5 DEG C/min；
Deposit growth SiO in the embodiment of the present invention2During gate dielectric layer deposition temperature with 300 DEG C, deposition time with 2h
Exemplified by illustrate, 200-400 DEG C of other deposition temperatures, deposition time 0.5-5h be applied to the present invention；The SiO of deposit2Grid
The thickness of dielectric layer illustrates by taking 1nm as an example, and other thickness 0.5-5nm is applied to the present invention；Make annealing treatment temperature with
Illustrated exemplified by 1000 ± 5 DEG C, such as 950-1050 DEG C of other temperature are applied to the present invention；The time is made annealing treatment by taking 2h as an example
Illustrate, other 1-2h are applied to the present invention.
Step 5, splash-proofing sputtering metal electrode and annealing.
5.1 deposited SiO2On SiC epitaxial wafers after gate dielectric layer, using the method for magnetron sputtering in gate medium SiO2
Surface splash-proofing sputtering metal Al as positive electrode, SiC substrate back spatter W metal as negative electrode；
5.2 are placed in the print after sputtering electrode in the Ar compression rings border that temperature is 400 ± 5 DEG C the 30min that anneals, and complete whole
The making of electric capacity.
The temperature that made annealing treatment in Ar compression rings border in the embodiment of the present invention after sputtering electrode is carried out exemplified by 400 ± 5 DEG C
Illustrate, such as 350-400 DEG C of other temperature are applied to the present invention；The annealing time illustrates by taking 30min as an example, other
25-30min is applied to the present invention.
Embodiment 2
During depositing growth alkaline earth metal oxide interface layer except step 3, deposition temperature is 200 DEG C, deposition time
For 7min；The thickness for depositing the BaO boundary layers of growth is 1nm；The cooldown rate of cooling treatment is 3 DEG C/min in Ar compression rings border
Outside, remaining is same as Example 1.
Embodiment 3
During depositing growth alkaline earth metal oxide interface layer except step 3, deposition temperature is 400 DEG C, deposition time
Outside 3min, remaining is same as Example 1.
Embodiment 4
Step 1, N-type SiC epitaxial layer is grown.
It it is 380 μm by thickness, doping concentration is 5 × 1018cm-3N-type SiC substrate material be placed in SiC epitaxial growth reactions
In stove, one layer of N-type SiC epitaxial layer is grown on one side, N-type SiC epitaxial wafers is made, wherein in SiC epitaxial furnaces
1570 DEG C of temperature, doping concentration be 5 × 1015cm-3, until the thickness of the SiC epitaxial layer of growth is 80 μm.
Step 2, the N-type SiC epitaxial wafers grown are pre-processed.
2.1 are cleaned by ultrasonic with deionized water to N-type SiC epitaxial wafers；
2.2 are cleaned with the concentrated sulfuric acid, are heated to smoldering, and after boiling 10min, soak 30min minutes；
2.3 use deionized water rinsing surface several times；
2.4 use H2O、H2O25min are soaked for 5: 1: 1 80 DEG C of water-baths of No. 1 cleaning fluid with ammoniacal liquor ratio, and it is molten with hydrogen fluoride
After liquid cleaning, deionized water rinsing surface is several times；
2.5 use H again2O、H2O25min are soaked for 6: 1: 1 80 DEG C of water-baths of No. 2 cleaning fluids with HCl ratios, and use hydrogen fluoride
After solution cleaning, deionized water rinsing surface several times, is dried finally by infrared lamp.
Step 3, alkaline earth metal oxide interface layer is grown.
3.1 are placed in pretreated N-type SiC epitaxial wafers in magnetic control sputtering device, using the method for magnetron sputtering outside SiC
The surface for prolonging layer sputters the thick alkaline-earth metal Sr layers of one layer of 3nm, and sputter temperature is 25 DEG C, deposition time 1min；
The mistake of one layer of alkaline-earth metal Sr layer is sputtered on the surface of SiC epitaxial layer using magnetron sputtering method in the embodiment of the present invention
Cheng Zhong, sputter temperature are illustrated exemplified by 25 DEG C, and such as 20-35 DEG C of other temperature room temperatures are applied to the present invention；Deposition time
Illustrated by taking 1min as an example, other times 1-5min is applied to the present invention.
3.2 are placed in the SiC epitaxial wafers for having sputtered alkaline-earth metal Sr in oxidation furnace, are 300 DEG C ± 5 DEG C in oxidizing temperature
Under the conditions of, the SrO boundary layers that generation a layer thickness is 5nm are aoxidized in dry oxygen atmosphere.
Step 4, deposit growth SiO2Gate dielectric layer and annealing.
4.1 in atomic layer deposition apparatus, and one layer of 80nm thickness is deposited on SrO boundary layers using the method for atomic layer deposition
SiO2Gate dielectric layer, deposition temperature are 300 DEG C, deposition time 3h；
Print after 4.2 pairs of deposits, under conditions of temperature is 1000 ± 5 DEG C, in the mixed gas of oxygen and nitrogen
2h is made annealing treatment, wherein the ratio between volume of oxygen and nitrogen is 10:90；Then the cooling treatment in Ar compression rings border, is cooled to
Room temperature, cooldown rate are 5 DEG C/min；
Step 5, splash-proofing sputtering metal electrode and annealing.
5.1 deposited SiO2On SiC epitaxial wafers after gate dielectric layer, using the method for magnetron sputtering in gate medium SiO2
Surface splash-proofing sputtering metal Al as positive electrode, SiC epitaxial wafers back spatter W metal as negative electrode；
5.2 are placed in the print after sputtering electrode in the Ar compression rings border that temperature is 400 ± 5 DEG C the 30min that anneals, and complete whole
The making of electric capacity.
Embodiment 5
Step 1, N-type SiC epitaxial layer is grown.
It it is 380 μm by thickness, doping concentration is 5 × 1018cm-3N-type SiC substrate material be placed in SiC epitaxial growth reactions
In stove, one layer of N-type SiC epitaxial layer is grown on one side, N-type SiC epitaxial wafers is made, wherein in SiC epitaxial furnaces
1570 DEG C of temperature, doping concentration be 1 × 1016cm-3, until the thickness of the SiC epitaxial layer of growth is 80 μm.
Step 2, the N-type SiC epitaxial wafers grown are pre-processed.
2.1 are cleaned by ultrasonic with deionized water to N-type SiC epitaxial wafers；
2.2 are cleaned with the concentrated sulfuric acid, are heated to smoldering, and after boiling 10min, soak 30min minutes；
2.3 use deionized water rinsing surface several times；
2.4 use H2O、H2O25min are soaked for 5: 1: 1 80 DEG C of water-baths of No. 1 cleaning fluid with ammoniacal liquor ratio, and it is molten with hydrogen fluoride
After liquid cleaning, deionized water rinsing surface is several times；
2.5 use H again2O、H2O25min are soaked for 6: 1: 1 80 DEG C of water-baths of No. 2 cleaning fluids with HCl ratios, and use hydrogen fluoride
After solution cleaning, deionized water rinsing surface several times, is dried finally by infrared lamp.
Step 3, alkaline earth metal oxide interface layer is grown.
3.1 are placed in pretreated N-type SiC epitaxial wafers in electron beam evaporation equipment, using the method for electron beam evaporation
The thick alkaline-earth metal Sr layers of one layer of 3nm are grown in the surface coating of SiC epitaxial layer, evaporating temperature is 1000 DEG C, and evaporation time is
1min；
One layer of alkaline-earth metal Sr is grown using surface coating of the electron-beam vapor deposition method in SiC epitaxial layer in the embodiment of the present invention
During layer, evaporating temperature is illustrated exemplified by 1000 DEG C, and such as 1000-1500 DEG C of other temperature room temperatures are applied to this hair
It is bright；Evaporation time illustrates by taking 1min as an example, and other times 1-5min is applied to the present invention.
The 3.2 SiC epitaxial wafers that plated film grown to alkaline-earth metal Sr are placed in oxidation furnace, are 300 DEG C ± 5 in oxidizing temperature
Under conditions of DEG C, the SrO boundary layers that generation a layer thickness is 5nm are aoxidized in dry oxygen atmosphere.
Step 4, deposit growth SiO2Gate dielectric layer and annealing.
4.1 in atomic layer deposition apparatus, and one layer of 80nm thickness is deposited on SrO boundary layers using the method for atomic layer deposition
SiO2Gate dielectric layer, deposition temperature are 300 DEG C, deposition time 3h；
Print after 4.2 pairs of deposits, under conditions of temperature is 1000 ± 5 DEG C, in the mixed gas of oxygen and nitrogen
2h is made annealing treatment, wherein the ratio between volume of oxygen and nitrogen is 10:90；Then the cooling treatment in Ar compression rings border, is cooled to
Room temperature, cooldown rate are 5 DEG C/min；
Step 5, splash-proofing sputtering metal electrode and annealing.
5.1 deposited SiO2On SiC epitaxial wafers after gate dielectric layer, using the method for magnetron sputtering in gate medium SiO2
Surface splash-proofing sputtering metal Al as positive electrode, SiC epitaxial wafers back spatter W metal as negative electrode；
5.2 are placed in the print after sputtering electrode in the Ar compression rings border that temperature is 400 ± 5 DEG C the 30min that anneals, and complete whole
The making of electric capacity.
Although the present invention is described in detail above, the invention is not restricted to this, those skilled in the art of the present technique
Various modifications can be carried out according to the principle of the present invention.Therefore, all modifications made according to the principle of the invention, all should be understood to
Fall into protection scope of the present invention.
Claims (10)
1. a kind of SiC mos capacitances, including negative electrode, SiC substrate, SiC epitaxial layer, the alkaline-earth metal oxide of arrangement are overlapped successively
Thing boundary layer, SiO2Gate dielectric layer and positive electrode.
2. SiC mos capacitances according to claim 1, the SiC epitaxial layer thickness is 5~100 μm, doping concentration 1
×1015~5 × 1016cm-3。
3. SiC mos capacitances according to claim 1, the thickness of the alkaline earth metal oxide interface layer for 0.5~
5nm。
4. SiC mos capacitances according to claim 1, SiO2The thickness of gate dielectric layer is 10nm~100nm.
5. a kind of manufacture method of SiC mos capacitances, comprises the following steps：
Step 1, one layer of SiC epitaxial layer being lightly doped is grown on the side of SiC substrate, SiC extension prints are made；
Step 2, one layer of alkaline earth metal oxide interface layer is grown in the SiC epitaxial layer of the SiC extensions print；
Step 3, one layer of SiO is deposited on the alkaline earth metal oxide interface layer first with the method for atomic layer deposition2Grid are situated between
Matter layer；Then made annealing treatment in the mixed gas of oxygen and nitrogen；Then cooling treatment is carried out in Ar compression rings border, is made
SiO must be deposited2The print of gate dielectric layer；
Step 4, it deposited SiO described respectively first with the method for magnetron sputtering2The SiO of the print of gate dielectric layer2Gate medium
Layer surface splash-proofing sputtering metal Al is as positive electrode, and splash-proofing sputtering metal Ni is as negative electrode on the another side of the SiC substrate；Then
The print for having sputtered electrode is made annealing treatment in Ar compression rings border, produced.
6. the manufacture method of SiC mos capacitances according to claim 5, using the method for atomic layer deposition in the SiC
The described alkaline earth metal oxide interface layer of epi-layer surface deposit, wherein deposition temperature are 200 DEG C~400 DEG C, deposition time
For 1min~20min.
7. the manufacture method of SiC mos capacitances according to claim 6, the alkali grown using atomic layer deposition method
The thickness of soil metal oxide boundary layer is 0.5~5nm.
8. the manufacture method of SiC mos capacitances according to claim 5, first with magnetron sputtering or electron beam evaporation
Method in described one layer of alkaline earth metal layer of SiC epitaxial layer surface deposition, then reoxidize the described alkaline-earth metal oxide of generation
Thing boundary layer.
9. the manufacture method of SiC mos capacitances according to claim 8, the thickness of the alkaline earth metal layer is 0.3-3nm；
The thickness of the alkaline earth metal oxide interface layer is 0.5-5nm.
Carried out 10. the manufacture method of SiC mos capacitances according to claim 5, described in step 3 in Ar compression rings border cold
But the speed that cools handled is 3-5 DEG C/min.
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