CN107851641B - 高功率应用中的三维整体模塑功率电子模块及其方法 - Google Patents

高功率应用中的三维整体模塑功率电子模块及其方法 Download PDF

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CN107851641B
CN107851641B CN201680000109.2A CN201680000109A CN107851641B CN 107851641 B CN107851641 B CN 107851641B CN 201680000109 A CN201680000109 A CN 201680000109A CN 107851641 B CN107851641 B CN 107851641B
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CN107851641A (zh
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高子阳
吕雅
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Hong Kong Applied Science and Technology Research Institute ASTRI
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Abstract

本发明提供的功率电子封装包括：第一基板、与第一基板反向安置的第二基板、一个或多个安置在基板之间的芯片、和至少三个垫块。垫块控制着功率电子封装的高度变化，并保护芯片和其它电子组件免遭过度压力。垫块高度是根据芯片高度、连接芯片到顶基板的焊块高度、和连接芯片到底基板的焊块高度而确定的。

Description

高功率应用中的三维整体模塑功率电子模块及其方法
【发明领域】
本发明涉及一种功率电子封装或一种整体注塑功率电子模块。
【背景技术】
功率半导体芯片用于许多高功率应用，如混合动力电动汽车和其它运输及能源系统。功率半导体芯片如金属氧化物半导体场效应晶体管(MOSFET)、绝缘栅双极晶体管(IGBT)、和二极管会产生大量的热。结果，当这些半导体芯片置入到封装内时，期望能有效且快速地将这些芯片产生的热散发出去。这种功率半导体芯片的封装需要满足严格的性能要求，如在一个很长的服务寿命期间提供可靠的高功率。此外，功率电子封装为芯片和其它内置组件提供电子互连、散热、和机械支持。
为了满足高功率封装的要求，期望能提高可靠性和散热性能。
【附图说明】
图1显示本发明一个示范实施例的功率电子封装的侧视图。
图2显示本发明一个示范实施例的功率电子封装的透明视图。
图3显示本发明一个示范实施例的确定功率电子封装中垫块厚度的方法。
图4显示本发明一个示范实施例的制作功率电子封装的方法。
图5显示本发明一个示范实施例的制作功率电子封装的系统。
图6A显示本发明一个示范实施例的功率电子封装的侧视图。
图6B显示本发明一个示范实施例的功率电子封装的侧视图。
【发明概述】
一个示范实施例的功率电子封装包括：第一基板、与第一基板反向安置的第二基板、一个或多个安置在基板之间的芯片、以及至少三个垫块。垫块控制着功率电子封装的高度变化，并保护芯片和其它电子组件免遭过度压力。垫块高度是根据芯片高度、连接芯片到顶基板的焊块高度上、以及连接芯片到底基板的焊块高度而确定的。
其它示范实施例将在以下讨论。
【发明详述】
本发明示范实施例涉及功率电子封装的装置和方法，该功率电子封装包括一个或多个安置在内的芯片，且能有效散热。
一个示范实施例的功率电子封装包括：一个顶基板和一个与顶基板相反安置的底基板。该功率电子封装为多个夹在顶基板和底基板之间的高功率芯片提供电子互连、散热和机械支持。该功率电子封装还包括垫块，每个垫块的第一端接触顶基板，其第二端接触底基板。垫块高度是根据芯片高度、将芯片键合到顶基板的焊块(solderblock)高度、将芯片键合到底基板的焊基(solderbase)高度而确定的。
垫块位于顶基板和底基板之间，能根据每个封装里特定芯片而提供一个机制以控制功率电子封装的高度。垫块高度是根据芯片高度、使用的焊块数量、以及在此讨论的其它标准进行定制和设计的。因此，功率电子封装的高度变化是由该垫块控制的。
在一个示范实施例里，在芯片的顶表面和顶基板之间有多个焊块，在芯片的底表面和底基板之间有多个焊基。焊块和焊基为芯片提供电子路径，以便连接到顶基板和底基板。
在一个示范实施例里，垫块高度是根据基板和夹在其间的芯片的传热属性而确定的，使得高功率芯片产生的热能够有效地散发出去。功率电子封装的高度变化被垫块精确地控制在小于0.1mm，从而降低焊块的机械压力和崩塌率。
在一个示范实施例里，垫块被垫在功率电子封装的周围，或靠近功率电子封装的一个或多个角，以便从芯片和焊块转移负载，从而降低功率电子封装里电子组件上的机械压力。
图1显示一个功率电子封装或功率电子模块100的侧视图。功率电子封装100包括多个晶片或芯片130，其位于或夹在顶基板或第一直接敷铜(DBC)基板110和底基板或第二DBC基板120之间。
例如，DBC顶基板110包括一个陶瓷基板110B和两层铜层110A和110C，两层铜层键合在陶瓷基板110B的顶面和底面上。DBC顶基板110有一个图案化的内表面118，其包括第一钝化区或非导电区114和第一导电区116。
DBC底基板120也有一个图案化的内表面128，其包括第二钝化区或非导电区124和第二导电区126。例如，通过将铜氧化而在DBC底基板和DBC顶基板的内表面上形成钝化区，而非氧化区则被确定为内表面118和128上的电子连接路径和可焊接区。
在芯片130的顶表面和DBC顶基板110的第一导电区116之间有第一多个焊块或焊球112，在芯片130的底表面和DBC底基板120的第二导电区126之间有第二多个焊块或焊基122。
一个或多个垫块140安置在DBC顶基板110和第二DBC基板120之间。每个垫块有第一端140A和第二端140B。第一端140A接触或紧靠DBC顶基板110的第一钝化区114，第二端140B接触或紧靠DBC底基板120的第二钝化区124。
在一个示范实施例里，垫块140的高度等于芯片130的高度、第一多个焊块112的高度、第二多个焊块122的高度的总和。功率电子封装的高度变化被精确控制到小于0.1mm。小公差的高度变化能够降低在注塑过程中产生在焊块和芯片上的机械压力，从而减小焊块的崩塌率。
如图1所示，功率电子封装100还包括第三多个焊块或焊球150，其接触DBC顶基板110的第一导电区116，并接触DBC底基板120的第二导电区126，以便电连接DBC顶基板和DBC底基板。在一个示范实施例里，焊球高度是焊球宽度的60％到80％。
如图1所示，功率电子封装100也包括一种注塑化合物或封装剂160，其通过一个整体模塑成型过程或传递模塑成型过程被注入填充在DBC顶基板和DBC底基板之间的空隙里。例如，一种硅氧树脂(silicone)或环氧树脂模塑化合物(EMC)被注入到封装内的空腔里，以提供一个锁定机制，从而提高封装的可靠性。例如，基板110和120的外表面或其部分外表面没有被模塑化合物覆盖，以便有效地将热量散发到周围空气中。
如图1所示，功率电子封装100还包括引线框架170，其被键合到或连接到DBC底基板上，以形成到外部设备的电子连接。
图2显示一个功率电子封装或功率电子模块200的透明视图。功率电子封装200包括多个晶片或芯片230，其安装在焊块或焊基222上。芯片的安置或排列要使得每个芯片都与焊基电接触。多个垫块240被垫在功率电子封装的周围。例如，垫块可以位于靠近功率电子封装的角上。垫块是由硅制成，其横截面形状是圆形或多边形。
如图2所示，功率电子封装200还包括多个非导电区或钝化区214以及导电区216。导电区216为安装在焊基222上的芯片230设定电子连接路径，并设定可焊接区。
如图2所示，功率电子封装200还包括多个焊块或焊球250，其接触导电区216。在一个示范实施例里，焊球高度是焊球宽度的60％到80％。
如图2所示，功率电子封装200还包括一种用于整体模塑过程或传递模塑过程的模塑化合物或封装剂260。例如，一种硅氧树脂或环氧树脂模塑化合物(EMC)被注入填充到封装内的空腔里，以提供一个锁定机制，从而提高封装的可靠性。
图3显示一个示范实施例的确定垫块厚度的方法。
在步骤310，提供第一DBC基板，其有非导电区和导电区。例如，通过一个钝化过程确定非导电区，沿着一个预定路径将第一DBC基板上的铜氧化。
在步骤320，提供第二DBC基板，其有支撑第一芯片的第一焊基、支撑第二芯片的第二焊基、非导电区和导电区。例如，焊基的尺寸是通过切割硅晶圆而预先设定或预先制成的。焊基通过焊锡膏而连接到第二DBC基板上，焊锡膏是被印制在第二DBC基板上的。因此，多个芯片被安装在焊基上。
在步骤330，通过分析第一和第二DBC基板以及第一芯片的传热属性和可靠性，确定安置在第一芯片和第一和第二DBC基板之间的第一焊块厚度和第一焊基厚度。
例如，进行蠕变分析(creepanalysis)和热分析来确定连接到第一和第二DBC基板和第一芯片的焊块的疲劳寿命。蠕变是指焊料在机械压力影响下移动或变形的倾向。
再如，进行热分析和模拟来确定第一和第二DBC基板和第一芯片的热阻抗。热分析是指材料属性受温度变化后的变化研究。例如，进行数字建模和有限元分析模拟，考虑不同的几何参数和材料特性后，可以确定第一芯片和第二基板连接处之间的热阻抗。根据热设计要求，可以调整第二焊块的厚度和形状。
在一个示范实施例里，第一焊基的厚度是根据功率电子封装的设计要求而通过软件建模和模拟来确定的。再如，位于第一芯片和第一DBC基板之间的第一焊块的厚度是根据蠕变分析和热分析结果以及第一焊块的类型及其相应位置开口来确定的。例如，疲劳寿命和热阻抗之间需要进行权衡。所以，根据功率电子封装的标准和设计要求，在这两个参数之间选择一个平衡点。
在步骤340，将第一芯片厚度和第一焊基厚度以及第一焊块厚度加在一起，计算得到第一高度。
在步骤350，通过分析第一和第二DBC基板以及第二芯片的传热属性和可靠性，确定位于第二芯片和第一DBC基板之间的第二焊基厚度和第二焊块厚度。例如，进行蠕变分析和热分析，以确定连接到第一、第二DBC基板和第二芯片的焊块的疲劳寿命。再如，进行热分析和模拟以确定第一、第二DBC基板和第二芯片的热阻抗。然后，根据设计要求进行软件建模和模拟而确定第二焊基厚度。再如，根据蠕变分析和热分析结果以及第二焊块的类型及其相应位置开口，而确定位于第二芯片和第一DBC基板之间的第二焊板厚度。
在步骤360，将第二焊基厚度和第二芯片厚度以及第二焊块厚度加在一起，计算得到第二高度。
在步骤370，当第一高度和第二高度之间差值小于0.1mm时，对第一高度和第二高度取均值，确定一个优化高度。例如，如果在步骤340计算出的第一高度是4mm，而在步骤360计算出的第二高度是4.04mm，那么优化高度被确定为4.02mm。再如，如果在步骤340计算出的第一高度是4.0mm，而在步骤360计算出的第二高度是4.2mm，过程将返回到步骤330，以确定另一组第一高度和第二高度，直到第一高度和第二高度之间的差值小于0.1mm。
在一个示范实施例里，如果在步骤340计算出的第一高度是4mm，而在步骤360计算出的第二高度是4.04mm，计算出的第三高度(其是第三芯片厚度、将第三芯片键合到第二DBC基板的第三焊基厚度、将第三芯片键合到第一DBC基板的第三焊块厚度之总和)是4.2mm，那么，过程循环返回第三芯片，重新计算第三高度，使得第一高度、第二高度和第三高度之间的最终高度差值小于0.1mm。否则，功率电子组件承受太多机械作用力或压力，这会导致组件内的芯片和其它电子元件失效。
图4显示一个示范实施例的制作功率电子封装的过程。
在步骤402，DBC顶基板被固定在一个组装系统的第一处理机(handler)上。例如，组装系统有多个能够支撑和固定基板的处理机。再如，处理机也能持有其他元件(如芯片和预成型的垫块)与基板适当对齐，使得元件能够在组装和热处理过程中保持一个正确的位置关系。
在步骤404，在DBC顶基板的预定区域上印制焊锡膏，以便将焊块连接到DBC顶基板上。
在步骤406，通过组装系统的一个处理机，将焊块安置在焊锡膏上。
在步骤408，在DBC顶基板的预定区域上涂布黏合剂，以便能够将垫块附着到DBC顶基板上。例如，将被涂布在预定区上的黏合剂的精确位置和数量是由一个涂布系统精确控制的。
在步骤410，将预先制成的垫块放置在黏合剂上，随后进行一个再流焊过程。例如，至少三个高度等于图3方法确定的优化高度的垫块，被放置在黏合剂上。再如，再流焊过程是一个加热过程，以熔化焊锡膏或黏合剂，形成一个机械连接和/或一个电子连接。例如，垫块是由硅制成，其横截面形状是圆形或多边形。
在步骤412，DBC底基板被固定到组装系统的第二处理机上。例如，组装系统有多个能够支撑和固定基板的处理机。再如，处理机也能持有其他元件(如芯片和预成型的垫块)与基板适当对齐，使得元件能够在组装和热处理过程中保持一个正确的位置关系。
在步骤414，在DBC底基板的预定区域上印制焊锡膏，以便将焊基连接到DBC底基板上。
在步骤416，通过组装系统的一个处理机，将焊基安置在焊锡膏上。
在步骤418，在焊基上印制焊锡膏，以便将芯片连接到DBC底基板上。
在步骤420，将芯片放置在焊锡膏上，随后在芯片顶表面上进行一个助焊剂涂布过程(fluxdispensingprocess)，以便将芯片连接到DBC顶基板上的焊块上。例如，助焊剂涂布过程包括一种化学清洁剂和一种流动剂，以从金属中去除氧化物，并在熔化之前保持焊块的固体特征形状，促进焊接过程。
在步骤422，在DBC底基板上放置引线框架，以形成到外部设备的电子连接。
在步骤430，将第一DBC基板压向第二DBC基板，直到垫块接触到第二DBC基板。通过该挤压步骤，安装在第二DBC基板上的芯片也连接到第一DBC基板上的焊块，因为垫块高度被精确设计用于该连接。功率电子封装的高度变化被垫块精确控制到小于0.1mm，以降低模塑过程中焊块和芯片的机械压力和崩塌率。
在步骤440，在真空环境下进行再流焊过程，以熔化焊块并形成机械和/或电子连接。
在步骤450，流动一种封装剂以封装功率电子封装。例如，将硅胶或环氧模塑化合物(EMC)的填料，填充在封装内的空腔里，以提供一个锁定机制，从而提高封装的可靠性。
图5显示本发明一个示范实施例的制作功率电子封装的系统500。系统500包括计算机510和功率电子封装组装系统520。计算机510包括处理器512、存储器514、显示器516和垫块尺寸推荐器518。处理器512与存储器514和垫块尺寸推荐器518进行通信，垫块尺寸推荐器518通过分析基板和芯片的热属性而提供一个推荐的垫块尺寸给功率电子封装组装系统520。垫块尺寸推荐器518包括软件和/或硬件以执行在此讨论的一个或多个步骤，从而确定垫块的一个尺寸。然后，功率电子封装组装系统520制作一个功率电子封装530，其包括一个具有推荐尺寸的垫块。
图6A显示本发明一个示范实施例的功率电子封装600A的侧视图。功率电子封装600A与图1披露的功率电子封装100相同或类似。其中一个区别是，芯片630A是通过焊球650被键合到DBC顶基板上的。在芯片630A的顶表面上和在朝向芯片的DBC顶基板内表面上有多个钝化区654。芯片上或DBC顶基板内表面上的相邻钝化区之间的距离，确定每个焊球的位置开口。例如，焊球开口是焊球直径的80％。
焊球接触DBC顶基板和芯片630A，以便电连接和机械连接芯片和DBC顶基板。在一个示范实施例里，焊球高度是焊球宽度的60％到80％。
图6B显示本发明另一个示范实施例的功率电子封装600B的侧视图。功率电子封装600B与图1所披露的功率电子封装100相同或类似。其中一个区别是，芯片630B是通过焊料铜料的混合物被键合到DBC顶基板上的。铜层670夹在两个焊层660之间，使得在底部的焊层被电连接和机械连接到芯片上，顶部的焊层被连接到DBC顶基板上。
用来评估功率模块的标准包括寄生电感、寄生电阻、和热阻抗。与有线键合的功率模块相比，电路的寄生电感和寄生电阻被降低高达89％。此外，由于能够通过DBC顶基板和DBC底基板散热，连接处的热阻抗被降低高达54％。
在此使用的“导电区”是指一个由导电材料形成并允许电流流动的区域。导电材料的例子包括但不限于铜、银、金、铝、锌、镍、黄铜、和其它导电材料(例如其它金属、石墨、聚合物、和半导体)。
在此使用的“整体模塑功率电子模块”是指被封装剂封装住的功率电子组件/模块，除了暴露表面用于散热。
在此使用的“功率电子封装”或“功率电子模块”是指包含功率半导体装置的电子封装或电子模块。功率半导体装置的例子包括但不限于MOSFET、二极管、IGBT、双极性结型晶体管(BJT)、晶闸管、可关断晶闸管、结型场效应晶体管(JFET)。
在此使用的“焊块”是一种具有球形状、立方体形状、或其他形状的焊接材料，包括金属和金属合金。
在此使用的“焊锡膏”是一种材料，其由多个离散焊料颗粒悬浮在载体如助焊剂或其它载体剂里而制成，以通过一个传统印制或类似过程而应用到基板上。

Claims (4)

1.一种制作功率电子封装的方法，包括：
提供第一DBC基板，其有非导电区、导电区、第一焊块和第二焊块；
提供第二DBC基板，其有支撑第一芯片的第一焊基，和支撑第二芯片的第二焊基，其也有非导电区和导电区；
通过分析所述第一和第二DBC基板和所述第一芯片的传热属性和可靠性，确定位于所述第一芯片和所述第一和第二DBC基板之间的所述第一焊基的厚度和所述第一焊块的厚度；
通过将所述第一芯片的厚度和所述第一焊基的厚度以及所述第一焊块的厚度加在一起，计算得到第一高度；
通过分析所述第一和第二DBC基板和所述第二芯片的传热属性和可靠性，确定位于所述第二芯片和所述第一和第二DBC基板之间的所述第二焊基的厚度和所述第二焊块的厚度；
通过将所述第二芯片的厚度和所述第二焊基的厚度以及所述第二焊块的厚度加在一起，计算得到第二高度；
当所述第一高度和所述第二高度之间的差值小于0.1mm时，计算所述第一高度和所述第二高度的平均值，确定一个优化高度；
在所述第一DBC基板的非导电区上涂布黏合剂，安装至少三个垫块在所述黏合剂上，所述垫块的高度等于所述优化高度；
将所述第一DBC基板压向所述第二DBC基板，直到所述垫块接触到所述第二DBC基板的非导电区，通过挤压，使支撑在所述第二DBC基板的焊基上的芯片也连接到所述第一DBC基板上的焊块，从而使所述功率电子封装的高度变化被所述垫块精确控制；
使用模塑化合物封装住包括所述第一DBC基板、所述第二DBC基板、和所述芯片的所述功率电子封装。
2.根据权利要求1所述的方法，其中所述第一焊块的高度是所述第一焊块宽度的60％到80％，所述第二焊块的高度是所述第二焊块宽度的60％到80％。
3.根据权利要求1所述的方法，还包括：
安置第三焊板，其接触所述第一DBC基板的导电区，并接触所述第二DBC基板的导电区。
4.根据权利要求1所述的方法，还包括：
使封装剂流动以封装所述功率电子封装。
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