CN107818921A - 一种基于二维平面异质结增强型场效应管的制备方法 - Google Patents

一种基于二维平面异质结增强型场效应管的制备方法 Download PDF

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CN107818921A
CN107818921A CN201710985285.2A CN201710985285A CN107818921A CN 107818921 A CN107818921 A CN 107818921A CN 201710985285 A CN201710985285 A CN 201710985285A CN 107818921 A CN107818921 A CN 107818921A
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张永哲
陈永锋
严辉
刘北云
邓文杰
游聪娅
李景峰
杨炎翰
申高亮
王光耀
庞玮
安博星
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Abstract

一种基于二维平面异质结增强型场效应管的制备方法,涉及微电子器件应用领域。采用湿法转移,将石墨烯膜转移至带有氧化层的单晶硅片衬底上;在石墨烯膜上进行均匀旋涂光刻胶,将图案通过曝光转移至光刻胶上;将石墨烯膜刻蚀成石墨烯条,去光刻胶处理;将这种带有石墨烯条的衬底作为生长的基底,以CVD法进行生长MX2类单层或者少层材料,形成石墨烯‑MX2‑石墨烯面内异质结;在石墨烯‑MX2‑石墨烯异质结上蒸镀沉积Ti/Au金属,制得二维平面异质结增强型场效应管。本发明结合高载流子迁移率的半金属材料石墨烯与带隙随层数变化可调的MX2二维材料,获得高开关比的场效应管并且用于光电探测时具有暗电流很小等优良特性。

Description

一种基于二维平面异质结增强型场效应管的制备方法
技术领域
本发明涉及一种微电子器件应用领域,特别是一种可用于数字逻辑电路的高开关比、低功耗的增强型场效应管的制备方法。
技术背景
2004年石墨烯的成功制备,证明了二维材料可以在自然界中稳定存在,也开启了二维纳米材料的研究热潮。对于二维材料,单层石墨烯具有单原子层的厚度,电子被限制在二维尺度范围内,使其电子特性增强。因此,单层石墨烯在室温状态下就具有高的载流子迁移率,达到2.5×105cn2V-1s-1。虽然单层石墨烯具有独特的电学性能和优异的稳定性,在未来微电子领域有优越地应用潜力,但是石墨烯材料在费米能级附近,能带具有线性色散关系而发生克莱因隧穿,导致材料制备的器件具有很低的开关比。尽管通过掺杂等方式可以使石墨烯具有一定大小的带隙,但是由于杂质散射或者缺陷作用对载流子迁移率影响很大;同时作为逻辑器件沟道材料使用过程中不能够很好的控制器件的关断,会出现漏电等情况。而通过这种平面异质结来制备场效应晶体管,不仅可以很好地控制器件的开关状态,而且还具有很高的开关比,使该异质结构材料制备的器件具有低功耗;同时,该器件在光电探测方面也具有低暗电流等特性。因此,这种平面异质结构制备的器件在未来的逻辑电路及光电探测器方面可以被广泛地应用。
发明内容
本发明提供一种基于二维平面异质结增强型场效应管的制备方法。该二维平面异质结实现不同二维材料之间线接触,改变传统范德华力面接触,可获得开关比高达106、低暗电流及低功耗等特性的增强型场效应管。并且基于刻蚀的石墨烯材料边界处有较多的悬挂键及缺陷,为其它二维材料的生长提供形核位点,可实现不同材料的二维平面异质结增强型场效应管批量化制备。
本发明的技术方案:一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,按下述步骤进行:
①采用湿法转移,将CVD法制备生长于铜箔上的石墨烯膜转移至带有氧化层的单晶硅片衬底;
②在转移后的石墨烯膜上进行均匀旋涂光刻胶,再将掩膜版上的图案通过曝光转移至光刻胶上;
③采用等离子体刻蚀机刻蚀掉非图案部分,将石墨烯膜刻蚀成一定形状和间距的石墨烯条或块,石墨烯条或块的长、宽值在2~60μm之间,石墨烯条或块之间的距离为5~30μm,然后进行去光刻胶处理;
④将这种带有石墨烯条或块的衬底作为生长的基底,以CVD法在相邻的两石墨烯条或块之间进行生长MX2类(MoS2、WS2等过渡族硫化物)单层或者少层材料,与石墨烯条或块之间形成石墨烯-MX2-石墨烯面内异质结层;
⑤在石墨烯-MX2-石墨烯面内异质结层上均匀旋涂光刻胶,再将掩膜版上的图案通过曝光转移至光刻胶上,并采用电子束蒸镀在石墨烯-MX2-石墨烯面内异质结层两边的石墨烯上沉积Ti/Au金属得到Ti/Au电极,制得二维平面异质结增强型场效应管。
其中,优选地,步骤①中的湿法移过程中腐蚀铜箔采用腐蚀液为过硫酸铵((NH4)2S2O8)溶液,溶液浓度为0.3mol/L~0.8mol/L。
其中,优选地,步骤①中衬底采用的是带二氧化硅氧化层的硅片,氧化层的厚度在290~300nm,衬底为厚度400μm的P型高掺杂硅片。
其中,优选地,所述步骤②中对转移后的石墨烯膜进行旋涂光刻胶,匀胶机低速挡转速选择350~450r/min,高速挡转速30000~3500r/min。
其中,优选地,所述步骤③中采用等离子体刻蚀机刻蚀,刻蚀采用的气体为O2,气流量的大小为30~50sccm,刻蚀时间为7~10min。
其中,优选地,所述步骤③刻蚀的石墨烯为条或块状,石墨烯条或块的长、宽数值在10~50μm之间,条块之间的距离为5~20μm。
其中,优选地,所述步骤④中以CVD法生长MX2类二维材料,选用常压条件下可生长的MoS2、WS2等材料。
前述的基于二维平面异质结增强型场效应管的制备方法中,其中,优选地,所述石墨烯-MX2-石墨烯异面内质结中的石墨烯原材料为转移CVD法生长于铜箔表面的膜状石墨烯。
前述的基于二维平面异质结增强型场效应管的制备方法中,其中,优选地,所述步骤⑤中Ti/Au电极采用电子束蒸镀沉积5~10nm厚度的金属Ti和60~80nm厚金属Au。
与现有技术相比,本发明的优点在于:
一、本发明的二维平面异质结增强型场效应管以过渡族硫化物生长的二氧化硅/硅基底为衬底,可以直接进行器件的制备,易于集成;
二、本发明中二维平面异质结可以根据合适掩膜版的选择,实现大面积、多数量及可控材料生长的增强型场效应管制备,易于批量化生产;
三、本发明的二维平面异质结增强型场效应管可获得高开关比、低功耗和低暗电流等特性。并且本发明异质结结构实现线接触,改变传统范德华力面接触,且表面悬挂键少,能有效改善载流子迁移率;同时,也打破石墨烯零能带隙的限制,保证场效应管的开关特性,克服石墨烯在场效应管逻辑电路中的应用的局限性。
附图说明
图1是实施例中石墨烯-MoS2-石墨烯异质结的结构示意图;
图2是实施例中石墨烯-MoS2-石墨烯二维平面异质结结构二维拉曼成像图;
图3是实施例中的石墨烯-MoS2-石墨烯二维平面异质结增强型场效应管的源极和漏极之间的电流Id随栅极电压Vg变化曲线;
图4为实施例中的石墨烯-MoS2-石墨烯二维平面异质结增强型场效应管的源极和漏极之间的电流Id随源漏极之间偏压Vds变化曲线;
附图中的标记为:1-高掺杂P型单晶硅片,2-300nm的二氧化硅的氧化层,3,7-均为Ti/Au电极,4,6-石墨烯薄片,5-CVD法生长的硫化钼薄片。
具体实施方式
下面结合附图和实施例对本发明进一步说明,但并不作为对本发明的限制。
实施例1一种基于二维平面异质结增强型场效应管的制备方法,按下述步骤进行:
采用湿法转移,将CVD法制备生长于铜箔上的石墨烯转移至带有氧化层的单晶硅片衬底。实验过程中,刻蚀铜箔的腐蚀液用过硫酸铵溶液,溶液的浓度为0.1mol/L,刻蚀完成后,将石墨烯膜转移至新的二氧化硅/硅基底上;
在转移后的石墨烯膜上进行均匀旋涂光刻胶,再通过光刻将掩膜版上的图案通过曝光转移至光刻胶上;然后通过显影液清洗,将未曝光的部分光刻胶清洗掉并烘干。
采用等离子体刻蚀非图案部分,将图案外的部分刻蚀掉。刻蚀结束后,石墨烯膜被刻蚀成长、宽大小均为50μm长的石墨烯块,且两个石墨烯条块之间的距离为5μm左右,然后进行去光刻胶处理,将刻蚀后的石墨烯块放入丙酮中进行清洗10min后,并用去离子水冲洗三遍,烘干为生长做准备。
将这种带有石墨烯块的衬底作为生长的基底,以常压CVD法在两相邻的石墨烯块之间的空隙内进行单层MoS2生长,与石墨烯块形成石墨烯-MoS2-石墨烯面内异质结;
具体的生长过程按下述步骤:
(1)选取适当大小的钼箔(纯度为99.999%),使用电化学工作站,将其进行氧化处理;然后选取合适大小的氧化钼箔片,放置在石英舟内,并将带有石墨烯块的衬底片正对着氧化钼箔,倒扣在石英舟上,然后将其放置于管式炉加热温区中心;
(2)称取纯度为99.999%的硫粉置于氧化铝坩埚中,放置在管式炉上游的的石英管管内,距离温区中心位置25cm;并将加热带包裹在硫源所在位置的石英管的外壁(上游指Ar气流流入的方向);
(3)实验前,排去腔体内的空气,Ar气气流量大小设置100~300sccm之间,通入时间为15min;
(4)待排空气时间结束后,以Ar气为载气,气流量设置为250sccm,至实验结束;并将管式炉温度设定850℃,升温速率为30℃/min,沉积时间为2min,自然冷却;同时,待中心温区温度升温至500℃时,打开硫温区加热带,硫加热带温度设定为300℃,开始为实验供应硫源,硫化时间30min,硫化结束后,关闭硫加热带,并将加热带移至石英管冷端;
(5)硫化结束后,待炉内温度降温至室温,取出样品进行二维拉曼成像测试(详见附图2)
在制备石墨烯-MoS2-石墨烯面内异质结层上均匀旋涂光刻胶,再将掩膜版上的图案通过曝光转移至光刻胶上,然后采用显影并烘干,并采用电子束蒸镀沉积Ti/Au(10nm/80nm)金属,用丙酮腐蚀光刻胶后显露出石墨烯-MoS2-石墨烯的2个电极3和7,制得二维平面异质结增强型场效应管,如附图1所示。
将制得的二维平面异质结增强型场效应管进行电学性质测试,所得的石墨烯-MoS2-石墨烯二维平面异质结增强型场效应管的源极和漏极之间的电流Id随栅极电压Vg变化曲线如附图3所示,其中Ion达到7μA左右,Ioff达到10-6μA,开关比可达到106。所得的石墨烯-MoS2-石墨烯二维平面异质结增强型场效应管在栅压Vg=0V时,源极和漏极之间的电流Id随偏压Vds变化曲线如图4所示,关态下,暗电流仅达到3pA左右。

Claims (9)

1.一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,按下述步骤进行:
①采用湿法转移,将CVD法制备生长于铜箔上的石墨烯膜转移至带有氧化层的单晶硅片衬底;
②在转移后的石墨烯膜上进行均匀旋涂光刻胶,再将掩膜版上的图案通过曝光转移至光刻胶上;
③采用等离子体刻蚀机刻蚀掉非图案部分,将石墨烯膜刻蚀成一定形状和间距的石墨烯条或块,石墨烯条或块的长、宽值在2~60μm之间,石墨烯条或块之间的距离为5~30μm,然后进行去光刻胶处理;
④将这种带有石墨烯条或块的衬底作为生长的基底,以CVD法在相邻的两石墨烯条或块之间进行生长MX2类单层或者少层材料,与石墨烯条或块之间形成石墨烯-MX2-石墨烯面内异质结层;
⑤在石墨烯-MX2-石墨烯面内异质结层上均匀旋涂光刻胶,再将掩膜版上的图案通过曝光转移至光刻胶上,并采用电子束蒸镀在石墨烯-MX2-石墨烯面内异质结层两边的石墨烯上沉积Ti/Au金属得到Ti/Au电极,制得二维平面异质结增强型场效应管。
2.按照权利要求1所述的一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,MX2类物质选自过渡族硫化物,优选MoS2、WS2
3.按照权利要求1所述的一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,步骤①中的湿法移过程中腐蚀铜箔采用腐蚀液为过硫酸铵((NH4)2S2O8)溶液,溶液浓度为0.3mol/L~0.8mol/L。
4.按照权利要求1所述的一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,步骤①中衬底采用的是带二氧化硅氧化层的硅片,氧化层的厚度在290~300nm,衬底为厚度400μm的P型高掺杂硅片。
5.按照权利要求1所述的一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,步骤②中对转移后的石墨烯膜进行旋涂光刻胶,匀胶机低速挡转速选择350~450r/min,高速挡转速30000~3500r/min。
6.按照权利要求1所述的一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,步骤③中采用等离子体刻蚀机刻蚀,刻蚀采用的气体为O2,气流量的大小为30~50sccm,刻蚀时间为7~10min。
7.按照权利要求1所述的一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,步骤③刻蚀的石墨烯为条或块状,石墨烯条或块的长、宽数值在10~50μm之间,条块之间的距离为5~20μm。
8.按照权利要求1所述的一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,石墨烯-MX2-石墨烯异面内质结中的石墨烯原材料为转移CVD法生长于铜箔表面的膜状石墨烯。
9.按照权利要求1所述的一种基于二维平面异质结增强型场效应管的制备方法,其特征在于,步骤⑤中Ti/Au电极采用电子束蒸镀沉积5~10nm厚度的金属Ti和60~80nm厚金属Au。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111106166A (zh) * 2019-11-21 2020-05-05 厦门大学 一种单层二硫化锡薄膜及其二维异质结和制备方法
CN111254414A (zh) * 2020-01-21 2020-06-09 西安工程大学 柔性石墨烯基硅纳米线异质结的制备与转移方法
CN111889112A (zh) * 2020-08-04 2020-11-06 杭州紫芯光电有限公司 一种MoS2/Graphene二维材料异质结可见光催化剂的制备方法
CN111969076A (zh) * 2020-08-04 2020-11-20 中国科学院金属研究所 一种基于氧化钼/二硫化钼/氧化钼异质结构的光电晶体管及其制作方法
CN112079387A (zh) * 2020-08-26 2020-12-15 广东工业大学 一种二维二硫化钨自构同质结及其制备方法和应用
CN112110411A (zh) * 2019-06-19 2020-12-22 中国科学院物理研究所 一种制备悬空的层状金属硫属化合物的方法
CN114447150A (zh) * 2022-01-17 2022-05-06 上海集成电路制造创新中心有限公司 一种光电探测器及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531655A (zh) * 2013-10-28 2014-01-22 鲍桥梁 一种与硅光波导集成的石墨烯异质结光探测器
CN104538288A (zh) * 2014-12-09 2015-04-22 哈尔滨工业大学 一种直接生长原子尺度二维半导体异质结的装置及方法
US20170170260A1 (en) * 2015-12-10 2017-06-15 Massachusetts Institute Of Technology Universal Methodology to Synthesize Diverse Two-Dimensional Heterostructures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531655A (zh) * 2013-10-28 2014-01-22 鲍桥梁 一种与硅光波导集成的石墨烯异质结光探测器
CN104538288A (zh) * 2014-12-09 2015-04-22 哈尔滨工业大学 一种直接生长原子尺度二维半导体异质结的装置及方法
US20170170260A1 (en) * 2015-12-10 2017-06-15 Massachusetts Institute Of Technology Universal Methodology to Synthesize Diverse Two-Dimensional Heterostructures

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
AMIRHOSSEIN BEHRANGINIA ET AL: "Direct Growth of High Mobility and Low Noise Lateral MoS2-Graphene Heterostructure Electronics", 《SMALL》 *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112110411A (zh) * 2019-06-19 2020-12-22 中国科学院物理研究所 一种制备悬空的层状金属硫属化合物的方法
CN112110411B (zh) * 2019-06-19 2023-06-06 中国科学院物理研究所 一种制备悬空的层状金属硫属化合物的方法
CN111106166A (zh) * 2019-11-21 2020-05-05 厦门大学 一种单层二硫化锡薄膜及其二维异质结和制备方法
CN111254414A (zh) * 2020-01-21 2020-06-09 西安工程大学 柔性石墨烯基硅纳米线异质结的制备与转移方法
CN111254414B (zh) * 2020-01-21 2022-03-29 西安工程大学 柔性石墨烯基硅纳米线异质结的制备与转移方法
CN111889112A (zh) * 2020-08-04 2020-11-06 杭州紫芯光电有限公司 一种MoS2/Graphene二维材料异质结可见光催化剂的制备方法
CN111969076A (zh) * 2020-08-04 2020-11-20 中国科学院金属研究所 一种基于氧化钼/二硫化钼/氧化钼异质结构的光电晶体管及其制作方法
CN111969076B (zh) * 2020-08-04 2024-03-22 中国科学院金属研究所 一种基于氧化钼/二硫化钼/氧化钼异质结构的光电晶体管及其制作方法
CN112079387A (zh) * 2020-08-26 2020-12-15 广东工业大学 一种二维二硫化钨自构同质结及其制备方法和应用
CN112079387B (zh) * 2020-08-26 2023-01-20 广东工业大学 一种二维二硫化钨自构同质结及其制备方法和应用
CN114447150A (zh) * 2022-01-17 2022-05-06 上海集成电路制造创新中心有限公司 一种光电探测器及其制备方法

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