CN107808902B - 一种具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管 - Google Patents
一种具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管 Download PDFInfo
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- 230000005684 electric field Effects 0.000 title claims abstract description 90
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 230000015556 catabolic process Effects 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims description 22
- 239000003989 dielectric material Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 10
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 238000001727 in vivo Methods 0.000 abstract description 7
- 230000005669 field effect Effects 0.000 abstract description 5
- 229910044991 metal oxide Inorganic materials 0.000 abstract description 5
- 150000004706 metal oxides Chemical class 0.000 abstract description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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Abstract
本发明公开一种具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管。该结构中漂移区下方的衬底为电荷补偿多环结构。衬底多环电荷补偿可以扩展横向双扩散金属氧化物半导体场效应管的纵向空间电荷区，同时该多环结构还能在表面横向电场和体内纵向电场分布中均引入新的电场峰，利用电场调制效应对表面横向电场和体内纵向电场同时进行调制，使得表面横向电场和体内纵向电场同时优化。该结构不仅突破了横向双扩散晶体管由于纵向耐压受限而带来的击穿电压饱和问题，还能达到同时优化表面横向电场和体内纵向电场的作用，可以大幅度提高器件的击穿电压。
Description
技术领域
本发明涉及半导体功率器件技术领域，具体涉及一种横向双扩散金属氧化物半导体场效应管。
背景技术
横向双扩散金属氧化物半导体场效应管(Lateral Double-diffused MOSFET，简称LDMOS)具有易集成，热稳定性好，较好的频率稳定性，低功耗，多子导电，功率驱动小，开关速度高等优点是智能功率电路和高压器件的核心。由于便携式电源管理和汽车电子产品的市场需求日益增长，在全球范围内受到越来越多的关注。
然而，由于Si与GaAs为代表的前两代半导体材料的局限性，第三代宽禁带半导体材料因为其优异的性能得到了飞速发展。宽禁带半导体材料由于具有禁带宽度大，电子漂移饱和速度高、介电常数小、导电性能好的特点，其本身具有的优越性质及其在功率器件领域应用中潜在的巨大前景，非常适用于制作抗辐射、高频、大功率和高密度集成的半导体器件。因此，宽禁带功率半导体器件的性能相比前两代半导体器件是有明显提升的。
为了进一步提高宽带隙横向功率器件的性能，在器件设计过程中，需要满足弱化表面电场(Reduced Surface Field，简称RESURF)技术的条件使得器件的击穿点从表面转移到体内。然而随着器件漂移区长度的增加，器件的击穿电压主要受限于体内纵向耐压能力，即由于横向功率器件的电压饱和效应，器件的击穿电压随着漂移区长度的增加逐渐趋于饱和。
为了打破击穿电压饱和效应，早期提出的具有REBULF结构的LDMOS，通过在体内埋入一层N+-Floating层，使横向高压器件的电场重新分配，突破了传统上漏端为高电场而源端为低电场的电场分布形式，N+-Floating层的等电势作用使漏端高电场区的高电场降低，在硅达到其临界击穿电场时击穿电压提高，器件的衬底承担了几乎全部的纵向耐压。
发明内容
本发明提出了一种具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，不仅突破了横向双扩散晶体管由于纵向耐压受限而带来的击穿电压饱和问题，还能达到同时优化表面横向电场和体内纵向电场的作用，大幅度提高器件的击穿电压。
本发明的技术方案如下：
该具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，包括：
半导体材料的衬底；
位于衬底表面的基区和漂移区；
位于基区表面的源区；
位于漂移区表面的漏区；
其特殊之处在于：
所述衬底为宽带隙半导体材料；漂移区下方邻接的衬底区域设置为多环电场调制结构；所述多环电场调制结构与漂移区的宽度(OA方向)相当，是以靠近漏区的一端为中心，向靠近基区的一端扩展形成多环；
所述多环电场调制结构的每个环分别采用N型或P型掺杂宽带隙半导体材料，或者采用介质材料；相应的，相邻的环以不同材料、不同掺杂类型、不同掺杂浓度之任一或任意组合的方式来区分。
例如以下三类具体形式：
1、多环电场调制结构完全采用宽带隙半导体材料
每个环分别由N型或P型掺杂宽带隙半导体材料构成；其中相邻的环的掺杂类型和/或掺杂浓度不同，即(1)掺杂类型不同，掺杂浓度相同；(2)虽然掺杂类型相同但掺杂浓度不同；(3)掺杂类型不同，掺杂浓度也不同；
2、多环电场调制结构完全采用介质材料，相邻的环的介质材料不同。
3、多环电场调制结构的某些环为宽带隙半导体材料，某些环为介质材料，可通过宽带隙半导体材料与介质材料相间设置的方式来区分，也可仍然或同时采用前两类方式区分。
在以上方案的基础上，本发明还进一步作了如下优化：
宽带隙半导体材料的衬底掺杂浓度的典型值为1×1013cm-3～1×1015cm-3。
多环电场调制结构中，每个环的典型掺杂浓度为1×1014cm-3～1×1016cm-3。
介质材料选自二氧化硅和氧化铪。
多环电场调制结构中每个环的径向宽度(OB方向)占漂移区整体长度的比例根据耐压需求调整，典型的比例值为0.2～0.5，多环电场调制结构不超过漂移区整体长度。
多环电场调制结构中各个环的径向宽度(OB方向)相等或者有的环的径向宽度不同；所述多环电场调制结构中环的数量根据耐压需求调整，典型值为2～5个。
多环电场调制结构中环的形状为弧线型环或阶梯型环。
多环电场调制结构中环的形状为同心圆环。
对于漂移区厚度(OC方向)为2μm、漂移区长度(OB方向)为30μm的器件，当击穿电压要求为500V时，采用同心圆环形式的多环电场调制结构，多环以N/P相间掺杂，多环的数量为2～5个，每个环的径向宽度(OB方向)占漂移区整体长度的0.2～0.5，多环电场调制结构不超过漂移区整体长度。
宽带隙半导体材料为氮化镓、碳化硅或金刚石。
本发明技术方案的有益效果如下：
在LDMOS的漂移区下方的衬底区域设置为多环电荷补偿结构，可以扩展横向双扩散金属氧化物半导体场效应管的纵向空间电荷区，同时还能在表面横向电场和体内纵向电场分布中均引入新的电场峰，利用电场调制效应对表面横向电场和体内纵向电场进行调制，使得表面横向电场和体内纵向电场同时优化。
该结构不仅突破了横向双扩散晶体管由于纵向耐压受限而带来的击穿电压饱和问题，还能达到同时优化表面横向电场和体内纵向电场的作用，可以大幅度提高器件的击穿电压。
附图说明
图1为本发明一种具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管结构的三维示意图。
图2是在多环电荷补偿结构处沿OAC方向的截面图。
附图标号说明：
1-宽带隙半导体材料衬底；2-基区；3-源区；4-漏区；5-漂移区；6，7，8，9-多环电场调制结构的各个环。
具体实施方式
如图1和图2所示为一种具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管：
宽带隙半导体材料衬底1，掺杂浓度为一般宽带隙半导体单晶材料的浓度，典型值为1×1013cm-3～1×1015cm-3；
位于宽带隙半导体衬底表面的基区2和漂移区5；
位于基区表面的源区3；
位于漂移区表面的漏区4；
位于漂移区下的多环电场调制结构；
多环电场调制结构的各个环6、7、8和9可为N型、P型掺杂硅材料，典型的掺杂浓度达到1×1014cm-3～1×1016cm-3；
多环电场调制结构的各个环6、7、8和9还可为介质材料，如二氧化硅、氧化铪等；
多环电场调制结构的各个环6、7、8和9中环的径向宽度(OB方向)占漂移区整体长度的比例可根据耐压需求调整。典型的衬底多环结构中环的宽度占漂移区整体长度的比例为0.2～0.5；
多环电场调制结构的各个环6、7、8和9中环与环的径向宽度(OB方向)，或者等宽或者不等宽；
多环电场调制结构的各个环6、7、8和9中环的数量可根据耐压需求调整；
多环电场调制结构的各个环6、7、8和9的形状可为规则图形，如同心圆环。也可为不规则图形，如普通弧线型环、阶梯型环等。
设置的多环电荷补偿结构可以扩展横向双扩散金属氧化物半导体场效应管的纵向空间电荷区，同时还能在表面横向电场和体内纵向电场分布中均引入新的电场峰，利用电场调制效应对表面横向电场和体内纵向电场进行调制，使得表面横向电场和体内纵向电场同时优化。该结构不仅突破了横向双扩散晶体管由于纵向耐压受限而带来的击穿电压饱和现象，还能达到同时优化表面横向电场和体内纵向电场的作用，可以大幅度提高器件的击穿电压。
针对薄漂移区(2μm)N沟道LDMOS，当漂移区长度为30μm时，普通LDMOS击穿电压仅为300V左右，而采用本发明的结构，利用每个圆环宽度为10μm，N/P/N型相间掺杂的同心圆环结构可以将器件的击穿电压提高到750V左右，提高了150％.
针对薄漂移区(2μm)N沟道LDMOS，当漂移区长度为60μm时，普通LDMOS击穿电压仅为400V左右，而采用本发明的结构，利用每个圆环宽度为20μm，N/P/N型相间掺杂的同心圆环结构可以将器件的击穿电压提高到1500V，提高了275％.
当然，本发明中的LDMOS也可以为P沟道，其结构与N沟道LDMOS等同，在此不再赘述。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明技术原理的前提下，还可以做出若干改进和替换，这些改进和替换的方案也落入本发明的保护范围。
Claims (8)
1.一种具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，包括：
半导体材料的衬底；
位于衬底表面的基区和漂移区；
位于基区表面的源区；
位于漂移区表面的漏区；
其特征在于：
所述衬底为宽带隙半导体材料；漂移区下方邻接的衬底区域设置为多环电场调制结构；所述多环电场调制结构与漂移区的宽度相当，是以靠近漏区的一端为中心，向靠近基区的一端扩展形成多环；每个环的径向宽度占漂移区整体长度的比例为0.2～0.5，多环电场调制结构不超过漂移区整体长度；所述多环电场调制结构中各个环的径向宽度相等或者有的环的径向宽度不同；所述多环电场调制结构中环的数量为2～5个；
所述多环电场调制结构的每个环分别采用N型或P型掺杂宽带隙半导体材料，或者采用介质材料；相应的，相邻的环以不同材料、不同掺杂类型、不同掺杂浓度之任一或任意组合的方式来区分。
2.根据权利要求1所述的具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，其特征在于：宽带隙半导体材料的衬底掺杂浓度为1×1013cm-3～1×1015cm-3。
3.根据权利要求1所述的具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，其特征在于：所述多环电场调制结构中，每个环的掺杂浓度为1×1014cm-3～1×1016cm-3。
4.根据权利要求1所述的具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，其特征在于：所述介质材料选自二氧化硅和氧化铪。
5.根据权利要求1所述的具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，其特征在于：所述多环电场调制结构中环的形状为弧线型环或阶梯型环。
6.根据权利要求5所述的具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，其特征在于：所述多环电场调制结构中环的形状为同心圆环。
7.根据权利要求1所述的具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，其特征在于：对于漂移区厚度为2μm、漂移区长度为30μm的器件，当击穿电压要求为750V时，采用同心圆环形式的多环电场调制结构，多环以N/P相间掺杂，多环的数量为2～5个，每个环的径向宽度占漂移区整体长度的0.2～0.5，多环电场调制结构不超过漂移区整体长度。
8.根据权利要求1所述的具有多环电场调制衬底的宽带隙半导体横向双扩散晶体管，其特征在于：所述宽带隙半导体材料为氮化镓、碳化硅或金刚石。
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| US4288802A (en) * | 1979-08-17 | 1981-09-08 | Xerox Corporation | HVMOSFET Driver with single-poly gate structure |
| US20070221967A1 (en) * | 2006-03-27 | 2007-09-27 | Khemka Vishnu K | Semiconductor device and method for forming the same |
| CN101916729A (zh) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | 具有多层超结结构的soi ldmos器件制作方法 |
| CN106876464A (zh) * | 2016-12-29 | 2017-06-20 | 西安电子科技大学 | 一种横向双扩散金属氧化物半导体场效应管 |
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| US4288802A (en) * | 1979-08-17 | 1981-09-08 | Xerox Corporation | HVMOSFET Driver with single-poly gate structure |
| US20070221967A1 (en) * | 2006-03-27 | 2007-09-27 | Khemka Vishnu K | Semiconductor device and method for forming the same |
| CN101916729A (zh) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | 具有多层超结结构的soi ldmos器件制作方法 |
| CN106876464A (zh) * | 2016-12-29 | 2017-06-20 | 西安电子科技大学 | 一种横向双扩散金属氧化物半导体场效应管 |
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