CN107731783A - One kind bonding wafer and its technique - Google Patents
One kind bonding wafer and its technique Download PDFInfo
- Publication number
- CN107731783A CN107731783A CN201711131170.3A CN201711131170A CN107731783A CN 107731783 A CN107731783 A CN 107731783A CN 201711131170 A CN201711131170 A CN 201711131170A CN 107731783 A CN107731783 A CN 107731783A
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- wafer
- metallic film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Adhesives Or Adhesive Processes (AREA)
Abstract
The present invention relates to technical field of semiconductors, more particularly to a kind of bonding wafer, including：First wafer, prepared by the upper surface at edge have metallic film in uniform thickness；Second wafer, the upper surface that the one side for having metallic film is prepared with the first wafer are bonded；Enable to wafer to keep bonding force that is smooth, and then keeping the edge of wafer in edge, avoid the generation of grey side defect.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of bonding wafer and its technique, and use the technique
Three dimensional integrated circuits.
Background technology
Three dimensional integrated circuits is the integrated circuit formed using three-dimensional packaging technology, and common three-dimensional packaging technology is by wafer
Lamination, processing, such as by the wafer lamination for grinding very thin, scribing, small folded block is formed, then carry out cloth in the side of small folded block
Line, realize the connection between each layer.
However, the edge for the one side for needing wafer having metal in traditional technique carries out side washing, but the crystalline substance Jing Guo side washing
The round pattern out-of-flatness in edge, bonding force is weak, and higher grey side ratio of defects is easily produced after wafer bonding.
The content of the invention
In view of the above-mentioned problems, the present invention proposes a kind of bonding wafer, wherein, including：
First wafer, prepared by the upper surface at edge have metallic film in uniform thickness；
Second wafer, the upper surface that the one side for having the metallic film is prepared with first wafer are bonded.
Above-mentioned bonding wafer, wherein, the metallic film is Copper thin film.
Above-mentioned bonding wafer, wherein, it is also formed with multiple through holes in first wafer；
The metallic film also fills up forms contact hole structure into each through hole.
A kind of three dimensional integrated circuits, wherein, including as above any described bonding wafer.
A kind of wafer bonding technique, wherein, including：
Step S1, there is provided one first wafer and one second wafer, and it is prepared by the upper surface at the edge of first wafer
There is metallic film in uniform thickness；
Step S2, prepared by first wafer have the one side of the metallic film and second wafer bonding.
Above-mentioned wafer bonding technique, wherein, the metallic film is Copper thin film.
Above-mentioned wafer bonding technique, wherein, it is also formed with multiple through holes in first wafer；
The metallic film also fills up forms contact hole structure into each through hole.
Above-mentioned wafer bonding technique, wherein, the step S2 is completed in high temperature environments.
Beneficial effect：A kind of bonding wafer proposed by the present invention and its technique, and the three-dimensionally integrated electricity using the technique
Road, enable to wafer to keep bonding force that is smooth, and then keeping the edge of wafer in edge, avoid the production of grey side defect
It is raw.
Brief description of the drawings
Fig. 1 is the structural representation that wafer is bonded in one embodiment of the invention.
Embodiment
The present invention is further described with reference to the accompanying drawings and examples.
Embodiment one
In a preferred embodiment, as shown in Figure 1, it is proposed that one kind bonding wafer, wherein it is possible to including：
First wafer 10, prepared by the upper surface at edge have metallic film 11 in uniform thickness；
Second wafer 20, the upper surface that the one side for having metallic film 11 is prepared with the first wafer 10 are bonded.
In above-mentioned technical proposal, justify compared to conventional keys synthetic, the side of the first wafer 10 of the bonding wafer in the present invention
Prepared by the upper surface of edge have metallic film 11 in uniform thickness, the edge of the first wafer 10 is not ground or etched, so as to
It ensure that the bonding force of the first wafer 10 and the second wafer 20 also will not be insufficient in edge, avoid the appearance of grey side defect；
20 can also prepare other structures in first wafer 10 and the second wafer, but this is the ordinary skill in the art, herein no longer
Repeat.
In a preferred embodiment, metallic film 11 can be Copper thin film, can be brilliant by first using the Copper thin film
The wafer 20 of circle 10 and second is closely bonded.
In a preferred embodiment, multiple through holes are also formed with the first wafer 10；
Metallic film 11 also fills up forms contact hole structure into each through hole.
Embodiment two
In a preferred embodiment, it is also proposed that a kind of three dimensional integrated circuits, it is characterised in that including as above any
Bonding wafer, the bonding wafer can be carried on a printed circuit board.
Embodiment three
In a preferred embodiment, it is also proposed that a kind of wafer bonding technique, wherein it is possible to including：
Step S1, there is provided one first wafer 10 and one second wafer 20, and the upper surface system at the edge of the first wafer 10
Have metallic film 11 in uniform thickness；
Step S2, the one side that prepared by the first wafer 10 have metallic film 11 are bonded with the second wafer 20.
In above-mentioned technical proposal, in step S2, the bonding process of the first wafer 10 and the second wafer 20 can be in high temperature
Lower completion.
In a preferred embodiment, metallic film 11 is Copper thin film, can be by the first wafer 10 using the Copper thin film
Closely it is bonded with the second wafer 20.
In a preferred embodiment, multiple through holes are also formed with the first wafer 10；
Metallic film 11 can also fill forms contact hole structure into each through hole.
In a preferred embodiment, step S2 can be completed in high temperature environments.
In summary, a kind of bonding wafer proposed by the present invention, including：First wafer, prepared by the upper surface at edge have thickness
Spend uniform metallic film；Second wafer, the upper surface that the one side for having metallic film is prepared with the first wafer are bonded；Enable to
Wafer keeps bonding force that is smooth, and then keeping the edge of wafer in edge, avoids the generation of grey side defect.
By explanation and accompanying drawing, the exemplary embodiments of the specific structure of embodiment are given, it is smart based on the present invention
God, it can also make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading described above, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard whole variations and modifications of the true intention and scope that cover the present invention as.Weighing
Any and all scope and content of equal value, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (8)
1. one kind bonding wafer, it is characterised in that including：
First wafer, prepared by the upper surface at edge have metallic film in uniform thickness；
Second wafer, the upper surface that the one side for having the metallic film is prepared with first wafer are bonded.
2. bonding wafer according to claim 1, it is characterised in that the metallic film is Copper thin film.
3. bonding wafer according to claim 1, it is characterised in that be also formed with multiple through holes in first wafer；
The metallic film also fills up forms contact hole structure into each through hole.
4. a kind of three dimensional integrated circuits, it is characterised in that including the bonding wafer as described in claims 1 to 3 is any.
A kind of 5. wafer bonding technique, it is characterised in that including：
Step S1, there is provided one first wafer and one second wafer, and the upper surface preparation at the edge of first wafer has thickness
Spend uniform metallic film；
Step S2, prepared by first wafer have the one side of the metallic film and second wafer bonding.
6. wafer bonding technique according to claim 5, it is characterised in that the metallic film is Copper thin film.
7. wafer bonding technique according to claim 5, it is characterised in that be also formed with first wafer multiple logical
Hole；
The metallic film also fills up forms contact hole structure into each through hole.
8. wafer bonding technique according to claim 5, it is characterised in that the step S2 is completed in high temperature environments.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711131170.3A CN107731783A (en) | 2017-11-15 | 2017-11-15 | One kind bonding wafer and its technique |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711131170.3A CN107731783A (en) | 2017-11-15 | 2017-11-15 | One kind bonding wafer and its technique |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107731783A true CN107731783A (en) | 2018-02-23 |
Family
ID=61216157
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711131170.3A Pending CN107731783A (en) | 2017-11-15 | 2017-11-15 | One kind bonding wafer and its technique |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107731783A (en) |
Citations (10)
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|---|---|---|---|---|
| US20050139954A1 (en) * | 2003-12-30 | 2005-06-30 | Pyo Sung G. | Radio frequency semiconductor device and method of manufacturing the same |
| CN101656217A (en) * | 2008-08-18 | 2010-02-24 | 中芯国际集成电路制造(上海)有限公司 | System-in-package method |
| CN102050418A (en) * | 2010-09-30 | 2011-05-11 | 北京大学 | Three-dimensional integrated structure and production methods thereof |
| CN102583220A (en) * | 2012-03-29 | 2012-07-18 | 江苏物联网研究发展中心 | Wafer-level vacuum packaged infrared detector and manufacturing method thereof |
| CN104370271A (en) * | 2014-09-29 | 2015-02-25 | 武汉新芯集成电路制造有限公司 | Micro-electromechanical systems (MEMS) device assembling technology |
| CN104465420A (en) * | 2013-09-18 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for acquiring the resistance of water-level bonding structure and semiconductor structure thereof |
| CN104867865A (en) * | 2015-03-31 | 2015-08-26 | 武汉新芯集成电路制造有限公司 | Lead process for wafer three-dimensional integration |
| CN105513983A (en) * | 2014-09-26 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN105679702A (en) * | 2016-01-27 | 2016-06-15 | 武汉新芯集成电路制造有限公司 | Through silicon via interconnection process for bonded wafer and bonded wafer |
| CN105826243A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
-
2017
- 2017-11-15 CN CN201711131170.3A patent/CN107731783A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050139954A1 (en) * | 2003-12-30 | 2005-06-30 | Pyo Sung G. | Radio frequency semiconductor device and method of manufacturing the same |
| CN101656217A (en) * | 2008-08-18 | 2010-02-24 | 中芯国际集成电路制造(上海)有限公司 | System-in-package method |
| CN102050418A (en) * | 2010-09-30 | 2011-05-11 | 北京大学 | Three-dimensional integrated structure and production methods thereof |
| CN102583220A (en) * | 2012-03-29 | 2012-07-18 | 江苏物联网研究发展中心 | Wafer-level vacuum packaged infrared detector and manufacturing method thereof |
| CN104465420A (en) * | 2013-09-18 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for acquiring the resistance of water-level bonding structure and semiconductor structure thereof |
| CN105513983A (en) * | 2014-09-26 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN104370271A (en) * | 2014-09-29 | 2015-02-25 | 武汉新芯集成电路制造有限公司 | Micro-electromechanical systems (MEMS) device assembling technology |
| CN105826243A (en) * | 2015-01-09 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Wafer bonding method and wafer bonding structure |
| CN104867865A (en) * | 2015-03-31 | 2015-08-26 | 武汉新芯集成电路制造有限公司 | Lead process for wafer three-dimensional integration |
| CN105679702A (en) * | 2016-01-27 | 2016-06-15 | 武汉新芯集成电路制造有限公司 | Through silicon via interconnection process for bonded wafer and bonded wafer |
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Application publication date: 20180223 |
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