CN109152225A - A kind of buried via hole method for plugging of holes on high density interconnected printed circuit board - Google Patents
A kind of buried via hole method for plugging of holes on high density interconnected printed circuit board Download PDFInfo
- Publication number
- CN109152225A CN109152225A CN201811216625.6A CN201811216625A CN109152225A CN 109152225 A CN109152225 A CN 109152225A CN 201811216625 A CN201811216625 A CN 201811216625A CN 109152225 A CN109152225 A CN 109152225A
- Authority
- CN
- China
- Prior art keywords
- via hole
- circuit board
- buried via
- consent
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
It the invention discloses a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board, comprises the following steps that (1) takes each straton plate of HDI circuit board and by it by layer serialization, circuit then is carried out to inner- electron plate, pattern makes and detection；(2) by internal layer daughter board and from the inside to the outside first pair be located at inner- electron plate two sides and need buried via hole, the daughter board of consent is carried out by serialization order fixing layer consolidation, then carry out circuit, pattern production and detection；(3) cleaning and roughening treatment are sequentially carried out to the copper surface for the daughter board for needing buried via hole, consent using polish-brush, pickling, buried via hole, consent processing then is carried out to daughter board, then flatten processing again；(4) by second pair from the inside to the outside be located at inner- electron plate two sides and need buried via hole, the daughter board of consent is carried out lamination is fixed by the circuit board that serialization order is handled with step (3) and is integrated, then step (3) are repeated, holes on high density interconnected printed circuit board is sequentially made with this rule, the program is at low cost, implements reliable.
Description
Technical field
The invention belongs to method for producing circuit board field, the buried via hole consent of especially a kind of holes on high density interconnected printed circuit board
Method.
Background technique
The method that existing high density printed wiring board buried via hole consent generally uses filling holes with resin that ceramics is added to brush is made, and leads
Want disadvantage as follows: a. filling holes with resin ink is expensive, and processing is 10 times of common ink；B. filling holes with resin uses vacuum taphole machine plug
Hole machine price is expensive；C. filling holes with resin consent fortress is quick-fried, and ceramic brushing is walked after consent and is polished.
Summary of the invention
The case where based on the prior art, at low cost, process that the purpose of the present invention is to provide one kind is simply and implementation is reliable
Holes on high density interconnected printed circuit board buried via hole method for plugging.
In order to realize above-mentioned technical purpose, the technical solution adopted by the present invention are as follows:
A kind of buried via hole method for plugging of holes on high density interconnected printed circuit board comprising following specific steps:
(1) it takes each straton plate of HDI circuit board and by it by layer serialization, electricity then is carried out to inner- electron plate according to default
Road, pattern production and detection；
(2) by internal layer daughter board and from the inside to the outside first pair be located at inner- electron plate two sides and need buried via hole, consent daughter board into
Row presses serialization order fixing layer consolidation, then carries out circuit, pattern production and detection；
(3) cleaning and roughening treatment are sequentially carried out to the copper surface for the daughter board for needing buried via hole, consent using polish-brush, pickling,
Then buried via hole, consent processing are carried out to daughter board by predeterminated position, then flattens processing again；
(4) by second pair from the inside to the outside be located at inner- electron plate two sides and need buried via hole, the daughter board of consent is carried out by serialization time
The circuit board that sequence is handled with step (3) is fixed lamination and is integrated, then repeatedly step (3), and with this rule sequentially to institute
Daughter board progress buried via hole, consent, leveling and the lamination of buried via hole, consent in need are fixed, and holes on high density interconnected printed circuit board is made.
As a preferred method, further, in step (1), the HDI circuit board is 6 layer circuit boards, lamination knot
Structure is 1+4+1.
As another preferred embodiment, further, in step (1), the HDI circuit board is 8 layer circuit boards, lamination
Structure is 1+1+4+1+1.
Further, in step (3), circuit board after cleaned and roughening treatment to buried via hole, the time interval of consent processing
No more than 4h.
Further, in step (3), the time that buried via hole, consent are handled is no more than for 24 hours.
Further, in step (3), consent processing carries out consent using ink.
Preferably, model Taiyo PSR-4000 or the Taiyo PF9 of the ink.
Further, in step (4), circuit board daughter board is after leveling is handled, and also through overbaking dehumidification treatments, then carries out again
Lamination is fixed.
Preferably, the baking temperature of the baking dehumidification treatments is 90 ± 5 DEG C.
Preferably, the baking time of the baking dehumidification treatments is 30min.
Using above-mentioned technical solution, compared with prior art, the present invention it has the beneficial effect that the present invention program
By the technique of optimization buried via hole, consent, while increasing levelling processing and consent baking processing, improves high density interconnection printing electricity
Product quality of the road plate after buried via hole, consent, in addition, which reduce the oil close to 90% for compared to existing traditional technology
Black use cost (reduction usage amount), and shorten process flow, about 3h is paid and shortened to the flow operations for having saved 50%
Process time.
Specific embodiment
A kind of buried via hole method for plugging of holes on high density interconnected printed circuit board comprising following specific steps:
(1) it takes each straton plate of HDI circuit board and by it by layer serialization, electricity then is carried out to inner- electron plate according to default
Road, pattern production and detection；
(2) by internal layer daughter board and from the inside to the outside first pair be located at inner- electron plate two sides and need buried via hole, consent daughter board into
Row presses serialization order fixing layer consolidation, then carries out circuit, pattern production and detection；
(3) cleaning and roughening treatment are sequentially carried out to the copper surface for the daughter board for needing buried via hole, consent using polish-brush, pickling,
Then by predeterminated position to daughter board carry out buried via hole, consent processing, then flatten processing again, wherein consent processing use ink into
The time interval of row consent, circuit board to buried via hole, consent processing after cleaned and roughening treatment is no more than 4h, in addition, buried via hole,
Consent processing time be no more than for 24 hours, it is preferred that the model of the ink can with but be not limited to Taiyo PSR-4000 or
The amalgamation of Taiyo PF9, ink and pressing PP are good, and avoiding binding force extremely causes to be layered plate bursting, in addition, ink viscosity is surveyed
Amount is subject to Prink ink cup and is just covered by ink.It can be added when viscosity is higher and open grease reduction viscosity in right amount；When viscosity is relatively low
A period of time can be stood or the appropriate crude oil of addition improves viscosity, re-measure viscosity after stirring sufficiently, viscosity is within the specified scope
Can use, ink viscosity read method be viscosimeter mark it is whole be worth+estimate readings；I.e. if viscosity is 100-110 on viscosimeter
Between when, viscosity read method is that 110- visually estimates readings or 100+ visually estimates readings；
(4) by second pair from the inside to the outside be located at inner- electron plate two sides and need buried via hole, the daughter board of consent is carried out by serialization time
The circuit board that sequence is handled with step (3) is fixed lamination and is integrated, then repeatedly step (3), and with this rule sequentially to institute
Daughter board progress buried via hole, consent, leveling and the lamination of buried via hole, consent in need are fixed, and holes on high density interconnected printed circuit board is made,
In, circuit board daughter board is after leveling is handled, and also through overbaking dehumidification treatments, then carries out lamination fixation again, it is preferred that the baking
The baking temperature of roasting dehumidification treatments is 90 ± 5 DEG C；Preferably, the baking time of the baking dehumidification treatments is 30min.
The folded structure number of plies for the HDI circuit board that the present invention program is applicable in can be 6 layer circuit boards, laminated construction 1+4+
1；It is readily applicable to 8 layers of HDI circuit board, laminated construction 1+1+4+1+1.
Further specific implementation parameter as the present invention program；
The design parameter for burying plug is as follows:
Wherein, ink dot is the hole for burying plug, shelves point design D+6 under consent；Consent deep-controlled 70-90%, FAA first article assurance OK
Volume production afterwards.
In addition, pressing is handled using hot press, the specific formula parameter of parameter and pressing is as follows:
Heating in bonding processes is unsuitable too fast, and should confirm that circuit board can be combined effectively with anti-solder ink, temperature
The parameter that heats up is as follows:
The foregoing is merely presently preferred embodiments of the present invention, all equivalent changes done according to scope of the present invention patent
With modification, covering scope of the invention is come under.
Claims (10)
1. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board, it is characterised in that: it is comprised the following specific steps that:
(1) it takes each straton plate of HDI circuit board and by it by layer serialization, circuit, figure then is carried out to inner- electron plate according to default
Sample production and detection；
(2) by internal layer daughter board and from the inside to the outside first pair be located at inner- electron plate two sides and need buried via hole, the daughter board of consent carry out by
Then serialization order fixing layer consolidation carries out circuit, pattern production and detection；
(3) cleaning and roughening treatment are sequentially carried out to the copper surface for the daughter board for needing buried via hole, consent using polish-brush, pickling, then
Buried via hole, consent processing are carried out to daughter board by predeterminated position, then flatten processing again；
(4) by second pair from the inside to the outside be located at inner- electron plate two sides and need buried via hole, the daughter board of consent carry out by serialization order with
The circuit board of step (3) processing is fixed lamination and is integrated, then repeatedly step (3), and with this rule sequentially to all need
Want buried via hole, the daughter board of consent carries out buried via hole, consent, leveling and lamination and fixes, obtained holes on high density interconnected printed circuit board.
2. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board according to claim 1, it is characterised in that: step
Suddenly in (1), the HDI circuit board is 6 layer circuit boards, laminated construction 1+4+1.
3. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board according to claim 1, it is characterised in that: step
Suddenly in (1), the HDI circuit board is 8 layer circuit boards, laminated construction 1+1+4+1+1.
4. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board according to claim 1, it is characterised in that:
In step (3), the time interval of circuit board to buried via hole, consent processing after cleaned and roughening treatment is no more than 4 h.
5. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board according to claim 1, it is characterised in that:
In step (3), the time that buried via hole, consent are handled is no more than 24 h.
6. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board according to claim 1, it is characterised in that: step
Suddenly in (3), consent processing carries out consent using ink.
7. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board according to claim 6, it is characterised in that:
Model Taiyo PSR-4000 or the Taiyo PF9 of the ink.
8. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board according to claim 1, it is characterised in that: step
Suddenly in (4), circuit board daughter board is after leveling is handled, and also through overbaking dehumidification treatments, then carries out lamination fixation again.
9. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board according to claim 8, it is characterised in that:
The baking temperature of the baking dehumidification treatments is 90 ± 5 DEG C.
10. a kind of buried via hole method for plugging of holes on high density interconnected printed circuit board according to claim 8, it is characterised in that:
The baking time of the baking dehumidification treatments is 30 min.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811216625.6A CN109152225A (en) | 2018-10-18 | 2018-10-18 | A kind of buried via hole method for plugging of holes on high density interconnected printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811216625.6A CN109152225A (en) | 2018-10-18 | 2018-10-18 | A kind of buried via hole method for plugging of holes on high density interconnected printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109152225A true CN109152225A (en) | 2019-01-04 |
Family
ID=64808582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811216625.6A Pending CN109152225A (en) | 2018-10-18 | 2018-10-18 | A kind of buried via hole method for plugging of holes on high density interconnected printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109152225A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110691478A (en) * | 2019-09-18 | 2020-01-14 | 九江明阳电路科技有限公司 | Method and system for manufacturing board for testing IST (integrated test) |
| CN110708888A (en) * | 2019-09-18 | 2020-01-17 | 九江明阳电路科技有限公司 | Method and system for manufacturing multilayer printing plate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110691478A (en) * | 2019-09-18 | 2020-01-14 | 九江明阳电路科技有限公司 | Method and system for manufacturing board for testing IST (integrated test) |
| CN110708888A (en) * | 2019-09-18 | 2020-01-17 | 九江明阳电路科技有限公司 | Method and system for manufacturing multilayer printing plate |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190104 |
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| RJ01 | Rejection of invention patent application after publication |