CN105161426A - Conductive substrate and manufacturing method thereof - Google Patents
Conductive substrate and manufacturing method thereof Download PDFInfo
- Publication number
- CN105161426A CN105161426A CN201510604563.6A CN201510604563A CN105161426A CN 105161426 A CN105161426 A CN 105161426A CN 201510604563 A CN201510604563 A CN 201510604563A CN 105161426 A CN105161426 A CN 105161426A
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- CN
- China
- Prior art keywords
- hole
- perforate
- aperture
- electrically
- perforates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
Abstract
The invention discloses a conductive substrate and a manufacturing method thereof. Firstly, an insulated substrate is provided, the insulated substrate is provided with a plurality of patterned through holes passing through the insulated substrate, each patterned through hole comprises a first open hole, a hole and a second open hole from bottom to top, the aperture of the first open hole is larger than or the same as that of the hole, the aperture of the second open hole is larger than or the same as that of the hole, and the first open hole, the hole and the second open hole are communicated mutually; and then, a conductive material is formed in all first open holes, all the holes and all the second open holes and all holes are filled to enable a conductive gasket to form in all first open holes and all second open holes. The conductive gasket is formed in the through holes of the insulated substrate, and the purpose of simplifying the integrated circuit process is achieved.
Description
Technical field
The invention relates to a kind of conduction technology, and especially in regard to a kind of electrically-conductive backing plate and preparation method thereof.
Background technology
Semiconductor integrated circuit (IC) industry has experienced the growth of too fast speed.The technological progress of IC material and design makes the production of IC ceaselessly push away from generation to generation newly, and there is less and more complicated circuit comparatively front of each generation from generation to generation.But these progressive complexity too increasing manufacture IC processing procedure, therefore IC processing procedure also needs same progress and could realize more advanced integrated circuit (IC) processing procedure.In the process of IC innovation, the functional density quantity of interconnection device (that is on each chip area) increases at large, but physical dimension (that is the minimal modules can created in processing procedure or line) is also more and more less.The processing procedure of these minifications usually can increase product usefulness and provide lower relevant cost.But the decline of some size also can cause the complexity of IC processing procedure.In order to solve the problem, corresponding development should should be had on IC processing procedure.
For example, in the conventional technology, external hanging type (out-cell) is if when contact panel is for installing capacitance type fingerprint contactor control device, can be do on a substrate by fingerprint contactor control device, and the some of the Making programme of this kind of fingerprint contactor control device can be identical with IC processing procedure.The Making programme of this fingerprint contactor control device, as shown in Fig. 1 a to Fig. 1 g, in fig 1 a, first provides an insulated substrate 12 with plural through hole 10.Then, as shown in Figure 1 b, a conducting resinl 14 is filled in through hole 10, to fill up.Come again, shown in Fig. 1 c, carry out grinding (polish) in different two surfaces of insulated substrate 12, two of conducting resinl 14 surfaces are flushed with two surfaces of insulated substrate 12.After grinding, as shown in Figure 1 d, a sensing metal level 16 is formed in the bottom surface of insulated substrate 12, to be electrically connected with conducting resinl 14.Then, as shown in fig. le, form a diaphragm (over-coatinglayer) 18 in the bottom surface of insulated substrate 12, cover sensing metal level 16 with part.Come, as shown in Figure 1 f, the end face in insulated substrate 12 forms a fingerprint metal level 20, to be electrically connected with conducting resinl 14 again.Finally, as shown in Figure 1 g, the end face in insulated substrate 12 sequentially forms a black-matrix layer (blackmatrixlayer) 22 and a rigid protective layer (hard-coating) 24, to cover fingerprint metal level 20.The flow process of above-mentioned Fig. 1 a to Fig. 1 f is traditional IC processing procedure.From the above, whole processing procedure is totally eight steps, comparatively complicated.
Therefore, the present invention is for above-mentioned puzzlement, proposes a kind of electrically-conductive backing plate and preparation method thereof, to solve existing produced problem.
Summary of the invention
Main purpose of the present invention; be to provide a kind of electrically-conductive backing plate and preparation method thereof; it offers plurality of patterns through hole in an insulated substrate; with in wherein filling up conduction material; and then in omission conventional art, form the step of metal level and diaphragm (over-coatinglayer), reduce the complexity of integrated circuit (IC) processing procedure.
For reaching above-mentioned purpose, the invention provides a kind of electrically-conductive backing plate, it comprises an insulated substrate and to conduct electricity material.Insulated substrate has the plural patterning through hole running through self, each patterning through hole from bottom to top comprises one first perforate (window), a hole and one second perforate, the aperture of the first perforate is more than or equal to the aperture of hole, the aperture of the second perforate is more than or equal to the aperture of hole, and the first perforate, hole and the second perforate interconnect.Conduction material fills up all first perforates, all holes and all second perforates, to form conductive connection pads (pad) in all first perforates and all second perforates.
The present invention also provides a kind of manufacture method of electrically-conductive backing plate, first, one insulated substrate with the plural patterning through hole running through self is provided, each patterning through hole from bottom to top comprises one first perforate, a hole and one second perforate, the aperture of the first perforate is more than or equal to the aperture of hole, the aperture of the second perforate is more than or equal to the aperture of hole, and the first perforate, hole and the second perforate interconnect.Then, a conduction material is formed in all first perforates, all holes and all second perforates, to form conductive connection pads in all first perforates and all second perforates.
Hereby further understand and understanding for making your juror more have architectural feature of the present invention and effect of reaching, careful assistant is with preferred embodiment figure and coordinate detailed description, illustrates as after.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 g is each step structure cutaway view of the making fingerprint contactor control device of prior art;
Fig. 2 is the structure cutaway view of the first embodiment of the present invention;
Fig. 3 a to Fig. 3 d is each step structure cutaway view of making first embodiment of the present invention;
Fig. 4 is the structure cutaway view of the second embodiment of the present invention;
Fig. 5 a to Fig. 5 e is each step structure cutaway view of making second embodiment of the present invention.
Drawing reference numeral illustrates:
10 through holes
12 insulated substrates
14 conducting resinls
16 sensing metal levels
18 diaphragms
20 fingerprint metal levels
22 black-matrix layer
24 rigid protective layers
26 insulated substrates
28 conduction materials
30 patterning through holes
32 first perforates
34 holes
36 second perforates
38 insulating supporting substrates
40 light shield layers
42 protective layers
The realization of the object of the invention, functional characteristics and advantage will in conjunction with the embodiments, are described further with reference to accompanying drawing.
Embodiment
Below first introduce the first embodiment of the present invention, refer to Fig. 2.The first embodiment of the present invention comprises an insulated substrate 26 and and conducts electricity material 28, the material of insulated substrate 26 is glass, polymethyl methacrylate (PMMA), Merlon (PC), polyimide (PI) or sapphire, and conduction material 28 is for conducting resinl.Insulated substrate 26 has the plural patterning through hole 30 running through self, each patterning through hole 30 from bottom to top comprises one first perforate (window) 32, hole 34 and one second perforate 36, the aperture of the first perforate 32 is more than or equal to the aperture of hole 34, the aperture of the second perforate 36 is more than or equal to the aperture of hole 34, and the first perforate 32, hole 34 and the second perforate 36 interconnect.Conduction material 28 fills up all first perforates 32, all holes 34 and all second perforates 36, to form conductive connection pads (pad) in all first perforates 32 with all second perforates 36.In design, the aperture of hole 34 is greater than 10 microns, and the degree of depth of the first perforate 32 and the second perforate 36 is all greater than 5 microns.Because integrated circuit (IC) all must comprise a substrate, the electrically-conductive backing plate of this first embodiment just can belong to the some of IC.
Below introduce the Making programme of the first embodiment of the present invention, refer to Fig. 3 a to Fig. 3 d, this Making programme is the some belonging to IC processing procedure.First, as shown in Figure 3 a, provide an insulating supporting substrate 38, its material is glass, polymethyl methacrylate (PMMA), Merlon, polyimide or sapphire.Then, as shown in Figure 3 b, all patterning through holes 30 are offered in insulating supporting substrate 38, to obtain insulated substrate 26, wherein insulated substrate 26 is identical with insulating supporting substrate 38 material, and each patterning through hole 30 from bottom to top comprises one first perforate (window) 32, hole 34 and one second perforate 36, the aperture of the first perforate 32 is more than or equal to the aperture of hole 34, the aperture of the second perforate 36 is more than or equal to the aperture of hole 34, and the first perforate 32 again, hole 34 and the second perforate 36 interconnect.Come again, as shown in Figure 3 c, form conduction material 28 and with all second perforates 36, and filled up in all first perforates 32, all holes 34, to form conductive connection pads in all first perforates 32 with all second perforates 36.Finally, as shown in Figure 3 d, carry out a grinding (polish) step, it adopts cmp (CMP) mode to grind conduction material 28, with two surfaces on the surface and insulated substrate 26 that flush conduction material 28.In the processing procedure of the first embodiment; because conductive connection pads is arranged in the first perforate 32 and the second perforate 36 of insulated substrate 26; and the surface of conductive connection pads flushes with the surface of insulated substrate 26; so do not need the step of formation diaphragm (over-coatinglayer) in conventional art and metal level, to reach the object of the complexity reducing integrated circuit manufacture process.
In addition, the step of above-mentioned Fig. 3 a and Fig. 3 b can also a step realize, namely the insulated substrate 26 with the plural patterning through hole 30 running through self is directly provided, and each patterning through hole 30 from bottom to top comprises one first perforate 32, hole 34 and one second perforate 36, the aperture of the first perforate 32 is more than or equal to the aperture of hole 34, the aperture of the second perforate 36 is more than or equal to the aperture of hole 34, first perforate 32 again, hole 34 and the second perforate 36 interconnect, as shown in Figure 3 b, to simplify processing procedure.
Below introduce the second embodiment of the present invention again, refer to Fig. 4.The second embodiment of the present invention comprises insulated substrate 26, conduction material 28, light shield layer 40 and a protective layer 42; the material of insulated substrate 26 is glass, polymethyl methacrylate, Merlon, polyimide or sapphire; the material of protective layer 42 is sapphire, glass or pottery, and conduction material 28 and light shield layer 40 are respectively for conducting resinl and black-matrix layer.Insulated substrate 26 has the plural patterning through hole 30 running through self, each patterning through hole 30 from bottom to top comprises one first perforate (window) 32, hole 34 and one second perforate 36, the aperture of the first perforate 32 is more than or equal to the aperture of hole 34, the aperture of the second perforate 36 is more than or equal to the aperture of hole 34, and the first perforate 32, hole 34 and the second perforate 36 interconnect.Conduction material 28 fills up all first perforates 32, all holes 34 and all second perforates 36, to form conductive connection pads in all first perforates 32 with all second perforates 36.In design, the aperture of hole 34 is greater than 10 microns, and the degree of depth of the first perforate 32 and the second perforate 36 is all greater than 5 microns.Light shield layer 40 is provided at conduction material 28 with on insulated substrate 26, and protective layer 42 is provided on light shield layer 40.The electrically-conductive backing plate of this second embodiment can as capacitance type fingerprint sensing apparatus.
Below introduce the Making programme of the second embodiment of the present invention, refer to Fig. 5 a to Fig. 5 e, wherein the flow process of Fig. 5 a to Fig. 5 d belongs to IC processing procedure.First, as shown in Figure 5 a, provide an insulating supporting substrate 38, its material is glass, polymethyl methacrylate, Merlon, polyimide or sapphire.Then, as shown in Figure 5 b, all patterning through holes 30 are offered in insulating supporting substrate 38, to obtain insulated substrate 26, wherein insulated substrate 26 is identical with insulating supporting substrate 38 material, and each patterning through hole 30 from bottom to top comprises one first perforate (window) 32, hole 34 and one second perforate 36, the aperture of the first perforate 32 is more than or equal to the aperture of hole 34, the aperture of the second perforate 36 is more than or equal to the aperture of hole 34, and the first perforate 32 again, hole 34 and the second perforate 36 interconnect.Come again, as shown in Figure 5 c, form conduction material 28 and with all second perforates 36, and filled up in all first perforates 32, all holes 34, to form conductive connection pads in all first perforates 32 with all second perforates 36.After filling up, as fig 5d, carry out a grinding steps, it adopts cmp mode to grind conduction material 28, with two surfaces on the surface and insulated substrate 26 that flush conduction material 28.Then, as depicted in fig. 5e, sequentially formed light shield layer 40 with protective layer 42 in insulated substrate 26 with on conduction material 28.In the processing procedure of the second embodiment; because conductive connection pads is arranged in the first perforate 32 and the second perforate 36 of insulated substrate 26; and the surface of conductive connection pads flushes with the surface of insulated substrate 26; so do not need the step of formation diaphragm in conventional art and metal level, to reach the object of the complexity reducing integrated circuit manufacture process.
In addition, the step of above-mentioned Fig. 5 a and Fig. 5 b can also a step realize, namely the insulated substrate 26 with the plural patterning through hole 30 running through self is directly provided, and each patterning through hole 30 from bottom to top comprises one first perforate 32, hole 34 and one second perforate 36, the aperture of the first perforate 32 is more than or equal to the aperture of hole 34, the aperture of the second perforate 36 is more than or equal to the aperture of hole 34, first perforate 32 again, hole 34 and the second perforate 36 interconnect, as shown in Figure 5 b, to simplify processing procedure.
In sum, conduction material is formed in the patterning through hole of insulated substrate by the present invention, the surface of conductive connection pads is flushed, to reduce the complexity of integrated circuit manufacture process with substrate surface.
Claims (13)
1. an electrically-conductive backing plate, is characterized in that, comprises:
One insulated substrate, there is the plural patterning through hole running through self, each this patterning through hole from bottom to top comprises one first perforate, a hole and one second perforate, the aperture of this first perforate is more than or equal to the aperture of this hole, the aperture of this second perforate is more than or equal to this aperture of this hole, and this first perforate, this hole and this second perforate interconnect; And
One conduction material, it fills up those first perforates, those holes and those the second perforates, to form conductive connection pads in those first perforates and those the second perforates.
2. electrically-conductive backing plate as claimed in claim 1, it is characterized in that, more comprise a light shield layer, it is provided on this conduction material and this insulated substrate.
3. electrically-conductive backing plate as claimed in claim 2, it is characterized in that, this light shield layer is black-matrix layer.
4. electrically-conductive backing plate as claimed in claim 2, it is characterized in that, more comprise a protective layer, it is provided on this light shield layer.
5. electrically-conductive backing plate as claimed in claim 4, it is characterized in that, the material of this protective layer is sapphire, glass or pottery.
6. electrically-conductive backing plate as claimed in claim 1, it is characterized in that, this conduction material is conducting resinl.
7. electrically-conductive backing plate as claimed in claim 1, it is characterized in that, the material of this insulated substrate is glass, polymethyl methacrylate, Merlon, polyimide or sapphire.
8. electrically-conductive backing plate as claimed in claim 1, it is characterized in that, the aperture of this hole is greater than 10 microns, and the degree of depth of this first perforate and this second perforate is all greater than 5 microns.
9. a manufacture method for electrically-conductive backing plate, is characterized in that, comprises the following step:
One insulating supporting substrate is provided;
Plural patterning through hole is offered in this insulating supporting substrate, to obtain an insulated substrate, each this patterning through hole from bottom to top comprises one first perforate, a hole and one second perforate, the aperture of this first perforate is more than or equal to the aperture of this hole, the aperture of this second perforate is more than or equal to this aperture of this hole, and this first perforate, this hole and this second perforate interconnect; And
Form a conduction material in those first perforates, those holes and those the second perforates, to form conductive connection pads in those first perforates and those the second perforates.
10. the manufacture method of electrically-conductive backing plate as claimed in claim 9, is characterized in that, more comprise a grinding steps, and it is this conduction material of grinding, with two surfaces on the surface and this insulated substrate that flush this conduction material.
The manufacture method of 11. electrically-conductive backing plates as claimed in claim 10, is characterized in that, this grinding steps performs in cmp mode.
The manufacture method of 12. electrically-conductive backing plates as claimed in claim 10, is characterized in that, more comprises the step of formation one light shield layer on this insulated substrate and this conduction material.
The manufacture method of 13. electrically-conductive backing plates as claimed in claim 12, is characterized in that, more comprises the step of formation one protective layer on this light shield layer.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510604563.6A CN105161426A (en) | 2015-09-21 | 2015-09-21 | Conductive substrate and manufacturing method thereof |
| TW104134806A TWI554166B (en) | 2015-09-21 | 2015-10-23 | Conductive substrate and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510604563.6A CN105161426A (en) | 2015-09-21 | 2015-09-21 | Conductive substrate and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105161426A true CN105161426A (en) | 2015-12-16 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510604563.6A Pending CN105161426A (en) | 2015-09-21 | 2015-09-21 | Conductive substrate and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105161426A (en) |
| TW (1) | TWI554166B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114899197A (en) * | 2022-06-20 | 2022-08-12 | 业成科技（成都）有限公司 | Display panel, display panel manufacturing method and display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101351088A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
| US20150008578A1 (en) * | 2010-12-22 | 2015-01-08 | Intel Corporation | Device packaging with substrates having embedded lines and metal defined pads |
| CN104751127A (en) * | 2015-03-06 | 2015-07-01 | 南昌欧菲生物识别技术有限公司 | Fingerprint identification device, touch screen and electronic equipment |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100476558B1 (en) * | 2002-05-27 | 2005-03-17 | 삼성전기주식회사 | Image sensor module and construction method |
| TWI256146B (en) * | 2005-07-21 | 2006-06-01 | Siliconware Precision Industries Co Ltd | Sensor semiconductor device and fabrication method thereof |
| KR100704915B1 (en) * | 2005-09-15 | 2007-04-09 | 삼성전기주식회사 | Printed circuit board having fine pattern and manufacturing method thereof |
| CN104063696A (en) * | 2014-07-02 | 2014-09-24 | 南昌欧菲生物识别技术有限公司 | Fingerprint identification detection assembly and terminal device containing same |
-
2015
- 2015-09-21 CN CN201510604563.6A patent/CN105161426A/en active Pending
- 2015-10-23 TW TW104134806A patent/TWI554166B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101351088A (en) * | 2007-07-17 | 2009-01-21 | 欣兴电子股份有限公司 | Inside imbedded type line structure and technique thereof |
| US20150008578A1 (en) * | 2010-12-22 | 2015-01-08 | Intel Corporation | Device packaging with substrates having embedded lines and metal defined pads |
| CN104751127A (en) * | 2015-03-06 | 2015-07-01 | 南昌欧菲生物识别技术有限公司 | Fingerprint identification device, touch screen and electronic equipment |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114899197A (en) * | 2022-06-20 | 2022-08-12 | 业成科技（成都）有限公司 | Display panel, display panel manufacturing method and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201713175A (en) | 2017-04-01 |
| TWI554166B (en) | 2016-10-11 |
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