CN107731678A - 三维存储器的制作方法 - Google Patents

三维存储器的制作方法 Download PDF

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CN107731678A
CN107731678A CN201710733237.4A CN201710733237A CN107731678A CN 107731678 A CN107731678 A CN 107731678A CN 201710733237 A CN201710733237 A CN 201710733237A CN 107731678 A CN107731678 A CN 107731678A
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CN107731678B (zh
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赵新梅
霍宗亮
唐兆云
隋翔宇
陆智勇
江润峰
王香凝
石晓静
王攀
王猛
闫伟明
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Yangtze Memory Technologies Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
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    • H01L21/31111Etching inorganic layers by chemical means
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    • HELECTRICITY
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation

Abstract

一种三维存储器的制作的方法,采用一步干蚀刻法,包括:蚀刻顶层多晶硅,停留在氮化物上;然后蚀刻硬掩膜SiN层,停留在氧化物上。其中蚀刻剂需要对SiN与氧化物具有高选择性,以使得氧化物的损失小于50埃。通过采用一步干蚀刻法,减少CMP的使用,以及取代通过湿蚀刻除去硬掩膜SiN,有利于消除了CMP工艺中的负载效应引起的不同阵列区域厚度的变化,同时有利于简化工艺,降低成本。

Description

三维存储器的制作方法
技术领域
本发明涉及一种三维存储器的制作方法,尤其涉及一种去除沟道通孔的多晶硅层和硬掩膜层的方法。
背景技术
蚀刻技术是半导体制备中常使用的技术。蚀刻是将材料使用化学反应或物理撞击作用而移除的技术。蚀刻技术可以分为湿蚀刻和干蚀刻两类。湿法刻蚀是将刻蚀材料浸泡在腐蚀液内进行腐蚀的技术。干法刻蚀是用等离子体进行薄膜刻蚀的技术。当气体以等离子体形式存在时,它具备两个特点:一方面等离子体中的这些气体化学活性比常态下时要强很多,根据被刻蚀材料的不同,选择合适的气体,就可以更快地与材料进行反应,实现刻蚀去除的目的;另一方面,还可以利用电场对等离子体进行引导和加速,使其具备一定能量,当其轰击被刻蚀物的表面时,会将被刻蚀物材料的原子击出,从而达到利用物理上的能量转移来实现刻蚀的目的。因此,干法刻蚀是晶圆片表面物理和化学两种过程平衡的结果。
化学机械研磨(CMP;Chemical Mechanical Polishing)为半导体晶片的一种平坦化工艺,特别是用在填沟工艺中。化学机械研磨亦称为化学机械抛光,其原理是化学腐蚀作用和机械去除作用相结合的加工技术,是目前机械加工中唯一可以实现表面全局平坦化的技术。CMP利用物理与化学上的协同作用来研磨晶片研磨时将晶片放置在研磨垫上,从晶背施加压力,并使晶片与研磨垫作反向旋转,而带有研磨粒子与反应性化学成份的研磨浆在研磨时被配输到研磨垫表面。CMP可以真正达到晶片表面全面性的平坦化。
研磨制程根据研磨对象不同主要分为:硅研磨(Poly CMP)、硅氧化物研磨(Silicon oxide CMP)、碳化硅研磨(Silicon carbide CMP)、钨研磨(W CMP)和铜研磨(CuCMP)。化学机械研磨技术综合了化学研磨和机械研磨的优势。单纯的化学研磨,表面精度较高,损伤低,完整性好,不容易出现表面/亚表面损伤,但是研磨速率较慢,材料去除效率较低,不能修正表面型面精度,研磨一致性比较差;单纯的机械研磨,研磨一致性好,表面平整度高,研磨效率高,但是容易出现表面层/亚表面层损伤,表面粗糙度值比较低。化学机械研磨吸收了两者各自的优点,可以在保证材料去除效率的同时,获得较完美的表面,得到的平整度比单纯使用这两种研磨要高出1-2个数量级,并且可以实现纳米级到原子级的表面粗糙度。
然而CMP工艺会有图案化效应的问题。当图案密度不同时会有所谓的“微负载效应(micro-loading effect)”,因而降低图案尺寸的一致性。微负载效应是当同时蚀刻或研磨高密度图案与低密度图案时,由于两个区域的蚀刻/研磨速率不同所造成。因为蚀刻/研磨的反应在不同图案密度的区域变得局部过高或过低,加上大量的蚀刻反应产物无法顺利排出,使得蚀刻速率不一致。当图案的密度差异很大时,会使研磨后的膜厚产生极大的差异。上述的不一致会造成所谓的碟化(dishing)效应,碟化指低图案密度的位置,因为其研磨速率大于高图案密度区,因而形成碟状的表面。
如图1所示,现有技术去除沟道通孔的多晶硅层和硬掩膜层的方法,包括在硬掩膜SiN层1的表面及接触孔内沉积一定深度的多晶硅层2,其中硬掩膜SiN层在硬掩膜氧化物层3之上;然后如图2所示,采用化学机械研磨法除去硬掩膜SiN上以及接触孔之内的多晶硅层2,并使得接触孔内的多晶硅层2与SiN硬掩膜层1齐平;然后,如图3所示,再采用湿蚀刻法除去SiN硬掩膜层1;然后,如图4所示,再次采用化学机械研磨法使得接触孔内的多晶硅2与去除SiN硬掩膜后的氧化物硬掩膜层高度齐平,实现多晶硅层和硬掩膜层的去除。
上述方法中多次采用了CMP工艺,由于CMP工艺在半导体上具有的微负载效应,使得不同区域的厚度不同。并且在上述方法的实施过程中,由于工艺中采用CMP工艺除去多晶硅层,以及采用湿蚀刻法除去SiN硬掩膜层,提高了工艺的成本。
如何减少使用CMP工艺和湿蚀刻工艺来降低工艺成本是目前需要解决的问题。
发明内容
本发明的目的是通过以下技术方案实现的。
针对上述存在的问题,本发明公开了一种去除沟道通孔的多晶硅层和硬掩膜层的方法,包括:在硬掩膜SiN层1表面及接触孔内沉积一定深度的多晶硅层2;
然后采用一步干蚀刻法除去硬掩膜SiN层1表面以及接触孔之内的多晶硅层2,停留在硬掩膜SiN层1上,接着继续干蚀刻除去硬掩膜SiN层1,停留在氧化物层硬掩膜层3上;
采用化学机械研磨法(CMP)使得接触孔内的多晶硅2与去除SiN硬掩膜2后露出的氧化物硬掩膜层高度齐平,实现多晶硅层和硬掩膜层的去除。
其中,干蚀刻除去硬掩膜SiN层1,停留在氧化物层硬掩膜层3上,是采用对SiN与氧化物具有高选择性的蚀刻剂进行蚀刻的。
其中氧化物为:SiO2
相对于现有技术采用CMP结合湿蚀刻技术的去除沟道通孔的多晶硅层和硬掩膜层的工艺,本发明采用一步干蚀刻法即可实现沟道通孔的多晶硅层和硬掩膜层的去除,并且避免了多次使用CMP以及湿蚀刻技术带来的问题。
所述硬掩膜层包括SiN和SiON中的一种,或者选用本领域常用的其他氮化物,并不局限于所列举的示例,所述氧化物包括硅氧化物等,也可以选用常用的氧化物。
所述硬掩膜层选用SiN和SiO2,所述硬掩膜层沉积方法可以选用化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等形成的低压化学气相沉积(LPCVD)、激光烧蚀沉积(LAD)以及选择外延生长(SEG)中的一种。
在本实施例中,采用干法蚀刻执行的蚀刻工艺包括但不限于:反应离子蚀刻(RIE)、离子束蚀刻、等离子体蚀刻或者激光切割。例如采用等离子体蚀刻,刻蚀气体可以采用基于氧气(O2-based)的气体。其中,干法蚀刻的刻蚀气体还可以是溴化氢气体、四氟化碳气体或者三氟化氮气体。需要说明的是上述蚀刻方法仅仅是示例性的,并不局限于该方法,本领域技术人员还可以选用其他常用的方法。
本发明的优点在于:
本发明公开的去除沟道通孔的多晶硅层和硬掩膜层的方法,通过采用一步干蚀刻法,相对于现有技术多次采用CMP工艺以及结合湿蚀刻技术实现沟道通孔的多晶硅层和硬掩膜层的去除,有利于消除了CMP工艺中的负载效应引起的不同阵列区域厚度的变化,同时有利于简化工艺,降低成本。
附图说明
通过阅读下文优选实施方式的详细描述,各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选实施方式的目的,而并不认为是对本发明的限制。而且在整个附图中,用相同的参考符号表示相同的部件。在附图中:
图1-4是传统的采用CMP结合湿蚀刻法去除沟道通孔的多晶硅层和硬掩膜层的工艺流程示意图;
图5-7是本发明实施例中采用干蚀刻法去除沟道通孔的多晶硅层和硬掩膜层的工艺流程示意图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式,然而应当理解,可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反,提供这些实施方式是为了能够更透彻地理解本公开,并且能够将本公开的范围完整的传达给本领域的技术人员。
参考图5-7,本实施例提供了一种去除沟道通孔的多晶硅层和硬掩膜层的的方法:
如图5所示,包括在硬掩膜SiN层1表面及接触孔内沉积一定深度的多晶硅层2;
然后如图6所示,采用一步干蚀刻法除去硬掩膜SiN层1表面以及接触孔之内的多晶硅层2,停留在硬掩膜SiN层1上,接着继续干蚀刻除去硬掩膜SiN层1,停留在氧化物层硬掩膜层3上;其中蚀刻剂需要对SiN与氧化物具有高选择性,以使得氧化物的损失小于50埃。
如图7所示,采用化学机械研磨法(CMP)使得接触孔内的多晶硅2与去除SiN硬掩膜1后露出的氧化物硬掩膜层高度齐平,实现沟道通孔的多晶硅层和硬掩膜层的去除。
所述硬掩膜层包括SiN或者选用本领域常用的其他氮化物,并不局限于所列举的示例,所述氧化物硬掩膜包括硅氧化物等,也可以选用常用的氧化物。
所述氧化物硬掩膜选用SiO2,所述硬掩膜层沉积方法可以选用化学气相沉积(CVD)法、物理气相沉积(PVD)法或原子层沉积(ALD)法等形成的低压化学气相沉积(LPCVD)、激光烧蚀沉积(LAD)以及选择外延生长(SEG)中的一种。
在本实施例中,所述干法蚀刻的蚀刻气体为包含NF3和NH3的混合物或者包含H2和NF3的混合物。
以上所述,仅为本发明较佳的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。

Claims (3)

1.一种去除沟道通孔的多晶硅层和硬掩膜层的方法,包括:在硬掩膜SiN层表面及接触孔内沉积一定深度的多晶硅层;
然后采用一步干蚀刻法除去硬掩膜SiN层表面以及接触孔之内的多晶硅层,停留在硬掩膜SiN层上,接着继续干蚀刻除去硬掩膜SiN层,停留在氧化物硬掩膜层上;
采用化学机械研磨法(CMP)使得接触孔内的多晶硅与去除SiN硬掩模后露出的氧化物硬掩膜层高度齐平,实现沟道通孔的多晶硅层和硬掩膜层的去除。
2.根据权利要求1所述的方法,其中,干蚀刻除去硬掩膜SiN层,停留在氧化物硬掩膜层上,是采用对SiN与氧化物具有高选择性的蚀刻剂进行蚀刻的。
3.根据权利要求1所述的方法,其中氧化物为SiO2
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