CN107680999A - 高功率半导体元件 - Google Patents

高功率半导体元件 Download PDF

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CN107680999A
CN107680999A CN201710609477.3A CN201710609477A CN107680999A CN 107680999 A CN107680999 A CN 107680999A CN 201710609477 A CN201710609477 A CN 201710609477A CN 107680999 A CN107680999 A CN 107680999A
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layer
electrode
semiconductor layer
high power
semiconductor
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CN107680999B (zh
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陈明钦
林奕志
杜尚儒
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Epistar Corp
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Abstract

本发明公开一种高功率半导体元件，通过在一通道层上，形成两彼此并联的二极管结构与一萧特基接触，可同时降低导通电压及电阻，提升击穿电压。

Description

高功率半导体元件
技术领域
本发明涉及一种高功率半导体元件，且特别是涉及一种高电子迁移率的高功率半导体元件。
背景技术
高电子迁移率晶体管(HEMT)，是一种包含有一个由两种不同禁带宽度的材料所形成的异质结构，例如氮化铝镓(AlGaN)层与氮化镓(GaN)层所形成的异质结构，产生具有独特的自发极化(spontaneous polarization)与压电极化(piezoelectric polarization)效应，在未掺杂的状况下，在氮化铝镓/氮化镓界面处形成高浓度二维电子气(twodimensional electron gas，2DEG)，使得载流子速度加快，通道电阻因而降低；另一方面由于能带不连续以及压电效应的优点，提高了通道载流子浓度。而2DEG中的载流子浓度提高，其电流密度也会提高，其中2DEG的浓度可高于1013cm-2。另外，氮化镓材料具有高电子迁移率，可高达2.5x105m/s，击穿电压可高达5MV/cm，因此用这种材料做成的高电子迁移率晶体管(HEMT)或萧特基二极管(SBD)具有耐高温、耐高压、高电流密度及高频操作的效果。但是在元件操作时往往因栅极的萧特基金属接点边缘的高电场增加氮化铝镓层中的应力，当达到临界的漏极－栅极电压时，就会发生结晶缺陷。这些结晶缺陷会成为深层陷阱使得电子隧道产生，从而显著造成漏电流增加，亦将使晶体管的击穿提早发生，元件的击穿电压无法提高。
发明内容
本发明的目的在于提供一种高功率半导体元件，通过在一通道层上，形成两彼此并联的二极管结构与一萧特基接触，可同时降低导通电压及电阻，提升击穿电压。
为达上述目的，本发明提供一种高功率半导体元件，包括：一基板；一通道层，形成于基板上，包含一第一区，一第二区及一第三区；一第一阻障层，形成于通道层的第一区上；一第一半导体层具有一第一导电性，形成于第一阻障层上；一第一电极，形成于第一阻障层上；一第二电极，形成于第一半导体层上；一第二阻障层，形成于通道层的第二区上；一第二半导体层具有第一导电性，形成于第二阻障层上；一第三电极，形成于第二阻障层上；一第四电极，形成于第二半导体层上；一沟槽，位于第一阻障层及第二阻障层之间；其中沟槽曝露出通道层的第三区，其中沟槽具有一底墙，底墙包含通道层的第三区；以及一连接部，覆盖沟槽内的底墙，电连接第二电极与第四电极，且连接部与通道层的第三区形成萧特基接触。
本发明另提供一种高功率半导体元件，包括：一基板；一第一PIN二极管结构，位于基板上；一第二PIN二极管结构，位于基板上；以及一具有萧特基接面的结构，位于基板上，其中第一PIN二极管结构、第二PIN二极管结构，以及具有萧特基接面的结构彼此并联。
本发明又提供一种高功率半导体元件，包括：一基板；一通道层位于基板上；一阻障层位于通道层上；一介电层位于通道层上；一第一半导体栅极位于阻障层上；一凹陷型栅极位于介电层上；一第二半导体栅极位于阻障层上；以及一连接部并联第一半导体栅极、凹陷型栅极，以及第二半导体栅极。
附图说明
图1A为本发明实施例一的高功率半导体元件1000的上视图；
图1B为本发明实施例四的高功率半导体元件4000的上视图；
图2A～图2F为本发明实施例一的高功率半导体元件1000的剖面制作工艺的示意图；
图3为本发明实施例二的高功率半导体元件2000的剖面示意图；
图4为本发明实施例三的高功率半导体元件3000的剖面示意图；
图5为本发明实施例四的高功率半导体元件4000的剖面示意图；
图6为本发明实施例五的高功率半导体元件5000的剖面示意图；
图7为本发明实施例六的高功率半导体元件6000的剖面示意图。
符号说明
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然而应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定形式实施。文中虽然以高功率半导体元件作为举例讨论的特定实施例，然而其仅为制造与使用本发明的特定方式，非用以限制本发明的范围，任何具有相似结构的半导体元件也可适用于本发明。
实施例一：
图1A绘示的是根据本发明实施例一的高功率半导体元件1000的上视图。图2F绘示的是图1A的高功率半导体元件1000沿A-A’方向的剖视图。
以下将配合图2A～图2F绘示的剖面示意图，说明根据本发明实施例一的高功率半导体元件1000的剖面制作工艺。
请参照图2A，提供一基板200，然后利用外延制作工艺，依序沉积一缓冲层210、一通道层220、一阻障层230以及一半导体层240具有一导电型。其中，基板200可为导电基板或者绝缘基板，其材料包含蓝宝石基板、碳化硅基板、或硅基板等；缓冲层210的材料可为三五族材料，例如是氮化铝(AlN)、氮化镓(GaN)、氮化铝镓(AlGaN)、或掺杂碳的氮化镓等，其作用为减少通道层220及阻障层230的晶格缺陷。在本实施例中，通道层220的厚度范围在50～300nm，形成于缓冲层210上，并具有一第一带隙，可为故意掺杂层或本质半导体层，其材料可包含氮化铟镓(InxGa(1-x)N)，0≤x<1，例如是氮化镓层。阻障层230的厚度范围在20～50nm，并具有一第二带隙，一般而言第二带隙较第一带隙高，即阻障层230的晶格常数较第一通道层220小，可为故意掺杂层或本质半导体层，其材料可包含氮化铝铟镓(AlyInzGa(1-z)N)，0<y<1，0≤z<1，例如是氮化铝镓层。半导体层240具有一导电型可包含n型或p型。在本实施例中，半导体层240为p型半导体层，其厚度范围在1～50nm，例如是3nm，其材料可包含p型氮化铝铟镓(AlyInzGa(1-z)N)，0<y<1，0≤z<1，例如是p型氮化镓层。
请参照图2B，利用光刻、蚀刻制作工艺，图案化通道层220、阻障层230及p型半导体层(半导体层)240，形成一由图案化的通道层220′、阻障层230′及p型半导体层240′所构成的半导体平台245，且通道层220′两侧具有部分裸露的第一、第二表面225a、225b，而阻障层230′两侧具有部分裸露的第三、第四表面235a、235b。
请参照图2C，形成一第一负电极(cathode)250a于阻障层230′的一侧裸露的第三表面235a上，并且自第三表面235a边缘延伸至通道层220′的一侧裸露的第一表面225a上，并且形成一第二负电极(cathode)250b于阻障层230′的另一侧裸露的第四表面235b上，并且自第四表面235b边缘延伸至通道层220′的另一侧裸露的第二表面225b上。
请参照图2D，去除部分图2C中的阻障层230′及p型半导体层240′，形成一沟槽260，且沟槽260具有一露出通道层220′表面的底墙260a及一位于底墙260a两侧的侧墙260b。此外，位于沟槽260两侧的阻障层230′及p型半导体层240′分别定义为第一阻障层230′a、第二阻障层230′b及第一p型半导体层240′a和第二p型半导体层240′b，且第一p型半导体层240′a具有邻近沟槽260的第一边缘241和一远离沟槽260的第二边缘242，第二p型半导体层240′b具有邻近沟槽260的第五边缘243和一远离沟槽260的第六边缘244。
请参照图2E，形成一第一欧姆接触层270a及一第二欧姆接触层270b于沟槽260两侧的第一p型半导体层240′a、第二p型半导体层240′b上，且第一欧姆接触层270a具有邻近沟槽260的第三边缘271和一远离沟槽260的第四边缘272，第二欧姆接触层270b具有邻近沟槽260的第七边缘273和一远离沟槽260的第八边缘274。在本实施例中，第一p型半导体层240′a的第二边缘242与第一欧姆接触层270a的第四边缘272对齐，而第二p型半导体层240′b的第六边缘244与第二欧姆接触层270b的第八边缘274对齐。在本实施例中，第一欧姆接触层270a及第二欧姆接触层270b的厚度范围在50～200nm，例如是100nm，其材料可包含氧化铟锡(indium tin oxide,ITO)或氧化铟锌(indium zinc oxide,IZO)等金属氧化物导电材料，或是镍(Ni)、金(Au)或镍金合金(NiAu)等金属导电材料。
请参照图2F，分别形成一第一正电极(anode)280a及一第二正电极(anode)280b于第一欧姆接触层270a和第二欧姆接触层270b上，此外，第一正电极280a与第二正电极280b之间还有一连接部282适顺性地覆盖沟槽260内的底墙260a及侧墙260b，且通过连接部282电性连接第一正电极280a和第二正电极280b，且连接部282与底墙260a所露出的通道层220′形成萧特基接触，二维电子气227a、227b则是分别形成于通道层220’与第一阻障层230’a以及通道层220’与第二阻障层230’b之间的异质区界面附近，完成根据本发明实施例一的高功率半导体元件1000。
本实施例的高功率半导体元件1000包含一个位于基板200上，由通道层220’、第一阻障层230′a、第一p型半导体层240′a、第一欧姆接触层270a、第一负电极250a及第一正电极280a所构成的结构，其中第一p型半导体层240′a包含例如掺杂p型杂质，通道层220’含二维电子气227a构成的负极化电荷，第一阻障层230′a含正极化电荷与负极化电荷形成电耦合，此结构可视为一第一PIN二极管结构291a，另一个位于基板200上，由通道层220’、第二阻障层230′b、第二p型半导体层240′b、第二欧姆接触层270b、第二负电极250b及第二正电极280b所构成的一第二PIN二极管结构291b。在一实施例中，位于基板200上第一PIN二极管结构291a、第二PIN二极管结构291b，通过连接部282分别连接第一正电极280a及第二正电极280b，达到彼此并联，连接部282同时与所露出的通道层220′形成萧特基接触，构成一萧特基接面的结构。
高功率半导体元件1000在顺向偏压操作下，当正极-负极电压(Vac)大于萧特基接面的起始电压(Vschottky,th)时，例如起始电压为0.8V，顺向导通电流将从第一正电极280a和第二正电极280b，通过连接部282以及连接部282与通道层220’的萧特基接面，再经由二维电子气227a、227b，流至第一负电极250a和第二负电极250b。而第一PIN二极管结构291a与第二PIN二极管结构291b将会在正极-负极电压(Vac)大于PIN二极管的起始电压(VPIN,th)时，例如起始电压为3～5V时导通并提供额外的顺向电流，可提升元件整体的顺向导通电流。另外，第一欧姆接触层270a、第二欧姆接触层270b分别形成于第一p型半导体层240′a、第二p型半导体层240′b与第一正电极280a、第二正电极280b之间，将降低第一正电极280a、第二正电极280b与第一p型半导体层240′a、第二p型半导体层240′b之间的接触电阻，使得其间形成一低阻值的接触，例如欧姆接触，使顺偏导通时能提供更多的顺向导通电流注入元件内。在逆向偏压操作下，由于第一p型半导体层240′a、第二p型半导体层240′b会吸附位于第一阻障层230′a、第二阻障层230’b的缺陷电子，将有助于防止逆偏时的漏电流产生，提升元件整体的击穿电压。
另外，由于第一正电极280a和第二正电极280b经由连接部282与沟槽260的底墙260a所露出的通道层220′形成萧特基接触，并且与二维电子气电连接，此萧特基势垒会下降，将有助于降低元件的导通电压及导通电阻。另外，第一负电极250a同时接触第一阻障层230’a与通道层220’、第二负电极250b同时接触第二阻障层230’b与通道层220’，将有助于负电极接收二维电子气227a、227b以及其他电流路径例如经由阻障层与通道层的电流，降低导通电阻，提升元件顺向电流。
实施例二：
请参照图3，其绘示的是根据本发明实施例二的高功率半导体元件2000的剖面示意图。如图3所示，高功率半导体元件2000与实施例一的高功率元件1000相似，均包括一位于基板200与缓冲层210上，由通道层220’、第一阻障层230′a、第二阻障层230′b、第一p型半导体层240′a、第二p型半导体层240′b、第一欧姆接触层270a、第二欧姆接触层270b、第一负电极250a、第二负电极250b、第一正电极280a及第二正电极280b所构成的结构。其中高功率半导体元件2000与高功率半导体元件1000的差别在于还包括一第三半导体层246a包含例如掺杂p型杂质构成一p型半导体层，形成于第一阻障层230′a上，且第三半导体层(p型半导体层)246a与第一p型半导体层240’a的第二边缘242邻接；一第四半导体层246b与第三半导体层246a相同为p型半导体层，形成于第二阻障层230′b上，且第四半导体层(p型半导体层)246b与第二p型半导体层240’b的第六边缘244邻接。此外，在本实施例中，第三p型半导体层246a与第一p型半导体层240’a具相同厚度，第四p型半导体层246b与第二p型半导体层240’b具相同厚度。在一实施例中，第三p型半导体层246a与第一p型半导体层240’a可于同一道制作工艺中形成，第四p型半导体层246b与第二p型半导体层240’b可于同一道制作工艺中形成。
在本实施例中，第一p型半导体层240′a及第三p型半导体层246a含p型杂质构成的正极化电荷，通道层220’含二维电子气227a构成的负极化电荷，第一阻障层230′a含正极化电荷与负极化电荷形成电耦合，此结构可视为一第一PIN二极管结构292a；类似的，第二p型半导体层240′b，第四p型半导体层246b，通道层220’，及第二阻障层230′b构成一第二PIN二极管结构292b。在一实施例中，位于基板200上的第一PIN二极管结构292a、第二PIN二极管结构292b，通过连接部282分别连接第一正电极280a及第二正电极280b，达到彼此并联，连接部282同时与沟槽260所露出的通道层220′形成萧特基接触，构成一萧特基接面的结构。
实施例三：
请参照图4，其绘示的是根据本发明实施例三的高功率半导体元件3000的剖面示意图。如图4所示，高功率半导体元件3000与实施例二的高功率元件2000相似，包括一位于基板200与缓冲层210上，由通道层220’、第一阻障层230′a、第二阻障层230’b、第一p型半导体层240’a、第二p型半导体层240’b、第一欧姆接触层270a、第二欧姆接触层270b、第一负电极250a、第二负电极250b、第一正电极280a及第二正电极280b所构成的结构。其中高功率半导体元件3000与高功率半导体元件2000的差别在于与第一p型半导体层240’a的第二边缘242邻接的是一厚度较第一p型半导体层240’a薄的第三p型半导体层246a’，第三p型半导体层246a’的厚度小于而与第二p型半导体层240’b的第六边缘244邻接的则是一厚度较第二p型半导体层240’b薄的第四p型半导体层246b’，第四p型半导体层246b’的厚度小于在一实施例中，第三p型半导体层246a’与第一p型半导体层240’a可于同一道外延制作工艺中形成一p型半导体层后，再经由蚀刻减薄，形成第三p型半导体层246a’；第四p型半导体层246b’与第二p型半导体层240’b可于同一道外延制作工艺中形成另一p型半导体层后，再经由蚀刻减薄形成第四p型半导体层246b’。第三p型半导体层246a’与第四p型半导体层246b’减薄至厚度范围为小于此厚度可减少顺偏时因半导体层包含例如掺杂p型杂质形成的电场对二维电子气浓度的影响，可避免顺向导通电压过高。
在本实施例中，第一p型半导体层240′a及第三p型半导体层246a’含p型杂质构成的正极化电荷，通道层220’含二维电子气227a构成的负极化电荷，第一阻障层230′a含正极化电荷与负极化电荷形成电耦合，此结构可视为一第一PIN二极管结构293a；类似的，第二p型半导体层240′b，第四p型半导体层246b’，通道层220’，及第二阻障层230′b构成一第二PIN二极管结构293b。在一实施例中，位于基板200上的第一PIN二极管结构293a、第二PIN二极管结构293b，通过连接部282分别连接第一正电极280a及第二正电极280b，达到彼此并联，连接部282同时与沟槽260所露出的通道层220′形成萧特基接触，构成一萧特基接面的结构。
实施例四：
图1B绘示的是根据本发明实施例四的高功率半导体元件4000的上视图。图5绘示的是图1B的高功率半导体元件4000沿B-B’方向的剖视图。
请参照图5，其绘示的是根据本发明实施例四的高功率半导体元件4000的剖面示意图。如图5所示，高功率半导体元件4000与实施例一的高功率元件1000相似，包括一位于基板200与缓冲层210上，由通道层220’、第一阻障层230′a、第二阻障层230′b、第一p型半导体层240’a、第二p型半导体层240’b、第一欧姆接触层270a、第二欧姆接触层270b、第一负电极250a、第二负电极250b、第一正电极280a及第二正电极280b所构成的结构。其中高功率半导体元件4000与高功率半导体元件1000的差别在于更包括一介电层275，形成于连接部282与侧墙260b、底墙260a、第一、第二p型半导体层240’a、240’b之间，形成一高击穿电压、低导通电压与低导通电阻特性的高功率半导体元件4000，例如加强型高电子迁移率晶体管(E-mode HEMT)。其中，第一负电极250a可充作此加强型高电子迁移率晶体管(E-mode HEMT)的源极，而第二负电极250b则可充作此加强型高电子迁移率晶体管的漏极。此外，此加强型高电子迁移率晶体管的一栅极结构，包含由第一正电极280a构成栅极结构的第一栅极部、由第二正电极280b构成栅极结构的第二栅极部，以及位于底墙260a的介电层275上的连接部282。在本实施例中，介电层275的材料可选自氮化硅、氧化硅及氮化氧硅等材料群组。
在顺向偏压操作下，栅源端电压(VGS)大于元件的起始电压(Vth)时，例如起始电压为0.8V，第一正电极280a、第二正电极280b以及连接部282下方的二维电子气浓度将会提高，顺向导通电流将从第一负电极250a充作的源极，经由二维电子气227a、227b，流至第二负电极250b充作的漏极。而逆向偏压操作下，由于第一、第二p型半导体层240’a、240’b的电场会降低第一正电极280a、第二正电极280b以及连接部282下方的二维电子气浓度，可有效阻绝通过连接部282形成的漏电路径，降低元件整体的栅极漏电流。在一实施例中，高功率半导体元件4000包含基板200、位于基板200上的缓冲层210、位于缓冲层210上的通道层220’、位于通道层220’上的第一半导体栅极结构294a、凹陷型金属绝缘半导体栅极(RecessMetal-Insulator-Semiconductor(MIS)Gate)结构301、以及第二半导体栅极结构294b，且该些栅极结构彼此并联。其中，第一半导体栅极结构294a包含第一阻障层230’a、第一半导体层240’a具有一导电型例如p型、第一欧姆接触层270a，以及第一正电极280a；第二半导体栅极结构294b可包含第二阻障层230’b、第二半导体层240’b具有一导电型例如p型、第二欧姆接触层270b，以及第二正电极280b；凹陷型金属绝缘半导体栅极结构301包含介电层275、位于介电层275上的连接部282、以及介电层275与通道层220’的接面；其中连接部282与第一正电极280a以及第二正电极280b形成电连接；且第一半导体栅极结构294a、凹陷型金属绝缘半导体栅极结构301、以及第二半导体栅极结构294b通过连接部282、第一正电极280a以及第二正电极280b形成电连接。第一半导体栅极结构294a、第二半导体栅极结构294b，以及凹陷型金属绝缘半导体栅极结构301的材料与连接方式可视元件的操作特性作适当调整。
实施例五：
请参照图6，其绘示的是根据本发明实施例五的高功率半导体元件5000的剖面示意图。如图6所示，高功率半导体元件5000与实施例二的高功率元件2000相似，包括位于基板200与缓冲层210上，由通道层220’、第一阻障层230′a、第二阻障层230’b、第一p型半导体层240’a、第二p型半导体层240’b、第三p型半导体层246a、第四p型半导体层246b、第一欧姆接触层270a、第二欧姆接触层270b、第一负电极250a、第二负电极250b、第一正电极280a及第二正电极280b所构成的结构。其中高功率半导体元件5000与高功率半导体元件2000的差别在于还包括一介电层275，形成于连接部282与侧墙260b、底墙260a、第一、第二p型半导体层240′a、240′b之间，形成高击穿电压、低导通电压与低导通电阻特性的高功率半导体元件5000，例如加强型高电子迁移率晶体管(E-mode HEMT)。其中，第一负电极250a可充作此加强型高电子迁移率晶体管(E-mode HEMT)的源极，而第二负电极250b则可充作此加强型高电子迁移率晶体管的漏极。此外，此加强型高电子迁移率晶体管的栅极结构，包含由第一正电极280a构成栅极结构的第一栅极部、由第二正电极280b构成栅极结构的第二栅极部，以及位于底墙260a的介电层275上的连接部282。在本实施例中，介电层275的材料可选自氮化硅、氧化硅及氮化氧硅等材料群组。在一实施例中，高功率半导体元件5000包含基板200、位于基板200上的缓冲层210、位于缓冲层210上的通道层220’、位于通道层220’上的第一半导体栅极结构295a、凹陷型金属绝缘半导体栅极结构301、以及第二半导体栅极结构295b，且该些栅极结构彼此并联。其中，第一半导体栅极结构295a包含第一阻障层230’a、第一半导体层240’a具有一导电型例如p型、第三半导体层246a具有一导电型例如p型、第一欧姆接触层270a，以及第一正电极280a；第二半导体栅极结构295b包含第二阻障层230’b、第二半导体层240’b具有一导电型例如p型、第四半导体层246b具有一导电型例如p型、第二欧姆接触层270b，以及第二正电极280b；凹陷型金属绝缘半导体栅极结构301包含介电层275、位于介电层275上的连接部282、以及介电层275与通道层220’的接面，其中连接部282与第一正电极280a以及第二正电极280b电连接；且第一半导体栅极结构295a、凹陷型金属绝缘半导体栅极结构301、以及第二半导体栅极结构295b通过连接部282、第一正电极280a以及第二正电极280b形成电连接。第一半导体栅极结构295a、第二半导体栅极结构295b，以及凹陷型金属绝缘半导体栅极结构301的材料与连接方式可视元件的操作特性作适当调整。
实施例六：
请参照图7，其绘示的是根据本发明实施例六的高功率半导体元件6000的剖面示意图。如图7所示，高功率半导体元件6000与实施例三的高功率元件3000相似，包括位于基板200与缓冲层210上，由通道层220’、第一阻障层230’a、第二阻障层230’b、第一半导体层240’a具有一导电型例如p型、第二半导体层240’b具有一导电型例如p型、第三半导体层246a’具有一导电型例如p型、第四半导体层246b’具有一导电型例如p型、第一欧姆接触层270a、第二欧姆接触层270b、第一负电极250a、第二负电极250b、第一正电极280a及第二正电极280b所构成的结构。其中高功率半导体元件6000与高功率半导体元件3000的差别在于还包括一介电层275，形成于连接部282与侧墙260b、底墙260a、第一、第二p型半导体层240’a、240’b之间，形成高击穿电压、低导通电压与低导通电阻特性的高功率半导体元件6000，例如加强型高电子迁移率晶体管。其中，第一负电极250a可充作此加强型高电子迁移率晶体管的源极，而第二负电极250b则可充作此加强型高电子迁移率晶体管的漏极。此外，此加强型高电子迁移率晶体管的栅极结构，包含由第一正电极280a构成栅极结构的第一栅极部、由第二正电极280b构成栅极结构的第二栅极部，以及位于底墙260a的介电层275上的连接部282。在本实施例中，介电层275的材料可选自氮化硅、氧化硅及氮化氧硅等材料群组。在一实施例中，高功率半导体元件6000包含基板200、位于基板200上的缓冲层210、位于缓冲层210上的通道层220’、位于通道层220’上的第一半导体栅极结构296a、凹陷型金属绝缘半导体栅极结构301、以及第二半导体栅极结构296b，且该些栅极结构彼此并联。其中，第一半导体栅极结构296a包含第一阻障层230’a、第一半导体层240’a具有一导电型例如p型、第三半导体层246a’具有一导电型例如p型、第一欧姆接触层270a，以及第一正电极280a；第二半导体栅极结构296b包含第二阻障层230’b、第二半导体层240’b具有一导电型例如p型、第四半导体层246b’具有一导电型例如p型、第二欧姆接触层270b，以及第二正电极280b；凹陷型金属绝缘半导体栅极结构301包含介电层275、位于介电层275上的连接部282、以及介电层275与通道层220’的接面，其中连接部282与第一正电极280a以及第二正电极280b电连接，且第一半导体栅极结构296a、凹陷型金属绝缘半导体栅极结构301、以及第二半导体栅极结构296b通过连接部282、第一正电极280a以及第二正电极280b形成电连接。第一半导体栅极结构296a、第二半导体栅极结构296b，以及凹陷型金属绝缘半导体栅极结构301的材料或连接方式可视元件的操作特性作适当调整。
虽然结合以上优选实施例公开了本发明，然而其并非用以限定本发明，任何所属技术领域中具有通常知识者，在不脱离本发明的精神和范围内，可更动与组合上述各种实施例。

Claims (10)

1.一种高功率半导体元件，包括：
基板；
通道层，形成于该基板上，包含第一区，第二区及第三区；
第一阻障层，形成于该通道层的该第一区上；
第一半导体层，具有第一导电性，形成于该第一阻障层上；
第一电极，形成于该第一阻障层上；
第二电极，形成于该第一半导体层上；
第二阻障层，形成于该通道层的该第二区上；
第二半导体层，具有该第一导电性，形成于该第二阻障层上；
第三电极，形成于该第二阻障层上；
第四电极，形成于该第二半导体层上；
沟槽，位于该第一阻障层及该第二阻障层之间；其中该沟槽曝露出该通道层的该第三区，其中该沟槽具有底墙，该底墙包含该通道层的该第三区；以及
连接部，覆盖该沟槽内的该底墙，电连接该第二电极与该第四电极，且该连接部与该通道层的该第三区形成萧特基接触。
2.如权利要求1所述的高功率半导体元件，还包括：
第一欧姆接触层，形成于该第一半导体层上；以及
第二欧姆接触层，形成于该第二半导体层上，其中，该第二电极形成于第一欧姆接触层上，该第四电极形成于第二欧姆接触层上。
3.如权利要求1所述的高功率半导体元件，其中该第一电极以及该第三电极的另一部分分别形成于该通道层上。
4.如权利要求2所述的高功率半导体元件，其中该第一半导体层具有一远离该沟槽的第一边缘，该第一欧姆接触层具有一远离该沟槽的第二边缘，该第二半导体层具有一远离该沟槽的第三边缘，该第二欧姆接触层具有一远离该沟槽的第四边缘，其中该第一边缘与该第二边缘对齐，及/或该第三边缘与该第四边缘对齐。
5.如权利要求4所述的高功率半导体元件，还包括一第三半导体层具有该第一导电性，邻接于该第一半导体层的该第一边缘，以及一第四半导体层具有该第一导电性，邻接于该第二半导体层的该第三边缘。
6.如权利要求5所述的高功率半导体元件，其中该第三半导体层的厚度等于或小于该第一半导体层，该第四半导体层的厚度等于或小于该第二半导体层，或者/以及该第三半导体层及该第四半导体层的厚度小于
7.如权利要求1至6中任一所述的高功率半导体元件，还包括缓冲层，形成于该基板和该通道层之间，以及介电层，形成于该连接部与该底墙、该第一、第二半导体层之间。
8.一种高功率半导体元件，包括：
基板；
第一PIN二极管结构，位于该基板上；
第二PIN二极管结构，位于该基板上；以及
具有萧特基接面的结构，位于该基板上，其中该第一PIN二极管结构、该第二PIN二极管结构，以及该具有萧特基接面的结构彼此并联。
9.一种高功率半导体元件，包括：
基板；
通道层，位于基板上；
第一半导体栅极，位于该通道层上；
凹陷型栅极，位于该通道层上；以及
第二半导体栅极，位于该通道层上；其中该第一半导体栅极、该凹陷型栅极、以及该第二半导体栅极彼此并联。
10.如权利要求9所述的高功率半导体元件，其中该第一半导体栅极具有第一电极、该凹陷型栅极具有连接部、该第二半导体栅极具有第二电极，该连接部与该第一电极以及该第二电极电连接。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112885896A (zh) * 2021-01-29 2021-06-01 电子科技大学 一种hemt器件
CN113257896A (zh) * 2021-05-11 2021-08-13 华南师范大学 多场板射频hemt器件及其制备方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103109369B (zh) * 2010-06-24 2016-04-06 富士通株式会社 半导体装置
JP6616379B2 (ja) * 2017-10-30 2019-12-04 京セラ株式会社 電子機器
US10854646B2 (en) 2018-10-19 2020-12-01 Attollo Engineering, LLC PIN photodetector
US11158759B1 (en) * 2020-04-16 2021-10-26 International Business Machines Corporation Chip carrier integrating power harvesting and regulation diodes and fabrication thereof
US11545485B2 (en) * 2021-03-09 2023-01-03 Infineon Technologies Austria Ag Type III-V semiconductor substrate with monolithically integrated capacitor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057720A1 (en) * 2007-08-29 2009-03-05 Sanken Electric Co., Ltd. Field-Effect Semiconductor Device, and Method of Fabrication
CN102308390A (zh) * 2008-12-10 2012-01-04 特兰斯夫公司 半导体异质结构二极管
US20130082400A1 (en) * 2011-09-29 2013-04-04 Fujitsu Limited Compound semiconductor device and method of manufacturing the same
CN103035700A (zh) * 2011-09-29 2013-04-10 富士通株式会社 化合物半导体器件及其制造方法
US20140231873A1 (en) * 2009-09-03 2014-08-21 Panasonic Corporation Nitride semiconductor device
US20160204241A1 (en) * 2013-05-24 2016-07-14 Fujitsu Limited Semiconductor device and manufacturing method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7202528B2 (en) * 2004-12-01 2007-04-10 Semisouth Laboratories, Inc. Normally-off integrated JFET power switches in wide bandgap semiconductors and methods of making
US8154073B2 (en) * 2006-07-14 2012-04-10 Denso Corporation Semiconductor device
KR101821642B1 (ko) 2010-06-24 2018-01-24 더 유니버시티 오브 셰필드 반도체 소자

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057720A1 (en) * 2007-08-29 2009-03-05 Sanken Electric Co., Ltd. Field-Effect Semiconductor Device, and Method of Fabrication
CN102308390A (zh) * 2008-12-10 2012-01-04 特兰斯夫公司 半导体异质结构二极管
US20140231873A1 (en) * 2009-09-03 2014-08-21 Panasonic Corporation Nitride semiconductor device
US20130082400A1 (en) * 2011-09-29 2013-04-04 Fujitsu Limited Compound semiconductor device and method of manufacturing the same
CN103035700A (zh) * 2011-09-29 2013-04-10 富士通株式会社 化合物半导体器件及其制造方法
US20160204241A1 (en) * 2013-05-24 2016-07-14 Fujitsu Limited Semiconductor device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112885896A (zh) * 2021-01-29 2021-06-01 电子科技大学 一种hemt器件
CN113257896A (zh) * 2021-05-11 2021-08-13 华南师范大学 多场板射频hemt器件及其制备方法

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