CN107680948B - 半导体装置、显示面板总成、半导体结构 - Google Patents
半导体装置、显示面板总成、半导体结构 Download PDFInfo
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Abstract
本发明公开一种半导体装置、显示面板总成、半导体结构。其中半导体装置包括芯片、多个第一凸块以及多个第二凸块。芯片包括有源表面。第一凸块沿着第一方向被配置在有源表面上。第二凸块沿着平行于第一方向的第二方向配置在有源表面上,其中第二凸块的其中之一配置在第一凸块中相邻的两个之间。从第二凸块至扇出区域的最短距离小于从第一凸块至扇出区域的最短距离,且第一凸块的其中之一的第一宽度大于第二凸块的其中之一的第二宽度。
Description
技术领域
本发明涉及一种半导体装置、一种显示面板总成及一种半导体结构,且特别是涉及一种半导体装置、使用其半导体装置的一种显示面板总成及一种半导体结构。
背景技术
不断进步的晶片制造科技已经引领集成电路(Integrated circuit,IC)产业的快速发展。集成电路被制造得重量更轻、尺寸更小以及在功能上更复杂及多元,并具有更高针脚数和更高的频率。薄膜倒装(Chip-on-film,COF)封装满足配合发展趋势制造的集成电路的封装要求。薄膜倒装具有细间距(fine pitch)和良好的可挠性,因而在尺寸稳定度、线路的高密度、耐燃性以及环境保护上皆有良好的表现。
一般来说,薄膜倒装封装是将焊接/封装集成电路于可挠电路薄膜上。多个金属凸块焊接在集成电路的焊垫上。然而,当在芯片上的金属凸块的配置也遵循细间距的趋势时,金属凸块之间的距离缩短可能导致在回焊制作工艺时发生金属凸块的溢流,因而可能造成短路。再者,在细间距封装的应用上,特别是高分辨率(极细间距)封装,对位不准或对位偏移经常发生,其严重地降低金属凸块的接合能力。此外,芯片的厚度很难进一步减少。因此,业界致力于找寻是否可以提供更多解决方案来增加细间距封装的良率以及减少芯片的厚度。
发明内容
本发明的目的在于提供一种半导体装置,其可增进半导体装置的良率。
本发明的再一目的在于提供一种显示面板总成,其可增进使用上述半导体装置的显示面板总成的良率。
本发明的另一目的在于提供一种半导体结构,其可减少芯片的厚度。
为达上述目的,本发明提供一种半导体装置,包括芯片、多个第一凸块以及多个第二凸块。芯片包括有源表面。这些第一凸块沿着第一方向配置在有源表面上。第二凸块沿着平行于第一方向的第二方向配置在有源表面上,这些第二凸块的其中之一位于这些第一凸块的相邻两个之间,且第一凸块的其中之一的第一宽度大于第二凸块的其中之一的第二宽度
本发明提供一种显示面板总成,包括显示面板、可挠电路薄膜(flexible circuitfilm)、芯片、多个第一凸块及多个第二凸块。显示面板包括位于显示面板的显示区域内的像素阵列、配置在显示面板的接合区域上的多个焊垫以及电连接像素阵列及焊垫的多条连接线。可挠电路薄膜包括连接于接合区域的扇出区域、芯片区域和多个线路,其中这些线路从芯片区域往扇出区域延伸且电连接于这些连接线。芯片配置在芯片区域上并电连接这些线路,且芯片包括有源表面。这些第一凸块沿着第一方向配置在有源表面上。这些第二凸块沿着平行于第一方向的第二方向配置在有源表面上,其中自这些第二凸块至扇出区域的最小距离小于自这些第一凸块至扇出区域的最小距离。连接于这些第一凸块的各条线路通过这些第二凸块中相邻的两个之间,以往扇出区域延伸,且这些第二凸块的其中之一的宽度小于这些第一凸块的其中之一的宽度。
本发明更提供一种半导体结构,包括玻璃基板、承载器(carrier)及芯片。玻璃基板包括接合区域。芯片包括彼此相反的有源表面及背面(back surface),其中芯片以有源表面配置在接合区域上。承载器配置在芯片的背面上。
在本发明的一实施例中,上述的芯片配置在可挠电路薄膜上。
在本发明的一实施例中,上述可挠电路薄膜包括扇出区域、芯片区域以及多个线路,所述线路自芯片区域至扇出区域延伸,芯片配置在芯片区域,且这些第一凸块及这些第二凸块电连接于这些线路。
在本发明的一实施例中,上述线路的第一部分分别连接这些第一凸块,这些线路的第一部分的其中之一通过这些第二凸块中相邻的两个之间,以延伸至扇出区域。
在本发明的一实施例中,上述承载器配置在芯片的背面上,并且背面相对于有源表面。
在本发明的一实施例中,上述芯片的厚度等于或小于100微米(μm)。
在本发明的一实施例中,上述半导体装置还包括多个第三凸块,这些第三凸块沿着平行于第一方向的第三方向配置在有源表面上,其中这些第三凸块的其中之一位于这些第二凸块中相邻的两个之间。自这些第三凸块至扇出区域的最小距离小于自这些第二凸块至扇出区域的最小距离,并且这些第一凸块的其中之一的第一宽度大于这些第三凸块的其中之一的第三宽度。
在本发明的一实施例中,上述这些第二凸块的其中之一的第二宽度等于或大于这些第三凸块的其中之一的第三宽度。
在本发明的一实施例中,上述半导体装置还包括可挠层,配置在芯片相对于有源表面的背面上。
在本发明的一实施例中,上述可挠电路薄膜还包括至少一切除开口(cut-outopening),且扇出区域及切除开口分别位于芯片区域的相对两侧。
在本发明的一实施例中,上述可挠电路薄膜还包括电磁干扰屏蔽层(EMIshielding layer)及/或散热层(heat-dissipation layer)。
在本发明的一实施例中,上述这些连接线被分割成多个群组,显示面板还包括多个多工器(multiplexers,MUX),并且各个多工器选择性地将这些群组的其中之一的连接线的其中之一连接至这些焊垫的其中之一。
在本发明的一实施例中,上述的群组的连接线的数量为2、3、4、6、8或9。
在本发明的一实施例中,任两相邻的这些连接线分别属于这些多工器的这些群组中的两个不同的群组。
在本发明的一实施例中,上述承载器包括多个导通孔,以电连接芯片和接合区域。
在本发明的一实施例中,上述半导体结构的厚度等于或小于0.2mm。
基于上述,在本发明中,第一凸块和第二凸块配置在芯片的有源表面上,其中自第二凸块至可挠电路薄膜的扇出区域的最小距离小于自第一凸块至扇出区域的最小距离。如此,连接这些第一凸块的各条线路通过这些第二凸块中相邻的两个之间,并延伸至扇出区域。因此,这些第一凸块的其中之一的宽度大于这些第二凸块的其中之一的宽度,所以通过任两相邻的第二凸块的线路能够与此相邻两第二凸块保持适当的距离,避免对位不准或焊料溢流。因此,本发明能够增进半导体装置和使用其的显示面板总成的良率。
此外,本发明的一实施例将一承载器配置在芯片的背面上。如此,有了承载器的支撑,芯片能够研磨得更薄,且不易因外在撞击而碎裂或破裂。因此,本发明能够更加降低芯片的厚度和使用其的显示面板总成或半导体结构的整体厚度。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1是本发明一实施例的一种显示面板总成示意图;
图2是图1的显示面板总成中第一凸块、第二凸块及线路的配置的局部放大示意图;
图3是本发明一实施例的一种显示面板总成中第一凸块、第二凸块及线路的配置的局部放大示意图;
图4是图1的显示面板总成的局部剖面示意图;
图5是本发明一实施例的一种半导体结构的局部剖面示意图。
符号说明
10:显示面板总成
10a:半导体结构
100:半导体装置
110:芯片
112:有源表面
114:背面
116:底胶
120:第一凸块
120a:玻璃基板
130:第二凸块
140:第三凸块
150:承载器
160:可挠层
170:玻璃盖板
180:可挠印刷电路板
190:电磁干扰屏蔽层/散热层
200:可挠电路薄膜
210:线路
300:显示面板
310:像素阵列
320:焊垫
330:连接线
340:多工器
A1:扇出区域
A2:芯片区域
A3:接合区域
D1:第一方向
D2:第二方向
D3:第三方向
OP:切除开口
W1:第一宽度
W2:第二宽度
W3:第三宽度
具体实施方式
图1是根据本发明一实施例的一种显示面板总成示意图。图2绘示了图1的显示面板总成中第一凸块、第二凸块及线路的配置的局部放大示意图。图4绘示了图1的显示面板总成的局部剖面示意图。应该注意到的是,为了更好地描述凸块120、130、线路210及焊垫320之间的连接关系,芯片110、可挠电路薄膜200及显示面板300是以透视的形式绘示于图1中。请先参照图1、图2及图4,本发明的一实施例的一种半导体装置100可以是如图1所示的用于显示面板总成100的驱动集成电路(driver IC),但本发明不以此为限。半导体装置100包括芯片110、多个第一凸块120和多个第二凸块130。芯片110如图4所示的包括有源表面112。第一凸块120沿着第一方向D1配置在有源表面112上。第二凸块130沿着平行于第一方向D1的第二方向D2配置在有源表面112上,并且第二凸块130的其中之一位于相邻的两个第一凸块130之间。第一凸块120的其中之一的第一宽度W1大于第二凸块130的其中之一的第二宽度W2。
在本实施例中,半导体装置100可应用于如图1所示的显示面板总成10,并且,显示面板总成10包括半导体装置100、可挠电路薄膜200及显示面板300。可挠电路薄膜200包括扇出区域A1、芯片区域A2及多个线路210。线路210自芯片区域A2往扇出区域A1延伸。芯片110配置在可挠电路薄膜200的芯片区域A2上,并通过第一凸块120和第二凸块130电连接于线路210。也就是说,半导体装置100能够被应用于薄膜倒装(chip-on-film)封装上。在本实施例中,底胶(underfill)116可填充于芯片110和可挠电路薄膜200之间的间隙,以更加强化芯片110的接合力,但本发明不以此为限。
此外,显示面板300包括像素阵列310、多个焊垫320和多条连接线330。像素阵列310位于在显示面板300的显示区域内。焊垫320配置在显示面板300的接合区域A3上,并且连接线320电连接像素阵列310及焊垫320。如此,可挠电路薄膜200的扇出区域A1可连接至显示面板300的接合区域A3。在本实施例中,可挠电路薄膜200的扇出区域A1可与显示面板300的接合区域A3至少部分重叠(overlapped),因此线路210电连接至连接线330。线路210由芯片区域A2往扇出区域A1延伸,且与连接线330电连接,因此半导体装置可电连接至显示面板300。
详细而言,从第二凸块130至扇出区域A1的最小距离小于从第一凸块120至扇出区域A1的最小距离。也就是说,第二凸块130比第一凸块120更接近扇出区域A1,并且连接第一凸块120的各条线路210通过第二凸块130中相邻的两个之间,以使线路210延伸至扇出区域A1。换而言之,线路210的第一部分可分别连接第一凸块120,且线路210的第一部分的其中之一通过第二凸块130中相邻的两个之间,以使线路210延伸至扇出区域A1。如此,第二凸块130的其中之一的第二宽度W2小于第一凸块120的其中之一的第一宽度W1,因此,通过任两相邻的第二凸块130之间的线路210能够与此相邻两第二凸块130之间保持适当的距离,避免对位不准或焊料溢流的问题,以增进半导体装置100和使用此半导体装置100的显示面板总成10的良率。
更进一步而言,半导体装置100还可包括如图4所示的可挠层160。可挠层160可配置在与有源表面112相对侧的芯片110的背面上。在本实施例中,可挠层160可例如为散热膏或可挠胶,以防止芯片110被刮伤或受损。此外,可挠电路薄膜220还可包括如图1所示的至少一切除开口OP。扇出区域A1和切除开口OP分别位于芯片区域A2的相对两侧。可挠电路薄膜200还可包括电磁干扰屏蔽层及/或散热层190,所述电磁干扰屏蔽层及/或散热层190配置于芯片110所在的顶面或相对于芯片110所在的顶面的底面。
在本实施例中,连接线330可被分成多个群组,并且显示面板300还包括多个多工器340。多工器340用以选择几个模拟或数字输入信号的其中一个,并传送所选的输入信号至单一线路。因此,各个多工器340选择性地将其中一个群组中的其中一条连接线330连接至其中一个对应的焊垫320。如此配置,单一个焊垫320能对应多条连接线330,因而能减少焊垫320的数量,更可减少线路210及凸块120、130的数量。在本实施例中,各个多工器340可为2对1多功器(2-MUX)、3对1多功器(3-MUX)、4对1多功器(4-MUX)、6对1多功器(6-MUX)、8对1多功器(8-MUX)或9对1多功器(9-MUX)等等。也就是说,各个群组的连接线330的数量是2、3、4、6、8或9等等,这代表每一个群组可包括2、3、4、6、8或9条的连接线,但连接线330的数量并不以此为限。任两相邻的连接线330分别属于上述群组中的两个不同的群组,这代表任两相邻的连接线330分别连接至上述的多工器中的两个不同的多工器。
在本实施例中,承载器150配置于芯片110的背面上,其中背面相对于有源表面112。在承载器150的支撑下,芯片110能够被研磨得更薄,且不致因外在撞击而开裂或破碎。在本实施例中,芯片110的厚度可等于或小于100微米(μm),但本发明不以此为限。
图3是根据本发明一实施例所绘示的显示面板总成中第一凸块、第二凸块及线路的配置的局部放大示意图。在此必须说明的是,图3的实施例包含很多特征相同或相似于先前在图1及图2中所揭露的显示面板总成10。因此,本实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且,为了清楚及简洁,省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,本实施例不再重复赘述。以下将针对图3的实施例与图2的实施例的差异做说明。
本实施例绘示了三列的凸块120、130、140,但本发明并不限制凸块的列数。详细而言,本实施例的半导体装置还包括多个第三凸块140,其沿着平行于第一方向D1的第三方向D3配置在芯片的有源表面上(如图4所示的芯片110的有源表面112),并且第三凸块140的其中之一位于第二凸块中相邻的两个之间。从第三凸块140至扇出区域A1(如图1所示的扇出区域A1)的最小距离小于从第二凸块130至扇出区域A1的最小距离。也就是说,第三凸块140比第二凸块120更接近可挠电路薄膜的扇出区域。如此,连接第一凸块120和第二凸块130的线路210通过第三凸块130中相邻的两个之间,以使线路210可延伸至扇出区域A1。据此,第一凸块120的其中之一的第一宽度W1大于第三凸块140的其中之一的第三宽度W3,并且第二凸块130的其中之一的第二宽度W2大于或等于第三凸块140的其中之一的第三宽度W3。也就是说,第三宽度W3至少小于第一宽度W1,以使通过任两相邻的第三凸块140的线路210可与此两相邻的第三凸块140保持适当的距离,避免对位不准或焊料溢流的问题,以增进半导体装置和使用其的显示面板总成。
图5是根据本发明一实施例所绘示的一种半导体结构的局部剖面示意图。应该注意到的是,在此必须说明的是,图5的实施例包含很多特征相同或相似于先前揭露的图4的实施例。因此,本实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且,为了清楚及简洁,省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,本实施例不再重复赘述。以下将针对图5的实施例与图4的实施例的差异做说明。
在本实施例中,半导体结构10a包括玻璃基板120a、承载器150以及芯片110。半导体结构10a可为玻璃倒装(Chip-on-glass,COG)封装。玻璃基板120a包括接合区域。芯片110包括如图5所示的彼此相对的有源表面112和背面114,其中,芯片110是以其有源表面112配置于玻璃基板120a的接合区域上并电连接于接合区域。在本实施例中,芯片110是经由异方性导电薄膜(Anisotropic conductive film,ACF)118而接合于玻璃基板120a的接合区域上,但本发明不以此为限。承载器150配置在芯片110的背面114上。据此,通过承载器150的支撑,芯片110能够被研磨得更薄,且不易因外在冲击而龟裂或破碎,更可降低芯片110的厚度以及半导体结构10a的整体厚度。在本实施例中,芯片110的厚度可等于或小于100微米(μm),并且半导体结构10a的整体厚度可等于或小于0.2毫米(mm)。半导体结构10a可应用于显示面板总成,因此玻璃基板120a可为显示面板的基板,且玻璃盖板(cover glass)170可覆盖玻璃基板120a并暴露芯片110。再者,可挠印刷电路板(flexible printed circuitboard)180可连接至玻璃基板120a,以电连接显示面板和主机板。
综上所述,在本发明的半导体装置及使用其的显示面板总成中,第一凸块和第二凸块配置于芯片的有源表面上。从第二凸块至可挠电路薄膜的扇出区域的最小距离小于从第一凸块至扇出区域的最小距离。如此,连接第一凸块的各条线路通过第二凸块中相邻的两个之间,以延伸至扇出区域。因此,第一凸块的其中之一的宽度大于第二凸块的其中之一的宽度,故通过任两相邻的第二凸块的线路可与此两相邻的第二凸块保持适当距离,避免对位不准或焊料溢流。因此,本发明能够增进半导体装置及使用其的显示面板总成的良率。
更进一步而言,本发明将承载器配置在薄膜倒装或玻璃倒装中的芯片的背面。如此,通过承载器的支撑,芯片能够被研磨的更薄,且不易因外在冲击而龟裂或破碎。因此,本发明更可降低芯片的厚度以及显示面板总成或半导体结构的整体厚度。
虽然结合以上实施例揭露了本发明,然而其并非用以限定本发明,任何所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应以附上的权利要求所界定的为准。
Claims (12)
1.一种半导体装置,包括:
芯片,包括有源表面,其中所述芯片配置在可挠电路薄膜上,所述可挠电路薄膜包括扇出区域、芯片区域及至少一切除开口,所述芯片配置在所述芯片区域上,且所述扇出区域及所述切除开口分别位于所述芯片区域的相对两侧;
承载器,配置在所述芯片的背面上,并且所述背面相对于所述有源表面;
多个第一凸块,沿着第一方向配置在所述有源表面上;以及
多个第二凸块,沿着平行于所述第一方向的第二方向配置在所述有源表面上,其中所述多个第二凸块的其中之一位于所述多个第一凸块中的相邻两个之间,并且所述多个第一凸块的其中之一的第一宽度大于所述多个第二凸块的其中之一的第二宽度。
2.如权利要求1所述的半导体装置,其中所述可挠电路薄膜还包括多条线路,其中所述多条线路从所述芯片区域往所述扇出区域延伸,并且所述多个第一凸块及所述多个第二凸块电连接至所述多条线路。
3.如权利要求2所述的半导体装置,其中从所述多个第二凸块至所述扇出区域的最短距离小于从所述多个第一凸块至所述扇出区域的最短距离。
4.如权利要求2所述的半导体装置,其中所述多条线路的第一部分分别连接所述多个第一凸块,所述多条线路的所述第一部分的其中之一通过所述多个第二凸块中的相邻两个之间,以延伸至所述扇出区域。
5.如权利要求1所述的半导体装置,其中所述芯片的厚度等于或小于100微米。
6.如权利要求1所述的半导体装置,还包括多个第三凸块,沿着平行于所述第一方向的第三方向配置于所述有源表面上,其中所述多个第三凸块的其中之一位于所述多个第二凸块中的相邻两个之间,并且所述多个第一凸块的其中之一的所述第一宽度大于所述多个第三凸块的其中之一的第三宽度。
7.如权利要求6所述的半导体装置,其中所述多个第二凸块的其中之一的所述第二宽度大于或等于所述多个第三凸块的其中的一个的第三宽度。
8.如权利要求1所述的半导体装置,还包括可挠层,配置在所述芯片相对于所述有源表面的背面。
9.如权利要求1所述的半导体装置,其中所述可挠电路薄膜还包括电磁干扰屏蔽层及/或散热层。
10.一种显示面板总成,包括:
显示面板,包括位于所述显示面板的显示区域内的像素阵列、配置在所述显示面板的接合区域上的多个焊垫、多个多工器以及电连接所述像素阵列及所述多个焊垫的多条连接线,其中所述多条连接线被区分成多个群组,且各所述多工器经配置以选择性地将所述多个群组的其中之一中的连接线的其中之一连接至所述多个焊垫的其中之一;
可挠电路薄膜,包括连接于所述接合区域的扇出区域、芯片区域及多条线路,其中所述多条线路从所述芯片区域往所述扇出区域延伸且电连接所述多条连接线;
芯片,配置在所述芯片区域上以电连接于所述多条线路,并且所述芯片包括有源表面;
承载器,配置在所述芯片的背面上,并且所述背面相对于所述有源表面;
多个第一凸块,沿着第一方向配置在所述有源表面上;以及
多个第二凸块,沿着平行于所述第一方向的第二方向配置在所述有源表面上,其中从所述多个第二凸块至所述扇出区域的最短距离小于从所述多个第一凸块至所述扇出区域的最短距离,连接所述多个第一凸块的各所述线路通过所述多个第二凸块中相邻的两个之间,以延伸至所述扇出区域,且所述多个第二凸块的其中之一的第二宽度小于所述多个第一凸块的其中之一的第一宽度。
11.如权利要求10所述的显示面板总成,其中各所述群组的连接线的数量为2、3、4、6、8或9。
12.如权利要求10所述的显示面板总成,其中任两相邻的连接线分别属于所述多个群组中的两个不同的群组。
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TW202042359A (zh) * | 2019-05-02 | 2020-11-16 | 南茂科技股份有限公司 | 薄膜覆晶封裝結構 |
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