CN107634760A - Adaptive digital reset device for phase-locked loop - Google Patents
Adaptive digital reset device for phase-locked loop Download PDFInfo
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- CN107634760A CN107634760A CN201710898384.7A CN201710898384A CN107634760A CN 107634760 A CN107634760 A CN 107634760A CN 201710898384 A CN201710898384 A CN 201710898384A CN 107634760 A CN107634760 A CN 107634760A
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Abstract
the invention discloses a self-adaptive digital reset device for a phase-locked loop, which comprises a system reset detection logic circuit, a power-on delay logic circuit and a P LL reset generation logic circuit, wherein the system reset detection logic circuit is used for detecting whether system reset is effective and reaches an expected width through a plurality of registers, and if the system reset is effective and reaches the expected width, an effective reset pulse is generated to the monostable circuit, the monostable circuit is used for outputting the effective pulse to the power-on delay logic circuit in a stable state through the plurality of registers after receiving the effective pulse output by the monostable circuit, counting is carried out after receiving the effective pulse output by the monostable circuit, the effective pulse is kept unchanged until a preset threshold value is reached, and a trigger pulse is output to the P LL reset generation logic circuit, and the P LL reset generation logic circuit is used for generating the reset pulse with a required width after receiving the trigger pulse output by the power-on delay logic circuit.
Description
Technical field
The present invention relates to phaselocked loop (Phase Locked Loop, PLL) technical field, more particularly to one kind to be used to lock phase
The adaptive digital resetting means of ring.
Background technology
Phase-locked loop pll is that it is large scale integrated circuit particularly microprocessor for producing stable high frequency clock output
The heart of device.With the progress of integrated circuit technology and the raising of processor target dominant frequency, PLL design realization is more and more finer
Change, reliable and stable and rational reseting logic is into the essential part of phaselocked loop.The reset signal of phaselocked loop is led to
Often need to produce a positive pulse with one fixed width after system electrification is stable, the pulse at present is generally real by analog circuit
It is existing, 0 state is in before system electrification completion, the 1 of a fixed width is formed after upper electricity is stable, then returns nought state.
Phaselocked loop uses the reset mode that above-mentioned analog circuit is realized, there are the following problems for meeting：
1) because analog circuit is typically related to technique, and once design success rate is far below digital circuit, because
And once need to carry out technogenic migration, then the circuit needs to redesign completely, and risk is higher；
2) analog circuit is typically a monostable circuit, i.e., can only after the power-up produce and once reset, if system
Occur phaselocked loop losing lock in the course of work, above-mentioned logic can only be triggered by way of system cut-off then re-powers.For solution
The certainly problem, by the way of having systematic reset signal of practitioner's proposition using processor as PLL reset signal, but such
Mode, which resets, to be exited the locking delayed of rear PLL and explicitly will be presented in face of user program, makes user program clock at work
One is had from slowly to fast change so that the complex designing of user program particularly real-time program, while such mode is every
Subsystem, which resets, can all trigger PLL resets, cause irrational reset to produce；And if side using user program programming Control
Formula, although whole PLL reseting procedures displayization can be made, but still the difficulty of user procedure development can be dramatically increased.
The content of the invention
The technical problem to be solved in the present invention is that：For technical problem existing for prior art, the present invention provides one
The reset of phaselocked loop kind is realized based on Digital Logic, and structural principle is simple, can realize it is adaptive reset and reset efficiency and
The high adaptive digital resetting means for phaselocked loop of reliability.
In order to solve the above technical problems, technical scheme proposed by the present invention is：
A kind of adaptive digital resetting means for phaselocked loop, including：
System reset detects logic circuit, for whether keeping effective by the reset of multiple register detecting systems and reaching
Desired width, active homing pulse is if it is produced to monostable circuit；
Monostable circuit, after receiving the active homing pulse, a stable state is in by multiple registers,
Power on delay logic circuit is given in the effective impulse for exporting corresponding stable state；
Power on delay logic circuit, for being counted after receiving the effective impulse of the monostable circuit output, until
Keep constant after reaching predetermined threshold value, export trigger pulse and reset generation logic circuit to PLL；
PLL, which resets, produces logic circuit, after the trigger pulse for receiving the power on delay logic circuit output, production
The reset pulse of width needed for life.
As a further improvement on the present invention, the system reset detection logic circuit includes being used for detecting system reset letter
Number register chain and for judgement system reset persistent state the first decision logic unit, the register chain is by multiple
First register is sequentially connected composition, and the input access system reset signal of the register chain is as chain head, the deposit
The output end of each first register is respectively connecting to the input of the first decision logic unit in device chain, and described first
The output end output active homing pulse of decision logic unit or invalid reset pulse.
As a further improvement on the present invention, the decision logic unit is specifically by the output shape of each first register
State judges the persistent state of systematic reset signal, if it is determined that to the systematic reset signal continuous and effective in the register chain
Umber of beats is specified, active homing pulse is exported, otherwise exports idler Pulse.
As a further improvement on the present invention, the monostable circuit includes register group and for judging the register
The second of the stable state of group sentences decision logic unit, and the register group is connected and composed by multiple second registers, each described
The output end of the output end of second register and the system reset detection logic circuit is connected to pair after logic gates
The input for second register answered, the output end of each second register are respectively connecting to second decision logic
The input of unit, described second differentiates the output end output effective impulse of logic unit or idler Pulse.
As a further improvement on the present invention, the register group receives the system reset detection logic circuit output
Active homing pulse after remain output stationary value, by the second decision logic unit export effective impulse.
As a further improvement on the present invention, the power on delay logic circuit include the 3rd register and respectively with institute
First plus 1 logic unit and the 3rd decision logic of the 3rd register connection are stated, the 3rd register accesses the monostable electricity
The output pulse on road, if effective impulse, the 3rd register is carried out by described first plus 1 logic unit plus 1 counts,
Judge count whether reach predetermined threshold value by the 3rd decision logic, if it is, keep current count value constant, output triggering
Pulse produces logic circuit to PLL reset pulses.
As a further improvement on the present invention, it is invalid that the 3rd register, which receives the monostable circuit output pulse,
During pulse, in reset state, if the output pulse for receiving the monostable circuit is changed into effective impulse from idler Pulse, open
Beginning is carried out plus 1 counts.
As a further improvement on the present invention, the PLL reset pulses generation logic circuit includes the 4th be sequentially connected
Register, second plus 1 logic unit, the 5th register, the 4th decision logic and the 6th register, the system reset detection
The output of logic circuit with PLL losing locks signal after the first logical operation, obtained signal again with the power on delay logic
The input of the 4th register is accessed to after circuit output the second logical operation of progress, the 4th register output is effective
When, the 5th register is counted by described second plus 1 logic unit, judges that counting reaches by the 4th decision logic
During to predetermined threshold value, keep current count value constant, useful signal is exported by the 6th register to exit reset state.
As a further improvement on the present invention, when the 4th register output is invalid, the 5th register is in
Reset state, export from it is invalid be changed into effective when, proceed by plus 1 count.
Compared with prior art, the advantage of the invention is that：
1) present invention is used for the adaptive digital resetting means of phaselocked loop, is worth using electricity on different physical registers random
Property, pass sequentially through multiple deposits and realize the differentiation of system reset persistent state and monostability, then trigger steady logical circuit of counter so that obtain
Electric initial state and control upper electric stabilization time must be gone up, finally produces the reset pulse for meeting PLL requirements, complete numeral can be based on
PLL reliable resets after electricity is stable in logic realization, and multiple unit power-up state randomnesss are utilized, it can effectively reduce mistake
Sentence, realize reliable reset.
2) present invention is used for the adaptive digital resetting means of phaselocked loop, and further system reset detection logic circuit utilizes
Multiple flip-flop states randomnesss after upper electricity, realize whether effective has been kept to system reset by using reseting register chain
And reach the differentiation of desired width, the accuracy of identification for resetting edge can be improved, the self-adapting detecting to power up can be realized
Function, while burr and unexpected shake can also be filtered during hot reset.
3) present invention is used for the adaptive digital resetting means of phaselocked loop, and further monostable circuit profit is multiple after having access to electricity to be touched
The randomness of device state is sent out, monostability is differentiated by parallel multi-bit register group, it is small due to being directly in stable state probability,
Subsequent delay circuit count process (upper electricity is basically completed) after the reset is able to ensure that by the structure of parallel multi-bit register group
Triggering, while the self-adapting detecting function to power up can be realized.
4) present invention is used for the adaptive digital resetting means of phaselocked loop, further by configuring power on delay logic electricity
Road, it can be ensured that power up complete, system reset detection logic circuit and monostable circuit it is effective at the beginning of circuit only exist in one
The state that can be worked, but upper electricity is not fully finished, and triggers steady logical circuit of counter, it is stable so as to obtain upper electric initial state and the upper electricity of control
Time, electricity is completed, stably on whole chip when ensureing to count stable.
5) present invention is used for the adaptive digital resetting means of phaselocked loop, and further PLL reset pulses produce logic circuit
By merging electrification reset detection and two kinds of situations of hot reset PLL losing locks, electrification reset detection and hot reset PLL losing locks have been merged
Two kinds of situations, burr is resetted by reusing reseting register chain and eliminating, and using PLL losing locks monitoring logic, stabilization can be realized
Dynamic adaptive PLL is resetted, and reseting pulse width can be reconciled according to PLL specific requirement in implementation process, multiple so as to realize
Position signal burr filtering and stabilization function.
Brief description of the drawings
Fig. 1 is the structural representation for the adaptive digital resetting means that the present embodiment is used for phaselocked loop.
The timing diagram of each register during reset signal produces when Fig. 2 is electrification reset in the specific embodiment of the invention.
The timing diagram of each register during reset signal produces when Fig. 3 is hot reset in the specific embodiment of the invention.
Marginal data：1st, system reset detection logic circuit；11st, register chain；111st, the first register；12nd, first sentences
Disconnected logic unit；2nd, monostable circuit；21st, register group；211st, the second register；22nd, second sentences decision logic unit；3rd, upper electricity
Delay logic circuit；31st, the 3rd register；32nd, first adds 1 logic unit；33rd, the 3rd decision logic；4th, PLL resets generation and patrolled
Collect circuit；41st, the 4th register；42nd, second adds 1 logic unit；43rd, the 5th register；44th, the 4th decision logic unit；45、
6th register.
Embodiment
Below in conjunction with Figure of description and specific preferred embodiment, the invention will be further described, but not therefore and
Limit the scope of the invention.
As shown in figure 1, it is used for the adaptive digital resetting means of phaselocked loop in the present embodiment, including：
System reset detects logic circuit 1, for whether keeping effective by the reset of multiple register detecting systems and reaching
To desired width, active homing pulse is if it is produced to monostable circuit 2；
Monostable circuit 2, after receiving active homing pulse, a stable state is in by multiple registers, it is defeated
Go out the effective impulse of corresponding stable state to power on delay logic circuit 3；
Power on delay logic circuit 3, for being counted after receiving the effective impulse of the output of monostable circuit 2, until reaching
Keep constant after to predetermined threshold value, export trigger pulse and reset generation logic circuit 4 to PLL；
PLL, which resets, produces logic circuit 4, after the trigger pulse for receiving the output of power on delay logic circuit 3, produces
The reset pulse of required width.
The present embodiment is passed sequentially through multiple deposits and is realized system reset using the randomness of electricity value on different physical registers
Persistent state differentiates and monostability, then triggers steady logical circuit of counter so that electric initial state and control upper electric stabilization time in acquisition, most
The reset pulse for meeting PLL requirements is produced afterwards, can realize that the PLL after above electricity is stable is reliably multiple based on complete Digital Logic
Position, and multiple unit power-up state randomnesss are utilized, erroneous judgement can be effectively reduced, realizes reliable reset.
Realize that PLL resets by analog circuit compared to traditional, the present embodiment is produced by above-mentioned Digital Logical Circuits
PLL reset signals, single steady signal being produced after the power-up, and then producing the positive pulse of a fixed width, triggering PLL is answered
Position, the single steady signal can be independently using the reliabilities that can also be resetted with PLL after the upper electricity of analog circuit combined use raising；This
Embodiment can also be realized by using above-mentioned Digital Logical Circuits according to PLL working conditions using systematic reset signal (Reset)
Multiple reset to PLL, i.e., in the case of PLL losing locks, system reset triggering PLL resets, in the case where PLL does not have losing lock
PLL resets are not triggered, are stablized after the completion of being resetted so as to width can realization of the user by adjusting system reset pulse
Radio frequency system clock and the non-losing locks of PLL in the case of Rapid reset.
In the present embodiment, system reset detection logic circuit 1 specifically includes the register for detecting system reset signal
Chain 11 and the first decision logic unit 12 that persistent state is resetted for judgement system, register chain 11 is by the first register
111 are sequentially connected composition, and the input access system reset signal of register chain 11 is as chain head, each first in register chain 11
The output end of register 111 is connected to the input of the first decision logic unit 12, the output end of the first decision logic unit 12
Export active homing pulse or invalid reset pulse.First register 111 specifically can use multiple D without reset terminal to deposit
Device, the other types register without reset terminal can also be used, the quantity of the first register 111 can basis in register chain 11
Real needs configure.
The present embodiment profit multiple flip-flop states randomnesss after having access to electricity, realized by using reseting register chain to system
Whether reset has kept differentiation that is effective and reaching desired width, because upper electricity terminates rear wrong identification reset state probability
It is small, the accuracy of identification for resetting edge can be improved by way of reseting register chain；Multiple triggers can reach at the beginning of upper electricity
Also indicate that electricity is to a metastable stage on the whole to desired value, thus can be real by using register chain structure
Now to the self-adapting detecting function of power up, while burr can also be filtered by the form of reset chain during hot reset
With unexpected shake, reset shake and burr can be effectively eliminated, it is ensured that register group MRegs is after stabilization is resetted just from non-
Stationary value is changed into stationary value.
In the present embodiment, decision logic unit 12 specifically judges system reset by the output state of each first register 111
The persistent state of signal, if it is determined that in register chain 11 systematic reset signal continuous and effective specified umber of beats, output have
Reset pulse is imitated, idler Pulse is otherwise exported, i.e., judges that system reset continue for how much clapping by decision logic unit 12, such as N
Clap or N/2 is clapped, N is the number of the first register 111.
As shown in Fig. 2 the present embodiment is specifically N first by constructing a length without the first register 111 of reset terminal
Reset detection register chain RstChain, register chain RstChain using the system clock that chip inputs as clock, with core
The systematic reset signal of piece is chain head, and the value transmission of the chain can be that initial value can also be that initial value negates, i.e. some is by register
Q ends be connected to the D ends of next register ,~Q ends are connected to the D ends of next register by some；Patrolled again by a combination
NCycleRst structure decision logics unit 12 is collected, combinational logic NCycleRst inputs are each in register chain RstChain
The Q ends or NQ ends of first register 111, realize the following differentiation to register chain RstChain：If being " 0 " to whole piece chain,
NCycleRst outputs 1, otherwise export 0；If first half bar chain is " 0 ", later half bar chain is " 1 ", exports a clock period wide
Whole pulse, i.e. judgement system resets whether continuous and effective N is clapped or N/2, wherein the state corresponding to " 0 " and " 1 " is specific
It can according to the actual requirements be configured, such as be configured different by still negating the difference of connection register chain using initial value.
In the present embodiment, monostable circuit 2 includes register group 21 and for judging that the second judgement of stable state is patrolled
Unit 22 is collected, register group 21 is connected and composed by multiple second registers 211, the output end and system of each second register 211
The output end of reset detection logic circuit 1 is connected to the input of corresponding second register 211 after logic gates, the
The input of two decision logic units 22 connects the output end of each second register 211 respectively, and second differentiates logic unit 22
Output end exports effective impulse or idler Pulse.Second register 211, can also specifically using the D registers without reset terminal
Using the other types register without reset terminal.
The randomness of the present embodiment profit multiple flip-flop states after having access to electricity, differentiates list by parallel multi-bit register group
Steady state, it is small due to being directly in stable state probability, subsequent delay electricity is able to ensure that by the structure of parallel multi-bit register group
(the upper electricity is basically completed) triggering, while the self-adapting detecting function to power up can be realized after the reset of road counting process.
In the present embodiment, after register group 21 receives the active homing pulse that system reset detection logic circuit 1 exports
Output stationary value is remained, effective impulse is exported by the second decision logic unit 22, i.e., is examined by the second decision logic unit 12
Survey and reset whether edge is in a stable state.
As shown in Fig. 2 the present embodiment is specific to form monostable post by M the second registers 211 without reset terminal first
Storage group MRegs, using the system clock that chip inputs as clock, the D ends of each second register 211 can adopt this group of register
With following two kinds of logics：1. inputted the Q ends of actual registers and NCycleRst "or" as D ends；2. by actual registers
Q ends and (~NCycleRst) "AND" as D ends input.When 1. planting the register of input using the,
After NCycleRst is 1, register remains one state；When 2. planting the register of input using the, after NCycleRst is 1,
Remain " 0 " state.Register group MRegs is in random value at the beginning of upper electricity, but after NCycleRst is 1, in one
Stationary state, i.e., each register keeps a fixed value, and is no longer influenceed by NCycleRst.
The second decision logic unit 22 is built by a combinational logic MRegFix again, MRegFix input is register
The Q ends of M register in group MRegs；When all M registers are all in stationary value, MRegFix outputs 1,0 is otherwise exported.
In the present embodiment, power on delay logic circuit 3 specifically include the 3rd register 31 and respectively with the 3rd register
First plus 1 logic unit 32 and the 3rd decision logic 33 of 31 connections, the 3rd register 31 access the output arteries and veins of monostable circuit 2
Punching, if effective impulse, the 3rd register 31 is carried out by first plus 1 logic unit 32 plus 1 counts, by the 3rd decision logic
33 judge count whether reach predetermined threshold value, if it is, keeping current count value constant, export trigger pulse and reset production to PLL
Raw logic circuit.
The present embodiment is by configuring above-mentioned power on delay logic circuit 3, it can be ensured that power up is completed, system reset inspection
Circuit (is started counting up) at the beginning of surveying logic circuit 1 and monostable circuit 2 effectively and only exists in a state that can be worked, but upper electricity is not
Being fully finished, i.e. the counting process of power on delay logic circuit 3 is operated in " have electricity to work, but be not yet fully powered up between ",
Steady logical circuit of counter is triggered, so as to obtain upper electric initial state and control upper electric stabilization time, i.e., ensures that counting is steady by appropriate counting
Electricity is completed, stably on the whole chip of timing.The SerComm degree of falling into a trap of power on delay logic circuit 3 can be adjusted according to the actual requirements.
In the present embodiment, the 3rd register 31 receives monostable circuit 2 and exports pulse when be idler Pulse, in reset shape
State, if the output pulse for receiving monostable circuit 2 is changed into effective impulse from idler Pulse, proceeds by plus 1 counts.
Posted as shown in Fig. 2 the present embodiment specifically by one group there is the register StableCntRegs of reset terminal to form the 3rd
Storage 31, when MRegFix outputs are 0, StableCntRegs is in reset state；After MRegFix outputs are changed into 1 from 0,
StableCntRegs is proceeded by plus 1 counts；After StableCntRegs count down to desired value StableValue, the value is kept
It is constant.
In the present embodiment, PLL reset pulses produce the 4th register 41, second plus 1 that logic circuit 4 includes being sequentially connected
Logic unit 42, the 5th register 43, the 4th decision logic 44 and the 6th register 45, system reset detection logic circuit 1
Output and PLL losing locks signal after the first logical operation, obtained signal exports with power on delay logic circuit 3 again to be carried out
The input of the 4th register 41 is accessed to after second logical operation, when the output of the 4th register 41 is effective, the 5th register
43 are counted by second plus 1 logic unit 42, when judging that counting reaches predetermined threshold value by the 4th decision logic 43, keep working as
Preceding count value is constant, exports output useful signal by the 6th register 45 to exit reset state.
The present embodiment by using said structure PLL reset pulses produce logic circuit 4, merged electrification reset detection and
Two kinds of situations of hot reset PLL losing locks, burr is resetted by reusing reseting register chain and eliminating, and logic is monitored using PLL losing locks,
It can realize that the adaptive PLL of stabilization resets, it is wide to reconcile reset pulse according to PLL specific requirement in implementation process
Degree, so as to realize the filtering of reset signal burr and stabilization function.
In the present embodiment, the first logical operation operates for logical AND, and the second logical operation is logic or parameter, and the 4th deposits
Device 41 output for it is invalid when, the 5th register 43 be in reset state, export from it is invalid be changed into effective when, proceed by plus 1 count
Number.
As shown in Fig. 2 the present embodiment PLL reset pulses produce logic circuit 4 specifically by one group of deposit with reset terminal
Device RstCntRegs plus 1 logic, differentiate register (CntRst, PLLRst) composition of the logical sum two without reset terminal, deposit
Device CntRst as the 4th register 41, resetted for latching the upper electric PLL from system reset detection logic circuit output, with
The "or" for the adaptive reset that power on delay logic circuit 3 exports, when CntRst is 1, RstCntRegs is in reset state；
Register RstCntRegs is the 5th register 43, register PLLRst is the 6th register 45, after CntRst is changed into 0 from 1,
RstCntRegs is proceeded by plus 1 counts；After RstCntRegs count down to desired value RstCycles, keep the value constant, deposit
Device PLLRst latches RstCntRegs and RstCycles comparative result, and PLL exits reset state when both are equal.
Using said structure adaptive digital resetting means, realized by register chain and parallel multi-bit register group specific
Value differentiates and monostability, and triggers steady logical circuit of counter, and electric initial state and control upper electric stabilization time, finally produce and meet in acquisition
The reset pulse of PLL requirements, the PLL reliable resets after electricity stabilization can be realized, while during the subsequent reset of system,
Burr is resetted by reusing reseting register chain and eliminating, and using PLL losing locks monitoring logic, the adaptive of stabilization can be realized
PLL resets, and is designed to ensure that electrical secondary system resets L and can necessarily complete to reset by hot reset.
Respectively posted in the electrification reset course of work using above-mentioned adaptive digital resetting means in the specific embodiment of the invention
Storage sequential is as shown in figure 3, including following 6 stages：
1st stage：On establish by cable beginning dragged down to reset signal.
The stage, the reset of system and clock entered chip internal, respectively with electric on chip I/O interface and core system
Devices/circuits start discharge and recharge progress logical operation, and (upper possible signal swing at electric initial stage is relatively low, or even can not trigger lower logical
Complete normal upset).The hop mode difference of systematic reset signal makes this stage terminate that two kinds of situations can be divided into：If 1. system
Reset signal from it is upper electricity at the beginning of always remain as 0, then in this logic each trigger clock can stablize upset be this stage
Terminate；2. if reset signal initial pull-up is height, a negative pulse is then formed, then it is for the first time this rank by high step-down to reset
Section terminates.
The stage, each register logical state was as follows：
Reset detection register chain RstChain：For the above situation 1., each register is in initial random value, for upper
State situation 2., can be promoted with clock from it is upper electric when random value be changed into complete " 1 ", but no matter situation 1. or 2., on RstChain
Electricity is complete " 0 " so that NCycleRst is 1 probability very little；
The first meeting of electricity forms a random value on monostable register group MRegs, because NCycleRst is 1 probability very little
MRegs can be kept powered on initial value, the value make MRegFix be 1 probability very little, only when upper electric initial value be monostable fixed value or
NCycleRst be 1 triggering its when switching to monostable fixed value；
StableCntRegs can be kept default fixed initial value by MRegFix control, so as to phaselocked loop reset count
Its reseting register CntRst is set to 1, and reset count register is initial value, and PLL is in reset state.
2nd stage：Reset signal is the low top n cycle.
Reset detection register chain RstChain can with clock by shooting from complete " 1 " or upper electric when random value (for feelings
Condition is 1.) it is changed into complete " 0 ", NCycleRst is changed into 0 value determined；
Other register groups and control signal can keep or present the state in the 1st stage (if without the 1st stage).
3rd stage：The upper electric stabilization sub stage.
Reset detection register chain RstChain is changed into complete " 0 ", and NCycleRst saltus steps are 1；
Monostable register group MRegs is set default fixation and put, and MRegFix saltus steps are 1；
StableCntRegs is started counting up, until fixed value StableValue；
CntRst is defined as 1, and reset count device RstCntRegs is set to initial value, and the PLLRst of output is defined as height.
Until this stage terminates still tolerate upper piezoelectric voltage lifting, the output of various signals not necessarily achieves full width, i.e., one
Individual logical signal has all reached the minimum or ceiling voltage of expected design when being 0 or 1.
4th stage：The phaselocked loop active homing time.
Systematic reset signal, NCycleRst, MRegFix keep constant；
StableCntRegs is stable in fixed value StableValue；
CntRst saltus steps are 0, and reset count device (RstCntRegs) starts counting up, and the PLLRst of output is defined as height.
This stage upper electricity is set to complete, PLLRst is effectively resetted to PLL.
5th stage：The phase lock loop locks stage.
Systematic reset signal, NCycleRst, MRegFix, CntRst keep constant；
Reset count device (RstCntRegs) reaches RstCycles, and PLLRst saltus steps are 0；
PLL output frequencies gradually become expected frequence.
6th stage：Reset is exited, normal work.
Phaselocked loop successfully locks, and the saltus step of PLL_Lock signals is 1；
Systematic reset signal saltus step is 1, and system starts normal work；
NCycleRst is changed into 0, but MReg is not influenceed, and MRegFix, CntRst, PLLRst keep constant.
Hot reset work of the above-mentioned adaptive digital resetting means after phaselocked loop losing lock is used in the specific embodiment of the invention
Each register sequential during work is as shown in figure 3, electrification reset process can be divided into 4 stages：
1st stage：Hot reset detects and phaselocked loop reset trigger.
Systematic reset signal step-down, reset detection register chain RstChain can gradually become from complete " 1 " by shooting with clock
Entirely " 0 ", after [N/2] beat, to be determined as an active homing, a single bat high impulse is exported；
This singly clap high impulse when check PLL whether losing lock, if losing lock, set CntRst be 1, reset count device is set to
For initial value；
If detection finds the non-losing locks of PLL, phaselocked loop, which will reset interrelated logic, to be activated, and subsequently can only be answered in system
After position saltus step is 1, system worked well.
2nd stage：The phaselocked loop active homing time.
Reset count device (RstCntRegs) is counted, and the PLLRst of output is defined as height.
Set this stage voltage stable, PLLRst is effectively resetted to PLL.
3rd stage：The phase lock loop locks stage.
Reset count device (RstCntRegs) reaches RstCycles, and PLLRst saltus steps are 0；
PLL output frequencies gradually become expected frequence.
4th stage：Reset is exited, normal work.
Phaselocked loop successfully locks, and the saltus step of PLL_Lock signals is 1；
Systematic reset signal saltus step is 1, and system starts normal work.
The above-mentioned adaptive digital resetting means of the present embodiment is used, enables to PLL not to be constantly in the mould that is reset
Formula, during electrification reset, monostable circuit 2 determines to be in stable state after system reset is low N number of CLKIN cycles
(MRegFix saltus steps are 1), so as to discharge the reset to StableCntRegs, StableCntRegs is reaching StableValue
The control to RstCntRegs can be discharged afterwards, and RstCntRegs can only produce the reset pulse of fixed width；System hot reset mistake
It Cheng Zhong, only can just be triggered in the case of PLL losing locks, and produce pulse width and be fixed as RstCycles；
And use the above-mentioned adaptive digital resetting means of the present embodiment, additionally it is possible to obtain effective PLL and reset, because upper electricity is steady
When starting PLL resets and inadequate reseting pulse width before fixed, invalid reset can be caused, and use the above-mentioned adaptive number of embodiment
During word resetting means, only when upper electric MRegs initial values are stationary value (MRegFix=1) and StableCntRegs initial values are
During StableValue, it is only possible to PLL reset pulses occur, it is average by 0/1 that reset pulse produces too early and inadequate width situation
It is only 1/ (2M*StableValue) that distribution, which calculates probability, and by adjusting the specific data of trigger and StableValue also
The probability can further be reduced.
Above-mentioned simply presently preferred embodiments of the present invention, not makees any formal limitation to the present invention.It is although of the invention
It is disclosed above with preferred embodiment, but it is not limited to the present invention.Therefore, it is every without departing from technical solution of the present invention
Content, according to the technology of the present invention essence to any simple modifications, equivalents, and modifications made for any of the above embodiments, it all should fall
In the range of technical solution of the present invention protection.
Claims (9)
- A kind of 1. adaptive digital resetting means for phaselocked loop, it is characterised in that including：System reset detection logic circuit (1), for whether keeping effective by the reset of multiple register detecting systems and reaching Desired width, if it is produce active homing pulse and give monostable circuit (2)；Monostable circuit (2), after receiving the active homing pulse, a stable state is in by multiple registers, Power on delay logic circuit (3) is given in the effective impulse for exporting corresponding stable state；Power on delay logic circuit (3), for being counted after receiving the effective impulse of the monostable circuit (2) output, directly Keep constant to after reaching predetermined threshold value, export trigger pulse and reset generation logic circuit (4) to PLL；PLL, which resets, produces logic circuit (4), after the trigger pulse for receiving power on delay logic circuit (3) output, The reset pulse of width needed for generation.
- 2. the adaptive digital resetting means according to claim 1 for phaselocked loop, it is characterised in that the system is answered Position detection logic circuit (1) includes holding for the register chain (11) of detecting system reset signal and for judgement system reset First decision logic unit (12) of continuous state, the register chain (11) are sequentially connected structure by multiple first registers (111) Into, the register chain (11) input access system reset signal as chain head, it is each described in the register chain (11) The output end of first register (111) is respectively connecting to the input of the first decision logic unit (12), and described first sentences The output end output active homing pulse of disconnected logic unit (12) or invalid reset pulse.
- 3. the adaptive digital resetting means according to claim 2 for phaselocked loop, it is characterised in that：The judgement is patrolled The persistent state that unit (12) is specifically judged systematic reset signal by the output state of each first register (111) is collected, such as Fruit determines in the register chain (11) the specified umber of beats of systematic reset signal continuous and effective, exports active homing pulse, Otherwise idler Pulse is exported.
- 4. the adaptive digital resetting means for phaselocked loop according to claim 1 or 2 or 3, it is characterised in that：It is described Monostable circuit (2) includes the second judgement of register group (21) and the stable state for judging the register group (21) Logic unit (22), the register group (21) are connected and composed by multiple second registers (211), each second register (211) output end is connected to corresponding with the output end of system reset detection logic circuit (1) after logic gates Second register (211) input, the output end of each second register (211) is respectively connecting to described second The input of decision logic unit (22), described second differentiates the output end output effective impulse of logic unit (22) or invalid arteries and veins Punching.
- 5. the adaptive digital resetting means according to claim 4 for phaselocked loop, it is characterised in that：The register Group (21) remains output stationary value after receiving the active homing pulse of system reset detection logic circuit (1) output, Effective impulse is exported by the second decision logic unit (22).
- 6. the adaptive digital resetting means for phaselocked loop according to claim 1 or 2 or 3, it is characterised in that：It is described Power on delay logic circuit (3) include the 3rd register (31) and be connected respectively with the 3rd register (31) first add 1 logic unit (32) and the 3rd decision logic (33), the 3rd register (31) access the output arteries and veins of the monostable circuit (2) Punching, if effective impulse, the 3rd register (31) is carried out by described first plus 1 logic unit (32) plus 1 counts, by 3rd decision logic (33) judges count whether reach predetermined threshold value, if it is, keeping current count value constant, output is touched Send out pulse and reset generation logic circuit (4) to the PLL.
- 7. the adaptive digital resetting means according to claim 6 for phaselocked loop, it is characterised in that：Described 3rd posts Storage (31) receives the monostable circuit (2) output pulse when being idler Pulse, in reset state, if receiving the list When the output pulse of equalizing network (2) is changed into effective impulse from idler Pulse, proceeds by plus 1 counts.
- 8. the adaptive digital resetting means for phaselocked loop according to claim 1 or 2 or 3, it is characterised in that：It is described PLL reset pulses produce the 4th register (41) that logic circuit (4) includes being sequentially connected, second plus 1 logic unit (42), the Five registers (43), the 4th decision logic unit (44) and the 6th register (45), the system reset detect logic circuit (1) output with PLL losing locks signal after the first logical operation, obtained signal again with the power on delay logic circuit (3) input of the 4th register (41), the 4th register (41) output are accessed to after the second logical operation of output progress For it is effective when, the 5th register (43) by described second plus 1 logic unit (42) counted, by the described 4th judge When logic unit (44) judges that counting reaches predetermined threshold value, keep current count value constant, pass through the 6th register (45) Useful signal is exported to exit reset state.
- 9. the adaptive digital resetting means according to claim 8 for phaselocked loop, it is characterised in that：Described 4th posts Storage (41) output for it is invalid when, the 5th register (43) be in reset state, export from it is invalid be changed into effective when, beginning Carry out plus 1 counts.
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| CN201710898384.7A CN107634760B (en) | 2017-09-28 | 2017-09-28 | Adaptive digital reset device for phase-locked loop |
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| US6066988A (en) * | 1997-08-20 | 2000-05-23 | Nec Corporation | Phase locked loop circuit with high stability having a reset signal generating circuit |
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