CN108551336A - The computational methods and counting circuit of pulse signal duty ratio - Google Patents
The computational methods and counting circuit of pulse signal duty ratio Download PDFInfo
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- CN108551336A CN108551336A CN201810252025.9A CN201810252025A CN108551336A CN 108551336 A CN108551336 A CN 108551336A CN 201810252025 A CN201810252025 A CN 201810252025A CN 108551336 A CN108551336 A CN 108551336A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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Abstract
The invention discloses a kind of computational methods and counting circuit of pulse signal duty ratio.The technical solution of the embodiment of the present invention passes through when pulse signal level changes, detect the state of clock signal, then in the next period of the pulse signal, according to the state of detected clock signal, control the triggering of clock signal delay different time, from the clock signal triggering moment, the clock signal in the first level and current period is in the pulse signal respectively and counts the first count value of acquisition and the second count value, and obtains the duty ratio of the pulse signal accordingly.Therefore the duty ratio numerical value obtained in this way all same within each period of the pulse signal can effectively eliminate counting error, improve duty ratio precision, eliminate screen flicker.
Description
Technical field
The present invention relates to power electronic technique, more particularly, to a kind of computational methods and meter of pulse signal duty ratio
Calculate circuit.
Background technology
LED backlight simulates light regulating technology, it usually needs the duty cycle information of pwm signal is obtained, and it is most widely used at present
Be counter process.For example, using reference clock signal Clock as sampled signal, high level time Ton to pwm signal and
Whole cycle T distinguishes sample count, and duty ratio is the count ratio of Ton and T.The frequency of reference clock signal Clock is higher,
The duty ratio being then calculated is more accurate.
But pwm signal may not be synchronous with reference clock signal Clock.As shown in Figure 1, being counter process meter
Calculate the signal timing diagram of pwm signal duty ratio.In Fig. 1, since the high level time Ton of pwm signal and the length of cycle T differ
Surely it is the integral multiple of reference clock signal Clock, therefore in different PWM cycles, the meter of high level time Ton and cycle T
Number may be different.In this case, the accuracy of duty ratio calculating can be reduced.
In order to improve the accuracy of duty ratio calculating, one of the methods is pwm signal and reference clock signal Clock is same
Step.As shown in Fig. 2, calculating the signal timing diagram of pwm signal duty ratio using Synchronos method.In fig. 2, pwm signal and when benchmark
Clock signal Clock is synchronized.In the failing edge of the high level time Ton of a cycle pwm signal, reference clock signal is detected
Clock is high level, and the rising edge because of the failing edge apart from reference clock signal Clock is close, in noise and signal jitter
Under the influence of, in the failing edge of next PWM cycle high level time Ton, detect that reference clock signal Clock is low electricity
It is flat.In this way, just having 1 error to the counting of high level time Ton in the two PWM cycles.High level time Ton is got over
It is small, because the change in duty cycle in different cycles caused by error is bigger.If using on the screen of the electronic device, work as duty
The phenomenon that variation of ratio reaches certain value, and human eye will observe flicker.
Invention content
In view of this, an embodiment of the present invention provides a kind of computational methods and counting circuit of pulse signal duty ratio, with
Counting error is effectively eliminated, duty ratio precision is improved, eliminates screen flicker.
According to a first aspect of the embodiments of the present invention, a kind of computational methods of pulse signal duty ratio are provided, including with
Lower step：
1) when receiving the first detection signal for characterizing the pulse signal level saltus step, characterization clock signal shape is generated
The status signal of state；
2) it generates trigger signal according to the status signal in the next period of the pulse signal and controls the clock
The different delay time triggering of signal delay；
3) trigger signal to the clock signal between the first detection signal is counted, to obtain in terms of first
Numerical value；
4) to the trigger signal to characterize the pulse signal level saltus step second detection signal between it is described when
Clock signal-count, to obtain second value；
5) according to first count value and second count value, the duty ratio of the pulse signal is obtained.
Preferably, step 2) includes：
If the status signal characterizes the clock signal and is in first state, in the next week of the pulse signal
Phase triggers the first delay time of the clock signal delay；
If the status signal characterizes the clock signal and is in the second state, in the next week of the pulse signal
Phase triggers the second delay time of the clock signal delay.
Preferably, first count value, second count value and the duty ratio are in each of described pulse signal
All same in period.
Preferably, it is second electrical level that the first detection signal, which characterizes the pulse signal by the first level saltus step, described
Pulse signal described in second detection characterization is the first level by second electrical level saltus step.
Preferably, in a cycle of the pulse signal, the first delay time of the clock signal delay is triggered.
Preferably, the delay time is the integral multiple of the clock signal period.
Preferably, step 5) includes：The arteries and veins is obtained according to the ratio of first count value and second count value
Rush the duty ratio of signal.
Preferably, first delay time is more than second delay time.
According to a second aspect of the embodiments of the present invention, a kind of counting circuit of pulse signal duty ratio, the electricity are provided
Road includes：
Clock signal detection module for receiving the first detection signal for characterizing the pulse signal level variation, and produces
The status signal of raw characterization clock signal state；
Time-delayed trigger module, in the next period of the pulse signal, triggering letter to be generated according to the status signal
Number different delay time triggering of the control clock signal delay；
Counter module, based on to the trigger signal to the clock signal between the first detection signal
Number, to obtain the first count value；And the trigger signal to the clock signal between the second detection signal is counted, with
Obtain second value；
Duty ratio computing module, for according to first count value and second count value, obtaining the pulse letter
Number duty ratio.
Preferably, if the state of the clock signal detected is first state, in the next of the pulse signal
Period, the trigger signal control the first delay time of clock signal delay triggering；
If the state of the clock signal detected is the second state, in the next period of the pulse signal, institute
It states trigger signal and controls the second delay time of clock signal delay triggering.
Preferably, the circuit further includes：Pulse signal detection module, the level for detecting the pulse signal become
Change, and generates the first detection signal for characterizing the pulse signal level variation and the second detection signal.
Preferably, it is second electrical level that the first detection signal, which characterizes the pulse signal by the first level saltus step, described
Pulse signal described in second detection characterization is the first level by second electrical level saltus step.
Preferably, the circuit further includes：Clock signal generating module for receiving the trigger signal, and generates institute
State clock signal.
The technical solution of the embodiment of the present invention is by when pulse signal level changes, detecting the state of clock signal, so
Afterwards in the next period of the pulse signal, according to the state of detected clock signal, control clock signal delay is different
Time triggered is respectively in the first level and current period the pulse signal from the clock signal triggering moment
Clock signal count and obtain the first count value and the second count value, and obtain the duty ratio of the pulse signal accordingly.Pass through
Therefore the duty ratio numerical value that this mode obtains all same within each period of the pulse signal can effectively eliminate meter
Number error, improves duty ratio precision, eliminates screen flicker.
Description of the drawings
By referring to the drawings to the description of the embodiment of the present invention, the above and other purposes of the present invention, feature and
Advantage will be apparent from, in the accompanying drawings：
Fig. 1 is the existing signal timing diagram that pwm signal duty ratio is calculated using counter process；
Fig. 2 is the existing signal timing diagram that pwm signal duty ratio is calculated using Synchronos method；
Fig. 3 is a kind of flow chart of the computational methods of pulse signal duty ratio of embodiment according to the present invention；
Fig. 4 is the signal timing diagram using computational methods shown in Fig. 3；
Fig. 5-Fig. 7 is respectively illustrated using the stable state sequential for corresponding to 3 kinds of different pwm signals when calculation shown in Fig. 3
Figure；
Fig. 8 is a kind of block diagram of pulse signal duty ratio counting circuit of embodiment according to the present invention；
Fig. 9 is a kind of schematic diagram of Time-delayed trigger module of embodiment according to the present invention.
Specific implementation mode
Below based on embodiment, present invention is described, but the present invention is not restricted to these embodiments.Under
Text to the present invention datail description in, it is detailed to describe some specific detail sections.Do not have for a person skilled in the art
The description of these detail sections can also understand the present invention completely.In order to avoid obscuring the essence of the present invention, well known method, mistake
There is no narrations in detail for journey, flow, element and circuit.
In addition, it should be understood by one skilled in the art that provided herein attached drawing be provided to explanation purpose, and
What attached drawing was not necessarily drawn to scale.
It will also be appreciated that in the following description, " circuit " refer to passed through by least one element or sub-circuit it is electrical
The galvanic circle that connection or electromagnetism connect and compose.It " is connected when claiming element or another element of circuit " being connected to " or element/circuit
" between two nodes when, it can be directly coupled or connected another element or may exist intermediary element, element it
Between connection can be physically, in logic or its combination.On the contrary, when claiming element " being directly coupled to " or " directly connecting
Be connected to " another element when, it is meant that the two be not present intermediary element.
Unless the context clearly requires otherwise, "include", "comprise" otherwise throughout the specification and claims etc. are similar
Word should be construed as the meaning for including rather than exclusive or exhaustive meaning；That is, being containing for " including but not limited to "
Justice.
In the description of the present invention, it is to be understood that, term " first ", " second " etc. are used for description purposes only, without
It can be interpreted as indicating or implying relative importance.In addition, in the description of the present invention, unless otherwise indicated, the meaning of " multiple "
It is two or more.
Fig. 3 is a kind of flow chart of the computational methods of pulse signal duty ratio of embodiment according to the present invention.Such as Fig. 3 institutes
Show, the computational methods include：
Step S100：When receiving the first detection signal for characterizing the pulse signal level saltus step, when generating characterization
The status signal of clock signal condition.
Step S200：It generates trigger signal according to the status signal in the next period of the pulse signal and controls institute
State the different delay time triggering of clock signal delay.
Step S200 is specifically included：
Step S201：If the status signal characterizes the clock signal and is in first state, in the pulse signal
The next period, by the first delay time of clock signal delay Tdelay1 trigger；
Step S202：If the status signal characterizes the clock signal and is in the second state, in the pulse signal
The next period, by the second delay time of clock signal delay Tdelay2 trigger.
First delay time is more than second delay time.In one example, first delay time
Tdelay1 and the second delay time Tdelay2 meets：Tnoise<Tdelay1-Tdelay2<N/2Tclock-Tnoise,
Tnoise is the influence time that noise and shake generate the pulse signal and the clock signal, and Tclock is the clock
The period of signal, n are natural number.
Step S300：The trigger signal to the clock signal between the first detection signal is counted, to obtain
Obtain the first count value.
Step S400：To the trigger signal between the second detection signal for characterizing the pulse signal level saltus step
The clock signal counts, to obtain second value；
Step S500：According to first count value and second count value, the duty ratio of the pulse signal is obtained.
Specifically, in step S500, due to delay time very little, the precision of the duty ratio is not interfered with, it therefore, can
To obtain the duty ratio of the pulse signal according to the ratio of first count value and second count value.In an example
In, first delay time and second delay time could be provided as the integral multiple of the clock signal period, and set
Timing is set since the integral multiple of the clock signal period so that keep one with the trigger signal at the time of timing starts
It causes.
In above-mentioned or following embodiments, the pulse signal, which can be that pwm signal is either other, has varying level
Pulse signal；First level can be high level, and second electrical level can be correspondingly low level；Or first level can be with
For low level, and second electrical level can be correspondingly high level；The clock signal is high-frequency signal, has and is higher than the pulse
The frequency of signal.Certainly, it is not limited to the above example for the form of pulse signal and clock signal.The first state can be low
Level state, second state can be high level state；Or the first state can be low level state, described the
Two-state can be high level state.Certainly, it is not limited to the above example for the form of first state and the second state.
Computational methods in Fig. 3 in order to better understand are specifically described with reference to Fig. 4.
For clarity, the pwm signal is characterized by height by pwm signal and first detection signal of pulse signal below
Level saltus step be low level, second detection characterization described in pwm signal by low transition be high level and clock signal
First state be low level state, the second state be high level state for illustrate.
As shown in figure 4, for using computational methods shown in Fig. 3 signal timing diagram, wherein clock signal Clock1 and
Clock2 indicates the sequential of two kinds of different situations (i.e. delay time is respectively the first delay time and the second delay time) respectively.
First, when it is low level (i.e. failing edge) that pwm signal is by high level saltus step, the clock signal Clock is detected
State.
It, will be described in the next period of pwm signal if the clock signal Clock1 detected is low level state
Clock signal Clock1 delay the first delay time Tdelay1 triggerings.
It, will in the next period of the pwm signal if the clock signal Clock2 detected is high level state
The clock signal Clock2 delays the second delay time Tdelay2 triggerings.
Before, it is once mentioned in the description to Fig. 2, it is assumed that when noise is with the influence to pwm signal and Clock signals is shaken
Between be Tnoise, when the rising edge of clock signal Clock is fallen in the sections Tnoise, count value just has 1 error.And it adopts
After computational methods shown in Fig. 3, as shown in figure 4, no matter delay time be the first delay time or the second delay time, when
The rising edge of clock signal Clock will not be fallen in the sections Tnoise, thereby eliminate the turn-on time to pwm signal, period
Counting error.
Fig. 5-Fig. 7 is respectively illustrated using the stable state sequence diagram for corresponding to 3 kinds of different pwm signals shown in Fig. 3 when calculation.
As shown in figure 5, in the failing edge of each pwm signal, detect that the clock signal Clock is low level,
Therefore, in the next period of each pwm signal, the clock signal Clock postpones the first delay time Tdelay1 and touches
Hair.Clock signal counting between when to the failing edge of the triggering moment from the clock signal to the pwm signal is obtained
The first count value be N1, when occurring rising edge again to the triggering moment from the clock signal to the pwm signal between
Clock signal to count obtained the second count value be N2, it is known that, the high level time of pwm signal is N1*Tclock+
Tdelay1, period N2*Tclock+Tdelay1, therefore duty ratio D=(N1*Tclock+Tdelay1)/(N2*Tclock+
Tdelay1), because of the first delay time Tdelay1 very littles, can be neglected, therefore duty ratio D calculating can be reduced to D=N1*
Tclock/N2*Tclock=N1/N2, you can according to the acquisition of the ratio of first count value and second count value
The duty ratio of pwm signal.In this case, for the turn-on time of pwm signal and period count value in each period
All it is inside identical.
As shown in fig. 6, in the failing edge of each pwm signal, detect that the clock signal Clock is high level,
Therefore, in the next period of each pwm signal, the clock signal Clock postpones the second delay time Tdelay2 and touches
Hair.Clock signal counting between when to the failing edge of the triggering moment from the clock signal to the pwm signal is obtained
The first count value be N1 ', when occurring rising edge again to the triggering moment from the clock signal to the pwm signal between
Clock signal to count obtained the second count value be N2 ', it is known that, the high level time of pwm signal is N1 ' * Tclock+
Tdelay2, period N2 ' * Tclock+Tdelay2, therefore duty ratio D=(N1 ' * Tclock+Tdelay2)/(N2 ' * Tclock+
Tdelay2), similarly, because of the second delay time Tdelay2 very littles, can be neglected, therefore duty ratio D calculating can be reduced to D=
N1 ' * Tclock/N2 ' * Tclock=N1 '/N2 ', you can obtained according to the ratio of first count value and second count value
Obtain the duty ratio of the pwm signal.Equally, in this case, exist for the count value of the turn-on time of pwm signal and period
It is identical in each period.
As shown in fig. 7, the failing edge of a cycle in pwm signal, detects that the clock signal Clock is low electricity
Level state, then in the second period of pwm signal, the first delay time of clock signal Clock delays Tdealy1 is triggered,
And at the end of second period, and detect that the clock signal Clock is high level state, at this point, the clock is believed
Number Clock delay the second delay time Tdelay2 triggerings.Later, in the third of pwm signal, the 4th ... n-th period
It is interior, the work in meeting constantly repeatedly first, second period, when the clock signal Clock meetings alternating delay first is delayed
Between Tdelay1 and the second delay time Tdelay2 triggerings.In the figure 7, in a cycle of the pwm signal, to from institute
Clock signal between when stating the failing edge of the triggering moment of clock signal to the pwm signal counts obtained first and counts
Value is N1 ", when occurring rising edge again to the triggering moment from the clock signal to the pwm signal between clock signal
It is N2 " to count the second obtained count value, it is known that, the high level time of pwm signal is N1 " * Tclock+Tdelay1, period
For N2 " * Tclock+Tdelay1, therefore duty ratio D=(N1 " * Tclock+Tdelay1)/(N2 " * Tclock+Tdelay1), together
Sample, because of delay time Tdelay1 very littles, can be neglected, therefore in a cycle of the pwm signal, duty ratio D meters
Calculation can be reduced to D=N1 " * Tclock/N2 " * Tclock=N1 "/N2 ".And in the second period of the pwm signal, though
Right delay time becomes Tdelay2, but the calculation basis aforesaid way of duty ratio D, after simplified, remain as D=N1 "/
N2”.Therefore, either delay time is the first delay time Tdelay1 or the second delay time Tdelay2, can basis
The ratio of first count value and second count value obtains the duty ratio of the pwm signal.Equally, in such case
Under, the count value of turn-on time and period for pwm signal is identical within each period.
Fig. 8 is a kind of block diagram of pulse signal duty ratio counting circuit of embodiment according to the present invention.As shown in figure 8, institute
Stating pulse signal duty ratio counting circuit 800 includes：
Clock signal detection module 801, for receiving the first detection signal for characterizing the pulse signal level variation
VT1, and generate the status signal VS of characterization clock signal state；
Time-delayed trigger module 802, in the next period of the pulse signal, being generated and being touched according to the status signal VS
Signalling Trigger controls the different delay time triggering of the clock signal delay；
Counter module 803, for the trigger signal Trigger to the institute between the first detection signal VT1
Clock signal counting is stated, to obtain the first count value N1；And to the trigger signal Trigger to second detection signals VT2
Between the clock signal count, to obtain second value N2；
Duty ratio computing module 804, for according to the first count value N1 and the second count value N2, described in acquisition
The duty ratio D of pulse signal.
In one embodiment, the pulse signal duty ratio counting circuit 800 further includes：Pulse signal detection module
805, it is used for return pulse signal, and generate the first detection signal VT1 for characterizing the pulse signal level variation and institute
State the second detection signal VT2.
It is second electrical level that the first detection signal, which characterizes the pulse signal by the first level saltus step, second detection
Pulse signal described in characterization is the first level by second electrical level saltus step.
Wherein, pulse signal can be generated by the external equipment of chip, such as pwm signal generation circuit, using chip
PWM pins be converted to internal pwm signal；Or it can be directly given by the pwm signal generation circuit of chip interior.When
So, the generation of pulse signal is not limited to aforesaid way.
In one embodiment, the pulse signal duty ratio counting circuit 800 further includes：Clock signal generating module
806, for receiving the trigger signal Trigger, and generate the clock signal Clock.
In one embodiment, the concrete operating principle of the Time-delayed trigger module 802 includes：If for example, the state
Signal VS characterizes the clock signal Clock and is in first state, then in the next period of the pulse signal, that is, receives the
When two detection signal VT2, the trigger signal Trigger controls the relatively described second detection signals of the clock signal Clock
VT2 delay the first delay time Delay1 triggerings；If the status signal VS characterizes the clock signal Clock and is in the second shape
State, then in the next period of the pulse signal, that is, when receiving the second detection signal VT2, the trigger signal Trigger controls
Make relatively described second detection signal VT2 delays the second delay time Delay2 triggerings of the clock signal Clock.
Fig. 9 is a kind of schematic diagram of Time-delayed trigger module of embodiment according to the present invention.As shown in figure 9, the delay is touched
It includes switch Switch, the second delay time generation circuit and third delay time generation circuit to send out module 802.
Wherein, the second delay time generation circuit is connected in series with the third delay time generation circuit, described
The input terminal of second delay time generation circuit receives the second detection signal VT2, the output end of the third delay time
The trigger signal Trigger is generated, the switch Switch is in parallel with the third delay time generation circuit, the switch
The control terminal of Switch is controlled by the status signal VS.
If the status signal VS characterizes the clock signal Clock and is in first state, in the pulse signal
Next period, the status signal VS control the switch Switch and disconnect, and the trigger signal Trigger controls the clock
Relatively described second detection signal VT2 delays the first delay time Delay1 triggerings of signal Clock, wherein first delay
When time Delay1 is the second delay time Delay2 that the second delay time generation circuit generates and the third is delayed
Between the sum of the third delay time Delay3 that generates of generation circuit；If the status signal VS characterizes the clock signal Clock
In the second state, then in the next period of the pulse signal, the status signal VS controls the switch Switch and is closed
Make the third delay time generation circuit short circuit, the trigger signal Trigger controls the clock signal Clock as a result,
Relatively described second detection signal VT2 delays the second delay time Delay2 triggerings.
It is as a preferred mode, described in a cycle of the pulse signal in above each embodiment
The first delay time of clock signal delay triggers.Certainly, the clock signal can also postpone the triggering of the second delay time.
The technical solution of the embodiment of the present invention is by when pulse signal level changes, detecting the state of clock signal, so
Afterwards in the next period of the pulse signal, according to the state of detected clock signal, control clock signal delay is different
Time triggered is respectively in the first level and current period the pulse signal from the clock signal triggering moment
Clock signal count and obtain the first count value and the second count value, and obtain the duty ratio of the pulse signal accordingly.Pass through
Therefore the duty ratio numerical value that this mode obtains all same within each period of the pulse signal can effectively eliminate meter
Number error, improves duty ratio precision, eliminates screen flicker.
The foregoing is merely the preferred embodiment of the present invention, are not intended to restrict the invention, for those skilled in the art
For, the present invention can have various modifications and changes.It is all within spirit and principles of the present invention made by any modification, equivalent
Replace, improve etc., it should all be included in the protection scope of the present invention.
Claims (13)
1. a kind of computational methods of pulse signal duty ratio, which is characterized in that include the following steps：
1) when receiving the first detection signal for characterizing the pulse signal level saltus step, characterization clock signal state is generated
Status signal；
2) it generates trigger signal according to the status signal in the next period of the pulse signal and controls the clock signal
Postpone different delay time triggerings；
3) trigger signal to the clock signal between the first detection signal is counted, is counted with obtaining first
Value；
4) trigger signal to the clock between the second detection signal for characterizing the pulse signal level saltus step is believed
Number count, to obtain second value；
5) according to first count value and second count value, the duty ratio of the pulse signal is obtained.
2. computational methods according to claim 1, which is characterized in that step 2) includes：
It, will in the next period of the pulse signal if the status signal characterizes the clock signal and is in first state
The first delay time of the clock signal delay triggers；
It, will in the next period of the pulse signal if the status signal characterizes the clock signal and is in the second state
The second delay time of the clock signal delay triggers.
3. computational methods according to claim 1, which is characterized in that first count value, second count value and
Duty ratio all same within each period of the pulse signal.
4. computational methods according to claim 1, which is characterized in that the first detection signal characterizes the pulse signal
It is second electrical level by the first level saltus step, pulse signal described in the second detection characterization is first by second electrical level saltus step
Level.
5. computational methods according to claim 1, which is characterized in that in a cycle of the pulse signal, to institute
State the triggering of the first delay time of clock signal delay.
6. computational methods according to claim 1, which is characterized in that the delay time is the clock signal period
Integral multiple.
7. computational methods according to claim 1, which is characterized in that step 5) includes：According to first count value and
The ratio of second count value obtains the duty ratio of the pulse signal.
8. computational methods according to claim 2, which is characterized in that first delay time is more than described second and is delayed
Time.
9. a kind of counting circuit of pulse signal duty ratio, which is characterized in that the circuit includes：
Clock signal detection module for receiving the first detection signal for characterizing the pulse signal level variation, and generates table
Levy the status signal of clock signal state；
Time-delayed trigger module, in the next period of the pulse signal, trigger signal control to be generated according to the status signal
Make the different delay time triggering of the clock signal delay；
Counter module, for being counted to the trigger signal to the clock signal between the first detection signal, with
Obtain the first count value；And the trigger signal to the clock signal between the second detection signal is counted, to obtain
Second value；
Duty ratio computing module, for according to first count value and second count value, obtaining the pulse signal
Duty ratio.
10. counting circuit according to claim 8, which is characterized in that
It is described tactile in the next period of the pulse signal if the state of the clock signal detected is first state
It signals to control the first delay time of clock signal delay triggering；
It is described tactile in the next period of the pulse signal if the state of the clock signal detected is the second state
It signals to control the second delay time of clock signal delay triggering.
11. counting circuit according to claim 8, which is characterized in that the circuit further includes：
Pulse signal detection module, the level change for detecting the pulse signal, and generate for characterizing the pulse letter
The first detection signal of number level change and the second detection signal.
12. counting circuit according to claim 8, which is characterized in that the first detection signal characterizes the pulse letter
Number it is second electrical level by the first level saltus step, pulse signal described in the second detection characterization is the by second electrical level saltus step
One level.
13. counting circuit according to claim 8, which is characterized in that the circuit further includes：
Clock signal generating module for receiving the trigger signal, and generates the clock signal.
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|---|---|---|---|
| CN202111024193.0A CN113676162B (en) | 2018-03-26 | 2018-03-26 | Pulse signal level calculating method and circuit |
| CN201810252025.9A CN108551336B (en) | 2018-03-26 | 2018-03-26 | Pulse signal duty ratio calculation method and calculation circuit |
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| CN113068291A (en) * | 2021-03-30 | 2021-07-02 | 重庆长安汽车股份有限公司 | Welcome and welcome lamp control method and system based on PWM (pulse width modulation) signal and automobile |
| CN113068291B (en) * | 2021-03-30 | 2023-03-24 | 重庆长安汽车股份有限公司 | Welcome and welcome lamp control method and system based on PWM (pulse width modulation) signal and automobile |
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Also Published As
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|---|---|
| CN113676162A (en) | 2021-11-19 |
| CN113676162B (en) | 2024-02-23 |
| CN108551336B (en) | 2022-01-18 |
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