CN112782487A - Duty ratio detection system - Google Patents
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Abstract
This scheme provides a duty cycle detection system, its characterized in that, this system includes: the wide-voltage anti-interference shaping unit is used for shaping the PWM signal of the wide-voltage noise superposition to obtain a digital level PWM signal; and the duty ratio detection unit is used for obtaining the pulse width and the period of the digital level PWM signal by adopting a phase-shifting pulse counting method and determining the duty ratio based on the pulse width and the period. The scheme is not limited by a signal voltage range, and the anti-interference capability is strong; the wide-voltage anti-interference shaping unit can change voltage in a wide range and effectively and filter the influence of superposed noise signals on original signals; the duty ratio detection unit adopts a phase-shifting pulse technology method and can effectively improve the detection precision of the pulse width on the basis of a hardware technology; the scheme has wide popularization range in engineering application, low hardware cost, high efficiency and practicability.
Description
Technical Field
The embodiment of the scheme relates to the technical field of signal processing, in particular to a duty ratio detection system suitable for wide-voltage noise-superposed PWM signals.
Background
In practical applications, there are many pulse width modulation motors (hereinafter referred to as motors), such as pulse width modulation steering engines, and their driving control signals are a series of pulse waveforms with varying duty ratios, i.e., PWM signals. The drive controller can enable the motors to obtain corresponding information such as position, speed, angle and the like by adjusting the duty ratio of the drive control signal; meanwhile, the motor outputs an analog feedback signal to the driving controller to form a closed loop circuit with the driving controller.
The motors and the drive controllers thereof are inseparable, and one drive controller is often designed to be multi-channel and multi-functional in order to save resources in many times, so that a plurality of motors can be driven and controlled to act simultaneously. The reliability of the driving controller plays an important role for the motor, the electrical performance parameters of the motor need to be strictly measured, and the most direct solution is to connect one or more corresponding controlled motors and measure the motor by assisting a power supply with larger power. The power supply with larger power mentioned here is mainly used for supplying power to the controlled motor, and the power of the motor applied in industry or national defense is usually from dozens of watts to kilowatts.
In reality, if the method of configuring the corresponding motor and power supply for the mass-produced drive controller at the same time is too costly, the occupied space is huge. In fact, the interface between the driving controller and the motor is an electrical interface, and a motor simulator can be designed as long as the relation between the motor feedback signal and the driving control signal is found, so that the motor simulator can replace the real measurement of the motor matched with the driving controller. The motor simulator is finally changed into a circuit, the size is small, the weight is light, the problem of space placement can be solved, the cost can be greatly reduced, and the development period is shortened. And the multichannel motor simulator can realize the purpose of testing the electric performance of the drive controller in batch in a short time.
No matter what relationship exists between the motor feedback signal and the drive control signal, it is a precondition to extract the duty ratio parameter information in the drive control signal. Because the types and models of motors are different, the voltage requirements of driving control signals of the motors are greatly the same, and sometimes the driving control signals are influenced by using environmental factors, a lot of interference noise can be superposed when the driving control signals are output from a driving controller and then transmitted to the motors, the processing process of the PWM signals with wide-range noise superposition is complicated and the precision is low when the duty ratio parameters are measured by using the traditional method of conditioning circuits and A/D sampling detection, and the hardware parameters of the conditioning circuits need to be correspondingly adjusted as long as the level of the input voltage is changed, so that the existing design scheme has no way of adapting to the duty ratio detection of all the PWM signals with wide-range noise superposition.
Disclosure of Invention
In view of the above, the present invention provides a duty ratio detection system suitable for a wide-voltage noise-superimposed PWM signal.
In order to solve the above problem, according to an embodiment of the present invention, there is provided a duty ratio detection system, including:
the wide-voltage anti-interference shaping unit is used for shaping the PWM signal of the wide-voltage noise superposition to obtain a digital level PWM signal;
and the duty ratio detection unit is used for obtaining the pulse width and the period of the digital level PWM signal by adopting a phase-shifting pulse counting method and determining the duty ratio based on the pulse width and the period.
In a preferred embodiment, the wide-voltage interference rejection shaping unit includes: the voltage dividing/stabilizing selection circuit, the inverting hysteresis comparator circuit and the inverting logic isolation digital level conversion circuit are connected in sequence;
and the PWM signal of the wide-voltage superposition noise is processed by a voltage division/stabilization selection circuit, an inverse hysteresis comparator circuit and an inverse logic isolation digital level conversion circuit in sequence to obtain a digital level PWM signal.
In a preferred embodiment, the divide/regulate selection circuit includes: a first signal input terminal;
a first signal output terminal;
a first analog switch group connected between the first signal input terminal and the second signal output terminal; each analog switch in the first analog switch group is connected with the first signal input end through a peripheral resistor;
the second analog switch group is connected with the first signal output end and the ground end; each analog switch in the second analog switch group can be selectively connected with the ground end through two oppositely arranged diodes, a peripheral resistor or a diode according to an external control signal.
In a preferred embodiment, the inverting hysteretic comparator circuit comprises:
a second signal input terminal;
a second signal output terminal;
a comparator connected to the second signal input terminal and the second signal output terminal; the negative input end of the comparator is directly connected with the second signal input end; the positive input end of the comparator is connected with the ground end and the reference voltage end sequentially through the first resistor and the selection switch; the positive input end of the comparator is respectively connected with a second signal output end and a ground end through a second resistor, wherein two oppositely arranged diodes are connected between the second resistor and the ground end; and the output end of the comparator is connected with the second signal output end.
In a preferred embodiment, the inverse logic isolation digital level translation circuit comprises:
a third signal input terminal;
a third signal output terminal;
the high-speed optical coupler is connected between the third signal input end and the third signal output end; a current limiting resistor is connected between the high-speed optical coupler and the third signal input end; and the output end of the high-speed optocoupler is connected with a power supply voltage end through a pull-up resistor.
In a preferred embodiment, the duty ratio detection unit includes:
and the phase-locked loop module is used for generating two paths of clock signals which have the same frequency as the original signals and have phase differences.
In a preferred embodiment, the phase-locked loop module specifically performs the following steps:
processing the clock signal CLK0 based on a phase-shifting pulse counting method, sequentially shifting the phase by 90 degrees to form another three clock signals CLK90, CLK180 and CLK 270;
respectively driving four paths of counters by using the four paths of clock signals to measure the pulse to be measured;
if the frequency of the clock signal CLK0 is f and the period thereof is T equal to 1/f, the count values of the four clocks measured on the pulse signal to be measured are N1, N2, N3, and N4, respectively, and the measurement value of the last pulse signal to be measured is:
measuring pulse signals to be measured by using four paths of clocks, adding the measurement results, and equivalently measuring the pulses to be measured by using 4-frequency-multiplied clock signals with the clock frequency of 4 f;
the maximum error of the measurement is 1/4 of the clock period of the equivalent clock, i.e., the clock period of the clock signal CLK 0.
In a preferred embodiment, the duty ratio detection unit includes:
the calculation module is used for determining the period of the digital level PWM signal according to the width of the high level of the obtained PWM signal and the width of the low level of the PWM signal; and obtaining the duty ratio by using the ratio of the high level time of the digital level PWM signal to the period thereof.
In a preferred embodiment, the duty cycle detection unit is a programmable gate array FPGA.
The technical scheme of the embodiment of the scheme has the following advantages:
the scheme is not limited by a signal voltage range, and the anti-interference capability is strong; the wide-voltage anti-interference shaping unit can change voltage in a wide range and effectively and filter the influence of superposed noise signals on original signals; the duty ratio detection unit adopts a phase-shifting pulse technology method and can effectively improve the detection precision of the pulse width on the basis of a hardware technology; the scheme has wide popularization range in engineering application, low hardware cost, high efficiency and practicability.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a PWM signal of a wide-press noise stack according to the present embodiment;
FIG. 2 is a schematic diagram of the working principle of the wide-voltage anti-interference shaping unit according to the present embodiment;
FIG. 3 is a schematic diagram of the transmission characteristic of the inverting hysteretic comparator according to the present scheme;
FIG. 4 is a schematic diagram of the measurement principle of the phase-shift pulse counting method according to the present embodiment;
FIG. 5 is a schematic diagram of a wide-voltage noise-superimposed PWM signal in the present embodiment;
fig. 6 is a schematic diagram of a wide-voltage anti-interference shaping unit circuit in the present embodiment;
fig. 7 is a schematic diagram of the duty ratio detection unit in this embodiment calculating the duty ratio by using the FPGA.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The scheme is a simple and efficient detection method mainly aiming at duty ratio detection of the wide-voltage noise-superposed PWM signal. According to the scheme, the duty ratio of the PWM signal of the wide-pressing stacking noise is detected through a duty ratio detection system. The system consists of a wide-voltage anti-interference shaping unit and a duty ratio detection unit. The wide-voltage anti-interference shaping unit shapes the PWM signal of the wide-voltage superposition noise into the PWM signal which can be identified by the duty ratio detection unit, and simultaneously maintains the period and the duty ratio of the signal unchanged; the duty ratio detection unit is based on FPGA hardware, and adopts a phase-shifting pulse counting method to obtain the pulse width and the period of the PWM signal output by the wide-voltage anti-interference shaping unit, so as to obtain the duty ratio.
Fig. 1 is a schematic diagram of a PWM signal with wide noise superposition. U shapemaxIndicating the high level voltage amplitude, U, of the signalminRepresenting the low level voltage amplitude of the signal. Under different application scenes, UmaxMay range from a few volts to several hundred volts, UminIt may be a zero level voltage or a negative voltage, and may range from minus a few volts to minus a few hundred volts. The interference signal may be superimposed on a high level or may be superimposed on a low level.
The wide-voltage anti-interference shaping unit comprises a voltage dividing/stabilizing selection circuit, an inverting hysteresis comparator circuit and an inverting logic isolation digital level conversion circuit, and a schematic diagram of the wide-voltage anti-interference shaping unit is shown in fig. 2. U shapeiIs a PWM signal of wide superposition noise as shown in fig. 1. Analog switch SaAnd SbAnd its peripheral resistor and voltage-stabilizing tube, etc. form voltage-dividing/stabilizing circuit, in which C _ SaAnd C _ SbRespectively being an analogue switch SaAnd SbCan be controlled by an external control signal to the analog switch SaAnd SbPerforming control such as opening and closing and switching; u output by the voltage dividing/stabilizing circuitxEnters an inverse hysteresis comparator, outputs symmetrical positive and negative amplitudes with an absolute value of UzPWM signal U ofy；UyAfter the digital level conversion circuit is isolated through inverse logic, the circuit is integratedForming a digital level PWM signal U which can be identified by a duty ratio detection unit with the high level of 2.5V/3.3V and the low level of (0-0.8V)z. The signal UzLogic characteristic of and signal UyIn contrast, the signal UyLogic characteristic of and signal UxOn the contrary, so that the signal UzAnd the signal UxThe same is true.
FIG. 2 is a schematic diagram of a voltage division/stabilization selection circuit, for different levels, different frequencies of signal UiDifferent voltage division modes can be selected through the control end of the analog switch. The voltage-dividing and stabilizing topological structure of the resistor and the bidirectional voltage-stabilizing diode has strong anti-interference performance and is suitable for signals U with positive and negative levels and smaller frequencyi(ii) a The voltage-dividing and voltage-stabilizing topological structure of the resistor and the one-way voltage-stabilizing diode also has strong anti-interference performance, and is suitable for signals U with only positive level and smaller frequencyi(ii) a Although the pure-resistive voltage division topological structure has no anti-interference capability, the divided voltage signal UxThe frequency characteristic of the Ui can be closely tracked, and the problem of signal interference can be perfectly solved in the design of the inverting hysteresis comparator. In the case of a single-limit comparator, the superimposed noise will cause a transition of the input voltage if any slight variation is around the threshold, and finally affects the duty ratio detection result of the signal. The hysteresis comparator circuit has hysteresis characteristics, and therefore has certain anti-interference capability. The inverting hysteresis comparator is shown in FIG. 2 and corresponds to UxThere are two modes of operation with different level voltages. When U is turnedxIs a positive voltage, the threshold selection analog switch S is at the positive input terminal of the comparator N1yzSelectively connecting to reference voltage Uref(ii) a When U is turnedxWhen the level voltage of (b) has positive and negative voltages, the threshold selection analog switch S is provided at the positive input terminal of the comparator N1yzAnd selecting an access reference ground.
As shown in FIG. 2, if U isxIs a signal with positive and negative symmetry, and the threshold value selects the analog switch SyzSelecting the potential of the non-inverting input terminal connected to the reference ground
Let U+＝U-To find UXIs thus given a threshold voltage of
UyAnd UXThe transmission characteristic of (c) is shown in fig. 3 (a).
If U is presentXOnly a positive level signal, threshold selection analog switch SyzSelectively connecting to reference voltage UrefPotential of non-inverting input terminal
Let U+＝U-To find UXIs thus given a threshold voltage of
Due to the reference voltage Uref>0，UyAnd UxThe transmission characteristic of (c) is shown in fig. 3 (b). By changing the magnitude of the reference voltage, the voltage transmission characteristic of the hysteresis comparator generates horizontal movement; the voltage transmission characteristic can move in the vertical direction by changing the stable voltage of the voltage stabilizing tube.
From the output voltage of the inverting hysteretic comparator at the input voltage UyEqual to the threshold voltage, assume UxIs a signal with positive and negative symmetry, when Ux<-UTThen the input voltage U of comparator N1-Must be less than U+Thus U isy＝+UZSo that U is+＝+UT. Only when the input voltage U isxIncrease to + UTIncreasing by an infinitesimal amount again the output voltage UyWill go from + UZJump to-UZ. Similarly, assume Ux>+UTThen the input voltage U of comparator N1-Must be greater than U+Thus U isy＝-UZSo that U is+＝-UT. Only when the input voltage U isxReduced to-UTAnd when the voltage is reduced by an infinite small amount, the output voltage U isyWill be driven from-UZJump to + UZ. It can be seen that UyFrom + UZJump to-UZAnd Uy is from-UZJump to + UZAre different.
Signal U output by the hysteresis comparatoryAlready an output voltage amplitude of + -UZThe signal of (2) is input into an inverse logic isolation digital level conversion circuit, and finally, a PWM signal with a digital level of 2.5V or 3.3V at a high level and (0-0.8V) at a low level is formed in an integrated mode. As shown in fig. 2, the inverse logic isolation digital level conversion circuit is implemented by using a high-speed optical coupler, and the high level of the converted output is 2.5V or 3.3V, depending on the level voltage required by the I/O port of the duty ratio detection unit FPGA. R4 is a current-limiting resistor which limits the forward current of the optocoupler; r5 is a pull-up resistor, and the pull-up voltage determines the magnitude of the output high level voltage.
The duty ratio detection unit is based on FPGA hardware, and adopts a phase-shifting pulse counting method to obtain the pulse width and the period of the PWM signal output by the wide-voltage anti-interference shaping unit, so as to obtain the duty ratio. In a conventional pulse counting method, clock pulses are counted within a pulse width to be measured (generally, the rising edges of the clock pulses are counted, and the counting of the rising edges is taken as an example below), and the count value N is multiplied by the clock period T to obtain a value of the pulse width. The error of the method is derived from the time difference t1, t2 between the leading edge and the trailing edge of the pulse to be measured and the rising edge of the adjacent clock, and the maximum error is a value of one clock period, for example, if the clock frequency is 100MHz, the maximum error is 10 ns. In the conventional pulse counting method, if the timing precision is improved, the clock frequency needs to be improved, and the improvement of the clock frequency is limited by the performance of the device and brings certain difficulty to the design and processing of the printed circuit board. If nanosecond-level measurement accuracy is to be obtained, the clock frequency needs to reach 1GHz, which is difficult to apply in practical engineering. The invention provides a phase-shifting pulse counting method by applying a digital phase-shifting technology and combining an FPGA (field programmable gate array) on the basis of a conventional pulse counting method, and the measurement precision can be improved to nanosecond level. The phase shift is that the clock signal generates a certain time lag through the delay function of a phase-locked loop module (PLL) in the FPGA, and the newly generated signal and the original signal form two paths of clock signals with the same frequency and a certain phase difference. As shown in fig. 4, which is a schematic diagram of the measurement principle, the clock signal CLK0 is processed by a phase shifting technique, and is sequentially shifted by 90 ° to form three additional clock signals CLK90, CLK180, and CLK 270. And respectively driving the four paths of counters by using the four paths of clock signals to measure the pulse to be measured. Assuming that the frequency of the clock signal CLK0 is f and the period thereof is T1/f, the count values of the four clocks for the pulse signal to be measured are N1, N2, N3 and N4, respectively, and the measurement value of the last pulse signal to be measured is N1, N2, N3 and N4
As can be seen from equation (6) and fig. 4, each rising edge of the clock signals CLK0, CLK90, CLK180, and CLK270 respectively corresponds to a rising edge of the equivalent clock, so that the description can be made: four clocks are used to measure the pulse signal to be measured and the measurement results are added, which is equivalent to measuring the pulse to be measured by using a clock signal with 4 multiplied clock frequency 4 f. According to the conventional pulse counting method, the maximum error of the measurement result is 1/4 of the clock period of the equivalent clock, i.e., the clock period of the clock signal CLK 0. By the method, the purposes of reducing measurement errors and improving timing precision can be achieved on the premise of not improving the frequency of the counting clock.
The duty ratio detection unit obtains the pulse width of the PWM signal with higher precision, namely the width of a high level by using the phase-shift pulse counting method; similarly, after the signal to be measured is inverted, the width of the low level of the PWM signal can be obtained by the phase-shift pulse counting method, the sum of the two is the period of the signal to be measured, and the ratio of the time of the high level to the period is the duty ratio of the signal to be measured.
The duty ratio detection system for the PWM signals is not limited by a signal voltage range and is high in anti-jamming capability. The wide-voltage anti-interference shaping unit can change voltage in a wide range and effectively and filter the influence of superposed noise signals on original signals; the phase-shifting pulse technology method adopted by the duty ratio detection unit can effectively improve the detection precision of the pulse width on the basis of the hardware technology, and the hardware cost is low.
This solution is further explained below with reference to fig. 5 to 7.
The duty cycle detection system suitable for the PWM signal with wide voltage noise superposition mentioned above is further described in the present embodiment by way of example. The system comprises: the device comprises a wide-voltage anti-interference shaping unit and a duty ratio detection unit. The wide-voltage anti-interference shaping unit shapes the PWM signal of the wide-voltage superposition noise into the PWM signal which can be identified by the duty ratio detection unit, and simultaneously maintains the period and the duty ratio of the signal unchanged; the duty ratio detection unit is based on FPGA hardware, and adopts a phase-shifting pulse counting method to obtain the pulse width and the period of the PWM signal output by the wide-voltage anti-interference shaping unit, so as to obtain the duty ratio.
Wide-voltage noise superposition PWM signal U in the embodimentiIn particular, the frequency 10k (period 10)5ns), high level voltage 28V, low level voltage-28V, PWM signal with continuously changing duty ratio D, and superimposed noise voltage peak-to-peak value of 5V, as shown in fig. 5.
As shown in fig. 6, the wide-voltage interference rejection shaping unit in this embodiment includes a voltage divider circuit, an inverting hysteresis comparator circuit, and an inverting logic isolation digital level converter circuit.
Comparing fig. 2 and fig. 6, the present embodiment can be seen by setting the analog switch SaAnd SbControl terminal C _ SaAnd C _ SbSelecting the resistors R respectivelysa1And Rsb2Form a voltage dividing circuit Rsa1Value taking22k，Rsb1The value 10k, according to:
the high level voltage is 8.75V, the low level voltage is-8.75V, the frequency and the U are obtainediSame UxA signal. It should be noted that although the voltage divider circuit theoretically has a reduction effect on the superimposed noise level, the specific effect cannot be obtained by calculating the reduction amount of the noise peak-to-peak value by using a simple voltage divider calculation formula, here for the signal UxThe upper noise peak-to-peak value is considered to be less than 5V only.
As shown in fig. 6, the inverting hysteresis comparator in this embodiment is designed with the following parameters: the comparator adopts the power supply of 15V, and the steady voltage benchmark value of steady voltage geminate transistor selection is 5V, and R1 value 4k, R2 value 1 k. From the above parameters, the threshold voltage of the inverting hysteretic comparator can be obtained:
when U is turnedxWhen an interference signal with a peak value of +5V is superimposed on the low level of (1), Ux＝(-8.75+5)V，Uy+5V, so U+With +4V, no interference signal will cause the output signal UyOnly when the input voltage U is presentxIncreasing to +4V and then by an infinitesimal amount is the output voltage UyA transition from +5V to-5V will occur. In the same way, when UxWhen an interference signal with a peak value of-5V is superimposed on the high level of the signal, Ux＝(8.75-5)V，Uyis-5V, so U+No interference signal will cause the output signal U to be-4VyOnly when the input voltage U is presentxWhen the voltage is reduced to-4V and then reduced by an infinitesimal small quantity, the output voltage U is obtainedyIt will jump from-5V to + 5V. Thus, the output signal U of the inverting hysteretic comparatoryIs a non-interfering, polar input signal U of the circuitxThe inverted signal. The signal has high level of +5V, low level of-5V and frequency of 10kNull is (1-D) signal.
As shown in FIG. 6, the output signal U of the inverting hysteresis comparator circuit of this embodimentyAfter entering an inverse logic isolation digital level conversion circuit, a digital level PWM signal U with a high level of 3.3V and a low level of (0-0.8V) is finally formedZ. When U is turnedyWhen the current is high level, under the action of a current limiting resistor R4, the current is about 5mA through a front stage diode of an optocoupler B1, the diode is conducted, a rear stage triode of the optocoupler B1 is in saturation output, and a signal U is outputzAbout 0.3V; when U is turnedyWhen the level is low, the front stage of the optical coupler B1 is cut off, and UzAnd outputting a +3.3V voltage signal through a pull-up resistor. Thereby, the output signal U of the digital level conversion circuit is isolated in the reverse logic modezAnd its input signal UyThe polarity is reversed.
In conclusion, the output signal U of the whole wide-voltage anti-interference shaping unitzAnd an input signal UiThe polarities are the same, and the frequency and the duty ratio are consistent.
In the embodiment, the I/O level voltage of the FPGA adopted by the duty ratio detection unit is 3.3V. Since the frequency of the PWM signal in the embodiment is fixed to 10k, only the pulse width (i.e. high level time) of the PWM signal needs to be measured to obtain the duty ratio of the measured signal. The pulse width method adopted by the embodiment is a phase-shifting pulse counting method. Firstly, an FPGA internal phase-locked loop module (PLL) is utilized to generate four paths of clock signals with phases different by 90 degrees in sequence. In order to reduce the influence of high-frequency clock signals on the design of a printed circuit board, the frequency of an input clock signal is designed to be 50MHz, 5-time multiplication is carried out through a PLL to generate a clock with the frequency of 250MHz, and four paths of counting clock signals CLK0, CLK90, CLK180 and CLK270 with phases different by 90 degrees in sequence are generated through the phase shifting function of the PLL. Then, four counting modules (COUNTER) are generated by the counting module of the FPGA, and are driven by CLK0, CLK90, CLK180 and CLK270 respectively to count within the pulse width. As shown in fig. 7, the duty ratio detection unit uses an FPGA to calculate the duty ratio. The input pin pulse is a pulse signal to be measured, the input pin clr is a counting module zero clearing signal, and the output pin width is a measured pulse width output end.
Since the frequency of the counting clock signal is 250MHz and the period T is 4ns, it can be known from the above-described measurement technique and formula (6) that the pulse width is T-N1 + N2+ N3+ N4, i.e. the last output value of the adder is the measured pulse width in ns.
Finally, the measured pulse width is divided by the period 10 of the PWM signal5ns is the duty ratio of the signal to be measured.
For the above detailed logic implementation of the logic circuit unit, reference may be made to the corresponding descriptions of the method portions, and all the related portions in the description may be referred to correspondingly, which is not repeated herein
Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (9)
1. A duty cycle detection system, comprising:
the wide-voltage anti-interference shaping unit is used for shaping the PWM signal of the wide-voltage noise superposition to obtain a digital level PWM signal;
and the duty ratio detection unit is used for obtaining the pulse width and the period of the digital level PWM signal by adopting a phase-shifting pulse counting method and determining the duty ratio based on the pulse width and the period.
2. The system of claim 1, wherein the wide-voltage interference rejection shaping unit comprises: the voltage dividing/stabilizing selection circuit, the inverting hysteresis comparator circuit and the inverting logic isolation digital level conversion circuit are connected in sequence;
and the PWM signal of the wide-voltage superposition noise is processed by a voltage division/stabilization selection circuit, an inverse hysteresis comparator circuit and an inverse logic isolation digital level conversion circuit in sequence to obtain a digital level PWM signal.
3. The system of claim 2, wherein the divide/stabilize selection circuit comprises:
a first signal input terminal;
a first signal output terminal;
a first analog switch group connected between the first signal input terminal and the second signal output terminal; each analog switch in the first analog switch group is connected with the first signal input end through a peripheral resistor;
the second analog switch group is connected with the first signal output end and the ground end; each analog switch in the second analog switch group can be selectively connected with the ground end through two oppositely arranged diodes, a peripheral resistor or a diode according to an external control signal.
4. The system of claim 2, wherein the inverting hysteretic comparator circuit comprises:
a second signal input terminal;
a second signal output terminal;
a comparator connected to the second signal input terminal and the second signal output terminal; the negative input end of the comparator is directly connected with the second signal input end; the positive input end of the comparator is connected with the ground end and the reference voltage end sequentially through the first resistor and the selection switch; the positive input end of the comparator is respectively connected with a second signal output end and a ground end through a second resistor, wherein two oppositely arranged diodes are connected between the second resistor and the ground end; and the output end of the comparator is connected with the second signal output end.
5. The system of claim 2, wherein the inverse logic isolation digital level translation circuit comprises:
a third signal input terminal;
a third signal output terminal;
the high-speed optical coupler is connected between the third signal input end and the third signal output end; a current limiting resistor is connected between the high-speed optical coupler and the third signal input end; and the output end of the high-speed optocoupler is connected with a power supply voltage end through a pull-up resistor.
6. The system of claim 1, wherein the duty cycle detection unit comprises:
and the phase-locked loop module is used for generating two paths of clock signals which have the same frequency as the original signals and have phase differences.
7. The system of claim 6, wherein the phase-locked loop module performs the steps of:
based on phase-shift pulse counting method, clock signal CLK0 is processed to shift phase 90 in sequence0Forming three further clock signals CLK90, CLK180 and CLK 270;
respectively driving four paths of counters by using the four paths of clock signals to measure the pulse to be measured;
if the frequency of the clock signal CLK0 is f and the period thereof is T equal to 1/f, the count values of the four clocks measured on the pulse signal to be measured are N1, N2, N3, and N4, respectively, and the measurement value of the last pulse signal to be measured is:
measuring pulse signals to be measured by using four paths of clocks, adding the measurement results, and equivalently measuring the pulses to be measured by using 4-frequency-multiplied clock signals with the clock frequency of 4 f;
the maximum error of the measurement is 1/4 of the clock period of the equivalent clock, i.e., the clock period of the clock signal CLK 0.
8. The system according to claim 6 or 7, wherein the duty ratio detection unit comprises:
the calculation module is used for determining the period of the digital level PWM signal according to the width of the high level of the obtained PWM signal and the width of the low level of the PWM signal; and obtaining the duty ratio by using the ratio of the high level time of the digital level PWM signal to the period thereof.
9. The system according to claim 1 or 6, wherein the duty cycle detection unit adopts a programmable gate array (FPGA).
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