CN101762751A

CN101762751A - GLITCH detection circuit

Info

Publication number: CN101762751A
Application number: CN200810238897A
Authority: CN
Inventors: 孙雪萍; 郭健辉; 彭彬
Original assignee: Beijing Zhongkexin Electronic Equipment Co Ltd
Current assignee: Beijing Scintillation Section Zhongkexin Electronic Equipment Co ltd
Priority date: 2008-12-04
Filing date: 2008-12-04
Publication date: 2010-06-30
Anticipated expiration: 2028-12-04
Also published as: CN101762751B

Abstract

The invention discloses a GLITCH detection circuit which comprises a pulse amplitude detecting unit, a pulse width recognizing unit and a counting unit VI, wherein the three units are installed on a PCB of 60*80. The invention carries out expatiation on the working principle of the GLITCH detection circuit and provides a working timing sequence diagram and a concrete implementation scheme.

Description

The GLITCH testing circuit

Technical field

The present invention relates to the GLITCH detection technique, belong to control of semiconductor devices quality bills of materials and digital circuit field.

Background technology

Along with the semiconductor devices integrated level is more and more higher, the wafer size is increasing, and the unit component size is more and more littler, the raising of yield-power, the unit component size more and more littler to wafer inject the doping control procedure require more and more stricter, as implantation dosage and dose uniformity, repeatability.In ion implantation apparatus, in order to obtain needed ion beam, used multiple DC high-voltage power supply, as draw power supply, draw suppress to suppress power supply before power supply, high-voltage power supply, deceleration power supply, scanning power supply, the scanning, the scanning back suppresses power supply, quickens to suppress power supply etc., and the high voltage of these power supply outputs all is connected on the corresponding high-field electrode, these high-field electrodes all are in the high vacuum light path of ion operation, and these electrodes are all isolated with insulating element and ground electrode.The degradation reason all can cause these high-field electrodes discharges under the vacuum owing to the pollution of insulating part, ion beam collision electrode and tube wall venting make, these discharges can produce GLITCH, if in the wafer injection process, GLITCH occurs, can cause device yield to descend, thus this implantation quality of raising and control wafer the detection of GLITCH and control seemed be even more important.

Summary of the invention

At first we define causing the serious GLITCH that descends of wafer implantation quality: 12% its pulse width that exceeds normal steady-state value when disturbing signal is exactly a GLITCH greater than 100uS and less than 100mS.

The present invention is achieved through the following technical solutions: GLITCH detects theory diagram as shown in Figure 1:

The pulse-type disturbance a1 (pulse width is t1) that 2 pairs of input signals of circuit unit 1 occur compares with steady-state value b, if a1 exceeds b 12%, its pulse width of t1 pulse of circuit unit 2 meeting output waveforms 3 is t1; Pulse-type disturbance a2 (pulse width is t2) that 2 pairs of input signals of circuit unit 1 occur and steady-state value b compare, if a2 is lower than b 12%, its pulse width of t2 pulse that circuit unit 2 also can output waveform 3 is t2.

The pulse width t1 and the t2 of the waveform 3 of 4 pairs of circuit units of circuit unit, 2 outputs judge, if t1 and t2 are between 100uS and 100mS, just circuit unit 4 can provide waveform 5a (i.e. 2 GLITCH); If t1 is less than 100uS or greater than 100mS, and t2 is between 100uS and 100mS, just circuit unit 4 can provide waveform 5b (i.e. 1 GLITCH); If t2 is less than 100uS or greater than 100mS, and t1 is between 100uS and 100mS, just circuit unit 4 can provide waveform 5c (i.e. 1 GLITCH); If t1 and t2 are all less than 100uS or greater than 100mS, just circuit unit 4 can provide waveform 5d (i.e. 0 GLITCH).

The GLITCH that 6 pairs of circuit units of circuit unit 4 are determined count, and if when surpassing the maximum GLITCH that allows and count according to the GLITCH number of in the time of setting, being found, can send alerting signal to master controller, circuit unit 2 as shown in Figure 2.The principle of work of circuit unit 2 is: R1 and C1 are RC network that time constant is very big, its effect is the steady-state value Uw that obtains input signal, steady-state value Uw amplifies 0.88 times and 1.12 times respectively by amplifier A1 and A2, receive the negative input end of comparer A3 and the positive-negative input end of comparer A4 respectively as the benchmark of input signal perturbation amplitude comparison, A3 is used to detect the disturbing signal that disturbance causes steady-state value decline 12%, makes it to export a negative pulse; A4 is used to detect disturbance and causes the steady-state value rising to surpass 12% disturbing signal, makes it to export negative pulse .A3, an A4 output through not gate D1, and detected disturbing signal is become positive pulse.

Circuit unit 4 is as shown in Figure 3: circuit unit 4 has mainly adopted two can heavily trigger reducible monostable circuit TR1, TR2 and two reducible D flip-flop TR3, TR4; TR1, TR2 all adopt negative edge to trigger, and after TR1 was triggered, Q just can export its width of positive pulse by R3, C3 decision (T=0.5R3*C3=100uS); The pulse negative edge of TR1Q output triggers TR2, its width of positive pulse of TR2Q output is received the D end of TR3 by R4, C4 decision (T=0.5R3*C3=99.9mS) .TR2Q output, and the input pulse of TR1 is received the clock control end of TR3, if the input pulse width of TR1 greater than 100uS less than 100mS, the TR4Q end becomes high level by low level so, can detect next pulse this moment effectively, must (be determined by R2, C2) TR1, TR2, TR3 zero clearing in the regular hour.If the input pulse width of TR1 less than 100uS, (is determined by R5, C5) TR1, TR2 zero clearing within a certain period of time by TR4.Circuit unit 4 sequential are by shown in Fig. 4 a, Fig. 4 b, Fig. 4 c.

Fig. 4 a is that the input pulse width of TR1 is greater than the situation of 100uS less than 100mS

Fig. 4 b is the situation of the input pulse width of TR1 less than 100uS

Fig. 4 c is the situation of the input pulse width of TR1 greater than 100muS

The present invention has following remarkable advantage:

1. utilize RC network to obtain the stable state benchmark, utilize two comparers to detect perturbation pulse.

2. utilize two monostable circuits and two D flip-flops to constitute a GLITCH testing circuit dexterously

3. circuit is simple and reliable, and the design of reset circuit has effectively guaranteed flase drop and the omission of GLITCH.

Description of drawings

Fig. 1 GLITCH detects theory diagram

Fig. 2 circuit unit 2

Fig. 3 circuit unit 4

Fig. 4 circuit unit 4 sequential charts

Fig. 5 GLITCH detects and counting specific embodiment schematic diagram

Fig. 6 GLITCH detects and counting specific embodiment pcb map

Embodiment

The invention will be described further below in conjunction with accompanying drawing 5 specific embodiments, but not as a limitation of the invention.

Fig. 5 detects for GLITCH and counting specific embodiment schematic diagram: its 8 assemblies, 7 electric capacity, 17 resistance, 2 connector etc. such as bag A1, Uu1～U6, organically combine and constituted a simple and reliable GLITCH by these components and parts few in number and detect and counting circuit, and all be installed on one 60 * 80 the double-deck pcb board (as shown in Figure 6), and this pcb board is packed in the required power supply that GLITCH is monitored.

Its concrete principle of work is as follows:

Circuit is required ± 15V ,+5V working power and detected signal all introduce from connector J1.Receive the 9th pin (A1C-IN) of A1, the 12nd pin (A1D+IN) of A1 from the detected signal of J1 the 8th pin input respectively through R10, R11, and obtain the steady-state value Uw of detected signal through R1, C1 filtering, make A1A be output as the 1.12Uw benchmark of device A1C as a comparison by regulating P2, make A1B be output as () .88Uw benchmark of device A1D as a comparison by regulating P1, when disturbance causes descend 12% disturbing signal of steady-state value, A1D makes it to export a negative pulse; Surpass 12% disturbing signal when disturbance causes steady-state value to rise, A1C exports a negative pulse. and 5V stabilivolt DZ1, DZ2 work to do the clamper amplitude limit.U1 is that the perturbation pulse that two doors in the right are used for detecting from A1 among 2 inputs, the four Sheffer stroke gate figure carries out shaping.

The 5th pin of receiving U2 (two can heavily trigger the monostable circuit that can reset) respectively by the signal (negative pulse) of U1 the 4th pin output (TR1) and 3 pin (CP1), 5 pin (CP2) of U3 (two only trigger of setable D type that resets), the negative edge of negative pulse makes U2Q1 produce 100uS (=0.5R3C3) positive pulse, and the 11st pin that U2 is received in this pulse (TR2) and the 9th pin (D2) of U3.

If by signal (negative pulse) width of U1 the 4th pin output less than 100us, the rising edge of this pulse can make U3 the 13rd pin (Q2) uprise U3 the 12nd pin (Q2 is non-) step-down so, the effect of R5, C5 is that the about 2uS of time-delay resets U3 after U3 the 13rd pin (Q2) uprises, and the low level of the low level of U3 the 12nd pin (Q2 is non-) by U1 the 10th pin resets two monostable circuits of U2 simultaneously.

If by signal (negative pulse) width of U1 the 4th pin output greater than 100us less than 100mS, so the 100uS that U2Q1 produced (=0.5R3C3) negative edge of positive pulse will make the 10th pin (Q2) of U2 produce 99.9mS (=0.5R4C4) positive pulse, and the 5th pin (D1) of U3 is received in this pulse.The rising edge of U3 the 3rd pin (being the signal of U1 the 4th pin output) negative pulse can make U3 the 1st pin (Q1) uprise U3 the 2nd pin (Q1 is non-) step-down, R2, C2 effect are that the about 5uS of time-delay resets U3Q1 after U3 the 1st pin (Q1) uprises, just detected a GLITCH this moment, promptly find a GLITCH, U3 just exports the positive pulse that a pulse width is about 5uS; And the low level of the low level of U3 the 2nd pin (Q1 is non-) by U1 the 10th pin resets two monostable circuits of U2 simultaneously.

If by signal (negative pulse) width of U1 the 4th pin output greater than 100mS, so the 100uS that U2Q1 produced (=0.5R3C3) negative edge of positive pulse will make the 10th pin (Q2) of U2 produce 99.9mS (=0.5R4C4) positive pulse, and the 5th pin (D1) of U3 is received in this pulse.The rising edge of U3 the 3rd pin (being the signal of U1 the 4th pin output) negative pulse can make U3 the 1st pin (Q1) still for low U3 the 2nd pin (Q1 is non-) still is height, i.e. the signal (negative pulse) of U1 the 4th pin output is non-GLITCH.

U4 is that counter is counted the GLITCH that finds, U5 is a latch, and the GLITCH number that U4 is write down is latched among the U5 immediately, is convenient to master controller and reads and handle.U6, U7 be used for producing latch, the sum counter reset signal.

The above elaborates content of the present invention.For persons skilled in the art,, all constitute infringement, with corresponding legal responsibilities to patent of the present invention not deviating from any conspicuous change of under the prerequisite of the present invention it being done.

Claims

1.GLITCH testing circuit mainly comprises: pulse height detecting unit, pulse width recognition unit 4, counting unit 6, and these three unit are installed on the PCB of a 60*80.

It is characterized in that:

(1) said pulse height detecting unit 2 mainly is made up of one four fortune assembly and peripheral cell and a RC;

(2) said pulse height detecting unit 2 disturbing signal detecting that can cause signal to depart from steady-state value ± 12% disturbance is come out and is produced a negative pulse the same with the disturbing signal width;

(3) said pulse width recognition unit 4 mainly is made up of the two monostable circuits that can reset, two only triggers of setable D type that can reset, 4 RC network of can heavily triggering of dual input four Sheffer stroke gates;

(4) said pulse width recognition unit 4 can identify the pulse of certain pulse width effectively;

(5) said counting unit 6 mainly by a counter, latch, dual input four Sheffer stroke gate, one twoly can heavily trigger the monostable circuit that can reset and form.