CN103718459B - Detecting circuit and use method thereof - Google Patents
Detecting circuit and use method thereof Download PDFInfo
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- CN103718459B CN103718459B CN201380000361.XA CN201380000361A CN103718459B CN 103718459 B CN103718459 B CN 103718459B CN 201380000361 A CN201380000361 A CN 201380000361A CN 103718459 B CN103718459 B CN 103718459B
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Abstract
An embodiment of the invention discloses a detecting circuit which comprises the components of: a first monostable trigger which is used for receiving input pulses and outputting a corresponding level signal or pulse signal according to the period of the input pulse and the output pulse period of the first monostable trigger; a second monostable trigger which is used for receiving a level signal or pulse signal that is output from the first monostable trigger and outputting a corresponding detecting signal according to the period of the input pulse and the output pulse signal of the second monostable trigger; and a detecting module which is used for receiving the detected signal and determining the period of the input pulse according to the type of the detected signal, the output pulse period of the first monostable trigger and the output pulse period of the second monostable trigger. The embodiment of the invention further discloses a detecting circuit use method. The detecting circuit of the invention has the functions of: realizing accurate detection for disappear, slowing or quickening of the input pulse, and improving interference resistance and reliability of a processor system.
Description
Technical field
The present invention relates to electronic technology field, more particularly to a kind of detection circuit and its using method.
Background technology
Pulse or frequency detection circuit are all widely used in a variety of systems, such as industrial control field, security fields
Deng.Processor in system ensures whole system and safely and reliably runs by fixed frequency detecting or heartbeat mechanism.
In existing technical field, most representational detection circuit is watchdog circuit.Various including process
In the system of device, the pulse of a cycle is typically produced using processor.Whether watchdog circuit is by monitoring this pulse
Have normal output, so as to judge system in processor whether normal work.Watchdog circuit is actually a monitoring timing
Device, the time of its timing is changeless, when the processor normal work in system, in the time interval less than timing
Interior, processor can export a refresh signal and give watchdog circuit periodic refreshing, restart to count, and watchdog circuit would not
Reset signal or interrupt signal are produced, the processor in system will continue normal work；If timing is arrived, system is due to event
Barrier or program error normally do not export refresh signal and give watchdog circuit periodic refreshing, then watchdog circuit can produce reset
Signal or interrupt signal, indicate processor reset or interrupt routine operation.But, current watchdog circuit can only monitor process
The input pulse that device is produced disappears or slack-off situation, it is impossible to which the frequency of input pulse is judged, when input pulse becomes
When fast, watchdog circuit cannot note abnormalities.And traditional watchdog circuit also cannot be carried out to the frequency of input pulse
More accurately detect.
The content of the invention
Embodiments provide a kind of detection circuit and its using method, it is possible to achieve input pulse is disappeared, is become
Accurate detection that is slow or accelerating, improves the antijamming capability and reliability of provided with processor system.
Embodiment of the present invention first aspect provides a kind of detection circuit, it may include：
First monostable flipflop, for receives input pulse, and the cycle according to the input pulse and described first
The magnitude relationship of both output pulse periods of monostable flipflop, exports corresponding level signal or pulse signal；
Second monostable flipflop, for receiving the level signal or pulse letter of the first monostable flipflop output
Number, and the size of both output pulse periods of the cycle according to the input pulse and second monostable flipflop closes
System, exports corresponding detection signal；
Detection module, for receiving the detection signal, the type, first monostable according to the detection signal is touched
The output pulse period of the output pulse period and second monostable flipflop of sending out device judges the cycle of the input pulse；
Wherein, output of the output pulse period of first monostable flipflop less than second monostable flipflop
Pulse period.
In the first possible implementation of embodiment of the present invention first aspect, the detection circuit also includes first
Timing capacitor, the first timing resistor, the second timing capacitor and the second timing resistor, first timing capacitor one terminates described
The external capacitor pin of one monostable flipflop, the outer meeting resistance pin of another termination first monostable flipflop is described
First timing resistor one terminates positive source, the outer meeting resistance pin of another termination first monostable flipflop, and described the
Two timing capacitors one terminate the external capacitor pin of second monostable flipflop, another termination second monostable trigger
The outer meeting resistance pin of device, second timing resistor one terminates positive source, another termination second monostable flipflop
Outer meeting resistance pin.
With reference to the first possible implementation of first aspect, in second possible implementation, described first
Timing resistor and the second timing resistor are adjustable resistance.
With reference to first aspect or first or second possible implementation of first aspect, in the third possible realization
In mode, first monostable flipflop and the second monostable flipflop are Retargetable compiler monostable flipflop.
With reference to first aspect or first or second or the third possible implementation of first aspect, in the 4th kind of possibility
Implementation in, the model 74123 or 54123 of first monostable flipflop and the second monostable flipflop.
With reference to the 4th kind of possible implementation of first aspect, in the 5th kind of possible implementation, described first
The positive trigger input pin ground connection of monostable flipflop, bears trigger input pin and receives the input pulse, and reset pin connects height
Level, positive pulse output pin connects the negative trigger input pin of second monostable flipflop, second monostable trigger
The positive trigger input pin ground connection of device, reset pin connects high level, and positive pulse output pin connects the detection module.
With reference to the 5th kind of possible implementation of first aspect, in the 6th kind of possible implementation, if described defeated
Enter output pulse period of the pulse period less than first monostable flipflop, then the positive arteries and veins of first monostable flipflop
Rush output pin output high level signal, the positive pulse output pin output low level signal of second monostable flipflop；
If output pulse period and the input arteries and veins of the input pulse cycle more than first monostable flipflop
Output pulse period of the cycle less than second monostable flipflop is rushed, then the positive pulse of first monostable flipflop is defeated
Go out pin output pulse signal, the positive pulse output pin output high level signal of second monostable flipflop；
If the input pulse cycle, more than the output pulse period of second monostable flipflop, described first is single
The positive pulse output pin output pulse signal of steady state trigger, the positive pulse output pin of second monostable flipflop is defeated
Go out pulse signal.
Embodiment of the present invention second aspect provides a kind of detection circuit using method, it may include：
Input pulse is input into into the first monostable flipflop；
The monostable flipflop of signal input second that first monostable flipflop is exported；
Configure the pulse of the pulse output cycle less than second monostable flipflop of first monostable flipflop
The output cycle；
The pulse output of the detection signal, first monostable flipflop according to second monostable flipflop output
The pulse output cycle of cycle and second monostable flipflop judges the cycle of the input pulse.
It is described to configure first monostable in the first possible implementation of embodiment of the present invention second aspect
The pulse output cycle of trigger exports the cycle less than the pulse of second monostable flipflop, including：
The first timing capacitor and the first timing resistor are configured for first monostable flipflop；
The second timing capacitor and the second timing resistor are configured for second monostable flipflop；
By adjusting first timing resistor and the resistance of second timing resistor first monostable is touched
Send out the pulse output cycle of the pulse output cycle less than second monostable flipflop of device.
With reference to the first possible implementation of second aspect, in second possible implementation, described first
Timing resistor and the second timing resistor are adjustable resistance.
It is possible at the third with reference to second aspect or first or second possible implementation with reference to second aspect
In implementation, first monostable flipflop and the second monostable flipflop are Retargetable compiler monostable flipflop.
With reference to second aspect or first or second or the third possible implementation with reference to second aspect, at the 4th kind
In possible implementation, the model 74123 or 54123 of first monostable flipflop and the second monostable flipflop.
With reference to the 4th kind of possible implementation of second aspect, in the 5th kind of possible implementation, the basis
The detection signal of second monostable flipflop output, the pulse output cycle of first monostable flipflop and described the
The pulse output cycle of two monostable flipflops judges the cycle of the input pulse, including：
If the detection signal of the positive pulse output pin output of second monostable flipflop is low level signal, institute
State output pulse period of the input pulse cycle less than first monostable flipflop；
If the detection signal of the positive pulse output pin output of second monostable flipflop is high level signal, institute
Output pulse period and the input pulse cycle of the input pulse cycle more than first monostable flipflop is stated less than institute
State the output pulse period of the second monostable flipflop；
If the detection signal of the positive pulse output pin output of second monostable flipflop is pulse signal, described
Output pulse period of the input pulse cycle more than second monostable flipflop.
Implement the embodiment of the present invention, have the advantages that：
It is also right according to input signal difference output signal using monostable flipflop by configuring two monostable flipflops
The characteristic that should change realizes the detection to input signal types, while the pulse output week by configuring two monostable flipflops
Phase can realize the accurate detection to the input pulse cycle, and whole detection circuit structure is easy to use, with low cost, not only may be used
To realize, to input pulse disappearance, the detection of slack-off situation, the accurate detection for accelerating input pulse can also being realized, improve
The antijamming capability and reliability of provided with processor system.
Description of the drawings
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to institute in embodiment
The accompanying drawing that needs are used is briefly described, it should be apparent that, drawings in the following description are only some enforcements of the present invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can be being obtained according to these accompanying drawings
Obtain other accompanying drawings.
Fig. 1 is the connection diagram that the embodiment of the present invention detects circuit；
Fig. 2 is the schematic flow sheet that the embodiment of the present invention detects circuit using method.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than the embodiment of whole.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Fig. 1 is referred to, is the connection diagram that the embodiment of the present invention detects circuit, in the present embodiment, the detection electricity
Road includes：First monostable flipflop 1, the second monostable flipflop 2 and detection module 3.
Specifically, first monostable flipflop 1 is used for receives input pulse, and according to the cycle of the input pulse
With the magnitude relationship of both output pulse periods of first monostable flipflop 1, corresponding level signal or pulse are exported
Signal.
The input pulse can be in provided with processor system the refresh signal of processor timing output, or other
Need the input pulse of detection.
Second monostable flipflop 2 is used to receive the level signal or arteries and veins of the output of the first monostable flipflop 1
Rush signal, and the cycle according to the input pulse and both output pulse periods of second monostable flipflop 2 is big
Little relation, exports corresponding detection signal.
The detection module 3 is used to receive the detection signal, type according to the detection signal, described first monostable
The output pulse period of state trigger 1 and the output pulse period of second monostable flipflop 2 judge the input pulse
Cycle.
Wherein, the output pulse period of first monostable flipflop 1 is defeated less than second monostable flipflop 2
Go out the pulse period.
Preferably, the output pulse period of first monostable flipflop 1 is less than second monostable flipflop 2
The output pulse period, realized by adjusting corresponding external capacitor and outer meeting resistance.
For example, the detection circuit can also include the first timing capacitor, the first timing resistor, the second timing capacitor and the
Two timing resistors, first timing capacitor one terminates the external capacitor pin of first monostable flipflop 1, another termination
The outer meeting resistance pin of first monostable flipflop 1, first timing resistor one terminates positive source, another termination institute
The outer meeting resistance pin of the first monostable flipflop 1 is stated, second timing capacitor one terminates second monostable flipflop 2
External capacitor pin, the outer meeting resistance pin of another termination second monostable flipflop 2, second timing resistor one
Termination power positive pole, the outer meeting resistance pin of another termination second monostable flipflop 2.
More specifically, first timing resistor and the second timing resistor are adjustable resistance.Determined by adjusting described first
When resistance or the second timing resistor resistance can accordingly adjust the monostable of first monostable flipflop 1 or second touch
Send out the output pulse period of device 2.Eventually through detection signal type and two monostable flipflops the output pulse period just
May determine that the cycle of the input pulse is interval.
Preferably, the monostable flipflop 2 of first monostable flipflop 1 and second is Retargetable compiler monostable trigger
Device.
The continuous monitoring to input pulse and detection can thus be realized, it is ensured that whole provided with processor system is continuously steady
Fixed operation.
It is highly preferred that the model 74123 of the monostable flipflop 2 of first monostable flipflop 1 and second or
54123。
The positive trigger input pin ground connection of first monostable flipflop 1, bears trigger input pin and receives the input
Pulse, reset pin connects high level, and positive pulse output pin connects the negative trigger input pin of second monostable flipflop 2,
The positive trigger input pin ground connection of second monostable flipflop 2, reset pin connects high level, and positive pulse output pin meets institute
State detection module 3.
It is described when model 74123 or 54123 of the monostable flipflop 2 of first monostable flipflop 1 and second
First monostable flipflop 1 and the second monostable flipflop 2 possess two inputs, a reset terminal and two output ends, lead to
The input-output characteristic and sequential chart for analyzing the monostable flipflop 2 of first monostable flipflop 1 and second is crossed, can be obtained
Arrive：
If the input pulse cycle less than first monostable flipflop 1 the output pulse period, described first
The positive pulse output pin output high level signal of monostable flipflop 1, second monostable flipflop 2 is due to without pulse
The input of signal, so the positive pulse output pin output low level signal of second monostable flipflop 2；
If output pulse period and the input arteries and veins of the input pulse cycle more than first monostable flipflop 1
Output pulse period of the cycle less than second monostable flipflop 2 is rushed, then the positive pulse of first monostable flipflop 1
Output pin output pulse signal, therefore second monostable flipflop 2 can be triggered, but it is because the time cycle triggered
The cycle is exported less than the pulse of second monostable flipflop 2, so the positive pulse output of second monostable flipflop 2
Pin exports high level signal；
If the input pulse cycle more than second monostable flipflop 2 the output pulse period, described first
The positive pulse output pin output pulse signal of monostable flipflop 1, therefore second monostable flipflop 2 can be triggered,
But the time cycle for being because triggering is more than the input pulse cycle of second monostable flipflop 2, so described second is single
The positive pulse output pin output pulse signal of steady state trigger 2.
So, derive in turn, you can the type of the detection signal to be exported according to second monostable flipflop 2,
Judge the cycle of the input pulse with the output pulse period of first monostable flipflop 1 and second monostable
Magnitude relationship between the output pulse period of trigger 2.In summary, i.e.,：
The detection signal is low level signal, then the cycle of the input pulse is less than first monostable flipflop
1 pulse output cycle；
The detection signal is high level signal, then the cycle of the input pulse is more than first monostable flipflop
1 pulse output cycle, but it is less than the pulse output cycle of second monostable flipflop 2；
The detection signal is pulse signal, then the cycle of the input pulse is more than second monostable flipflop 2
Pulse output the cycle.
Can not only so detect that input pulse disappears or slack-off situation, while can also detect what input pulse accelerated
Situation, and by adjusting the resistance of outer meeting resistance and then adjusting the input pulse cycle of two monostable flipflops, you can with reality
Now the cycle of input pulse is more accurately judged, is the good of follow-up system call interception and whole provided with processor system
Operation provides basis.
For example, by adjusting the resistance of outer meeting resistance and then adjusting the input pulse cycle difference of two monostable flipflops
For T1=2 seconds, T2=4 seconds, if the detection signal is low level signal, the cycle T of the input pulse<2 seconds；If described
Detection signal is high level signal, then 2 seconds<T<4 seconds；If the detection signal is pulse signal, T>4 seconds.If it is desired to institute
The cycle for stating input pulse is more accurately detected that the resistance that can then pass through to adjust outer meeting resistance adjusts two monostables
The input pulse cycle of trigger is realized.For example, for the first time T is judged in detection<2 seconds, then can adjust T1=1 seconds, T2=
1.5 seconds, then implement the second detection and judge so as to obtain the more accurate scope of T.When 2 seconds<T<4 seconds or T>When 4 seconds, equally may be used
The cycle of the input pulse is more accurately detected with adjusting the input pulse cycle of two monostable flipflops,
Principle is similar to, and here is omitted.
Although giving a kind of model of specific monostable flipflop in the present embodiment, the present invention is not limited to
This.It will be appreciated by those skilled in the art that the present invention can also include that other arbitrarily can be exported according to input signal difference
Unlike signal possesses the monostable flipflop of state upset.But, 74123 or 54123 series be given in the present embodiment
Monostable flipflop not only applies ripe, with low cost, and can easily be accommodated, the convenient detection to the input pulse cycle.
The detection module 3 can be special signal deteching circuit, it is also possible to which second monostable flipflop 2 is defeated
The detection signal for going out is used for feedback control, the reset pin of processor is input to, when the cycle T of input pulse<During T1, described
Two monostable flipflop 2 exports low level signal, the processor reset is controlled, when the cycle T 1 of input pulse<T<During T2, institute
The output high level signal of the second monostable flipflop 2 is stated, processor keeps normal work.
Certainly, the embodiment of the present invention can be not only used for guaranteeing in any provided with processor system the normal work of processor and
Operation, so as to the antijamming capability and reliability of lift system, equally can be also used for special frequency or the detection in cycle, and
By the output pulse period for adjusting two monostable flipflops, testing result can be caused more accurate.
Fig. 2 is referred to, is the schematic flow sheet that the embodiment of the present invention detects circuit using method.In the present embodiment, institute
The method of stating is comprised the following steps：
S201, by input pulse the first monostable flipflop is input into.
Wherein, the input pulse can be the refresh signal of processor timing output in provided with processor system, it is also possible to
It is the input pulse of other needs detections.
S202, the monostable flipflop of signal input second that the first monostable flipflop is exported.
S203, configures the pulse output cycle of first monostable flipflop less than second monostable flipflop
Pulse exports the cycle.
Preferably, the pulse output cycle of the configuration first monostable flipflop is tactile less than second monostable
The pulse output cycle of device is sent out, including：
The first timing capacitor and the first timing resistor are configured for first monostable flipflop；
The second timing capacitor and the second timing resistor are configured for second monostable flipflop；
By adjusting first timing resistor and the resistance of second timing resistor first monostable is touched
Send out the pulse output cycle of the pulse output cycle less than second monostable flipflop of device.
Wherein, first timing resistor and the second timing resistor are adjustable resistance.By adjusting the first timing electricity
The resistance of resistance or the second timing resistor can accordingly adjust first monostable flipflop or the second monostable flipflop
The output pulse period.Just can sentence eventually through the type of detection signal and the output pulse period of two monostable flipflops
The cycle of the disconnected input pulse is interval.
First monostable flipflop and the second monostable flipflop are Retargetable compiler monostable flipflop.
The continuous monitoring to input pulse and detection can thus be realized, it is ensured that whole provided with processor system is continuously steady
Fixed operation.
It is highly preferred that the model 74123 or 54123 of first monostable flipflop and the second monostable flipflop.
By the input-output characteristic and sequential chart of analyzing first monostable flipflop and the second monostable flipflop,
The relation between detection signal and the input pulse cycle can be obtained.
S204, the arteries and veins of detection signal, first monostable flipflop according to second monostable flipflop output
The pulse output cycle for rushing output cycle and second monostable flipflop judges the cycle of the input pulse.
Specifically include：
If the detection signal of the positive pulse output pin output of second monostable flipflop is low level signal, institute
State output pulse period of the input pulse cycle less than first monostable flipflop；
If the detection signal of the positive pulse output pin output of second monostable flipflop is high level signal, institute
Output pulse period and the input pulse cycle of the input pulse cycle more than first monostable flipflop is stated less than institute
State the output pulse period of the second monostable flipflop；
If the detection signal of the positive pulse output pin output of second monostable flipflop is pulse signal, described
Output pulse period of the input pulse cycle more than second monostable flipflop.
Can not only so detect that input pulse disappears or slack-off situation, while can also detect what input pulse accelerated
Situation, and by adjusting the resistance of outer meeting resistance and then adjusting the input pulse cycle of two monostable flipflops, you can with reality
Now the cycle of input pulse is more accurately judged, is the good of follow-up system call interception and whole provided with processor system
Operation provides basis.
For example, by adjusting the resistance of outer meeting resistance and then adjusting the input pulse cycle difference of two monostable flipflops
For T1=2 seconds, T2=4 seconds, if the detection signal is low level signal, the cycle T of the input pulse<2 seconds；If described
Detection signal is high level signal, then 2 seconds<T<4 seconds；If the detection signal is pulse signal, T>4 seconds.If it is desired to institute
The cycle for stating input pulse is more accurately detected that the resistance that can then pass through to adjust outer meeting resistance adjusts two monostables
The input pulse cycle of trigger is realized.For example, for the first time T is judged in detection<2 seconds, then can adjust T1=1 seconds, T2=
1.5 seconds, then implement the second detection and judge so as to obtain the more accurate scope of T.When 2 seconds<T<4 seconds or T>When 4 seconds, equally may be used
The cycle of the input pulse is more accurately detected with adjusting the input pulse cycle of two monostable flipflops,
Principle is similar to, and here is omitted.
Although giving a kind of model of specific monostable flipflop in the present embodiment, the present invention is not limited to
This.It will be appreciated by those skilled in the art that the present invention can also include that other arbitrarily can be exported according to input signal difference
Unlike signal possesses the monostable flipflop of state upset.But, 74123 or 54123 series be given in the present embodiment
Monostable flipflop not only applies ripe, with low cost, and can easily be accommodated, the convenient detection to the input pulse cycle.
The detection signal of output can be also used for feedback control, the reset pin of processor is input to, when input pulse
Cycle T<During T1, second monostable flipflop 2 exports low level signal, controls the processor reset, works as input pulse
Cycle T 1<T<During T2, second monostable flipflop 2 exports high level signal, and processor keeps normal work.
Certainly, the embodiment of the present invention can be not only used for guaranteeing in any provided with processor system the normal work of processor and
Operation, so as to the antijamming capability and reliability of lift system, equally can be also used for special frequency or the detection in cycle, and
By the output pulse period for adjusting two monostable flipflops, testing result can be caused more accurate.
One of ordinary skill in the art will appreciate that：Realizing all or part of step of said method embodiment can pass through
Completing, aforesaid program can be stored in a computer read/write memory medium the related hardware of programmed instruction, the program
Upon execution, the step of including said method embodiment is performed；And aforesaid storage medium includes：ROM, RAM, magnetic disc or light
Disk etc. is various can be with the medium of store program codes.
A kind of detection circuit for being provided the embodiment of the present invention above and its using method are described in detail, herein
In apply specific case the principle and embodiment of the present invention be set forth, the explanation of above example is only intended to side
Assistant solves the method for the present invention and its core concept；Simultaneously for one of ordinary skill in the art, according to the think of of the present invention
Think, will change in specific embodiments and applications, in sum, it is right that this specification content should not be construed as
The restriction of the present invention.
Claims (11)
1. it is a kind of to detect circuit, it is characterised in that to include：
First monostable flipflop, for receives input pulse, and the cycle according to the input pulse is monostable with described first
The magnitude relationship of both output pulse periods of state trigger, exports corresponding level signal or pulse signal；
Second monostable flipflop, for receiving the level signal or pulse signal of the first monostable flipflop output, and
In cycle and the magnitude relationship of both output pulse periods of second monostable flipflop according to the input pulse, export
Corresponding detection signal；
Detection module, the type, first monostable flipflop for receiving the detection signal, according to the detection signal
The output pulse period and output pulse period of second monostable flipflop judge cycle of the input pulse；
Wherein, output pulse of the output pulse period of first monostable flipflop less than second monostable flipflop
Cycle, first monostable flipflop and the second monostable flipflop are Retargetable compiler monostable flipflop.
2. detection circuit as claimed in claim 1, it is characterised in that the detection circuit also include the first timing capacitor, the
One timing resistor, the second timing capacitor and the second timing resistor, first timing capacitor one terminates first monostable and touches
Send out the external capacitor pin of device, the outer meeting resistance pin of another termination first monostable flipflop, the first timing electricity
Resistance one terminates positive source, the outer meeting resistance pin of another termination first monostable flipflop, second timing capacitor
The external capacitor pin of one termination second monostable flipflop, the external electricity of another termination second monostable flipflop
Resistance pin, second timing resistor one terminates positive source, the outer meeting resistance of another termination second monostable flipflop
Pin.
3. it is as claimed in claim 2 to detect circuit, it is characterised in that first timing resistor and the second timing resistor are can
Adjust resistance.
4. the detection circuit as described in any one of claim 1-3, it is characterised in that first monostable flipflop and second
The model 74123 or 54123 of monostable flipflop.
5. it is as claimed in claim 4 to detect circuit, it is characterised in that the positive trigger input of first monostable flipflop is drawn
Pin is grounded, and bears trigger input pin and receives the input pulse, and reset pin connects high level, and positive pulse output pin connects described the
The negative trigger input pin of two monostable flipflops, the positive trigger input pin ground connection of second monostable flipflop, resets
Pin connects high level, and positive pulse output pin connects the detection module.
6. it is as claimed in claim 5 to detect circuit, it is characterised in that to include：
If the input pulse cycle is less than the output pulse period of first monostable flipflop, first monostable
The positive pulse output pin output high level signal of trigger, the positive pulse output pin output of second monostable flipflop
Low level signal；
If the input pulse cycle is more than the output pulse period and input pulse week of first monostable flipflop
Phase is less than the output pulse period of second monostable flipflop, then the positive pulse output of first monostable flipflop is drawn
Pin output pulse signal, the positive pulse output pin output high level signal of second monostable flipflop；
If the input pulse cycle is more than the output pulse period of second monostable flipflop, first monostable
The positive pulse output pin output pulse signal of trigger, the positive pulse output pin output arteries and veins of second monostable flipflop
Rush signal.
7. it is a kind of to detect circuit using method, it is characterised in that to include：
Input pulse is input into into the first monostable flipflop；
The monostable flipflop of signal input second that first monostable flipflop is exported；
The pulse output cycle for configuring first monostable flipflop exports less than the pulse of second monostable flipflop
Cycle；
The pulse output cycle of the detection signal, first monostable flipflop according to second monostable flipflop output
And the pulse output cycle of second monostable flipflop judges the cycle of the input pulse, first monostable trigger
Device and the second monostable flipflop are Retargetable compiler monostable flipflop.
8. method as claimed in claim 7, it is characterised in that the pulse output of the configuration first monostable flipflop
Cycle exports the cycle less than the pulse of second monostable flipflop, including：
The first timing capacitor and the first timing resistor are configured for first monostable flipflop；
The second timing capacitor and the second timing resistor are configured for second monostable flipflop；
First monostable flipflop is caused by adjusting first timing resistor with the resistance of second timing resistor
Pulse output the cycle less than second monostable flipflop pulse output the cycle.
9. method as claimed in claim 8, it is characterised in that first timing resistor and the second timing resistor are adjustable electric
Resistance.
10. the method as described in any one of claim 7-9, it is characterised in that first monostable flipflop and second single
The model 74123 or 54123 of steady state trigger.
11. methods as claimed in claim 10, it is characterised in that the inspection according to second monostable flipflop output
Survey the pulse output cycle of signal, the pulse output cycle of first monostable flipflop and second monostable flipflop
Judge the cycle of the input pulse, including：
If the detection signal of the positive pulse output pin output of second monostable flipflop is low level signal, described defeated
Enter output pulse period of the pulse period less than first monostable flipflop；
If the detection signal of the positive pulse output pin output of second monostable flipflop is high level signal, described defeated
Enter output pulse period and the input pulse cycle of the pulse period more than first monostable flipflop less than described the
The output pulse period of two monostable flipflops；
If the detection signal of the positive pulse output pin output of second monostable flipflop is pulse signal, the input
Output pulse period of the pulse period more than second monostable flipflop.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3898481A (en) * | 1974-03-28 | 1975-08-05 | Cincinnati Electronics Corp | Signal pulse detector |
| CN101762751A (en) * | 2008-12-04 | 2010-06-30 | 北京中科信电子装备有限公司 | GLITCH detection circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3898481A (en) * | 1974-03-28 | 1975-08-05 | Cincinnati Electronics Corp | Signal pulse detector |
| CN101762751A (en) * | 2008-12-04 | 2010-06-30 | 北京中科信电子装备有限公司 | GLITCH detection circuit |
Non-Patent Citations (2)
| Title |
|---|
| D触发器在脉冲宽度检测电路中的应用;苏成富;《电子技术》;19931231(第5期);第29-30，42页 * |
| 可重复触发单稳态触发器在检测电路中的应用;王全宇;《自动化与仪器仪表》;20111231(第155期);第100-101页 * |
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