CN106849920A - A kind of repositioning method, reset signal output circuit and reset system - Google Patents
A kind of repositioning method, reset signal output circuit and reset system Download PDFInfo
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- CN106849920A CN106849920A CN201710083888.3A CN201710083888A CN106849920A CN 106849920 A CN106849920 A CN 106849920A CN 201710083888 A CN201710083888 A CN 201710083888A CN 106849920 A CN106849920 A CN 106849920A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger
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Abstract
The embodiment of the invention provides a kind of repositioning method, reset signal output circuit and reset system.On the one hand, the reset system includes：Reset signal output circuit, the first input end of the reset signal output circuit is connected with the first power supply, and the second input of the reset signal output circuit is connected with second source；Two input nor gate logic chips, the inputs of the two inputs nor gate logic chip be connecteds with the output end of the reset signal output circuit, and described two are input into the output end of nor gate logic chip and treat reset circuit and be connected.Because the reset system in the embodiment of the present invention is made up of digital circuit, and digital circuit design complexities of the design complexities less than analog circuit, therefore the design complexities of the reset system in the embodiment of the present invention are relatively low.
Description
【Technical field】
The present invention relates to the control technology field that resets, more particularly to a kind of repositioning method, reset signal output circuit and multiple
Position system.
【Background technology】
In the prior art, phase-locked loop circuit is resetted using the reset circuit being made up of analog circuit, the reset
Circuit include band-gap reference circuit and comparator circuit, due to band-gap reference circuit and comparator circuit design complexities all compared with
Height, and then cause that the overall design complexities of the reset circuit are higher.
【The content of the invention】
In view of this, a kind of repositioning method, reset signal output circuit and reset system are the embodiment of the invention provides, is used
To solve the problems, such as that the overall design complexities of reset circuit are higher in the prior art.
In a first aspect, a kind of reset system is the embodiment of the invention provides, including：
Reset signal output circuit, the first input end of the reset signal output circuit is connected with the first power supply, described
Second input of reset signal output circuit is connected with second source；
Two input nor gate logic chips, the input of the two inputs nor gate logic chip is defeated with the reset signal
Go out the output end connection of circuit, the output end of the two inputs nor gate logic chip with treat reset circuit and be connected.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, first electricity
Include two stages when source and the second source are to the reset signal output circuit output voltage, wherein, the first stage is
To the reset signal output circuit output voltage, second stage is first power supply and second electricity to first power supply
Source is respectively to the reset signal output circuit output voltage；Or, the first stage is that the second source is believed to described reset
Number output circuit output voltage, second stage is that first power supply and the second source are exported to the reset signal respectively
Circuit output voltage.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, the reset letter
Number output circuit includes：First reset signal output circuit and the second reset signal output circuit；
The first input end of the first reset signal output circuit is connected with first power supply, and described first resets believes
Second input of number output circuit is connected with the second source, the output end of the first reset signal output circuit and institute
State the first input end connection of two input nor gate logic chips；
The first input end of the second reset signal output circuit is connected with first power supply, and described second resets believes
Second input of number output circuit is connected with the second source, the output end of the second reset signal output circuit and institute
State the second input connection of two input nor gate logic chips.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, when described first
Stage be first power supply to the reset signal output circuit output voltage, the second stage be first power supply and
The second source respectively to the reset signal output circuit output voltage when, the first reset signal output circuit output
Voltage signal be followed successively by：Low level voltage signal-high level voltage signal-low level voltage signal, described second resets believes
Number output circuit persistently exports low level voltage signal；
When the first stage be the second source to the reset signal output circuit output voltage, the second-order
Section for first power supply and the second source respectively to the reset signal output circuit output voltage when, described first answers
Position signal output apparatus persistently export low level voltage signal, the voltage signal of the second reset signal output circuit output according to
It is secondary to be：High level voltage signal-low level voltage signal.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, first electricity
Output voltage of the output voltage in source more than the second source.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, first electricity
The output voltage in source is in 3.1V, 3.3V and 3.5V；
The output voltage of the second source is one in 1.14V, 1.2V, 1.26V, 1.32V and 1.4V.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, described first answers
Position signal output apparatus, including：First power on detection circuit, Schmidt trigger, the first opposite device and level translator；
The first input end of first power on detection circuit is connected with first power supply, electro-detection electricity on described first
Second input on road is connected with the second source；
The first input end of the Schmidt trigger is connected with first power supply, and the second of the Schmidt trigger
Input is connected with the output end of the first power on detection circuit；
The first input end of the first opposite device is connected with first power supply, the second input of the first opposite device
End is connected with the output end of the Schmidt trigger；
The first input end of the level translator is connected with the second source, the second input of the level translator
The output end connection of end device opposite with described first, the output end of the level translator and described two input nor gate logic cores
The first input end connection of piece.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, when described first
Stage be first power supply to the reset signal output circuit output voltage when, and first power supply output voltage it is steady
After fixed, the first power on detection circuit output high level voltage signal, the Schmidt trigger output low level voltage letter
Number, the first opposite device output high level voltage signal, the level translator exports low level voltage signal；
When the second stage is first power supply and the second source respectively to the reset signal output circuit
During output voltage, during the second source draws high voltage, and second source output voltage be not up to it is described
Before the blanking voltage of the first power on detection circuit, the first power on detection circuit output high level voltage signal is described to apply
Schmitt trigger exports low level voltage signal, the first opposite device output high level voltage signal, the level translator
Output high level voltage signal；The blanking voltage of first power on detection circuit is reached in the voltage of second source output
Afterwards, the first power on detection circuit output low level voltage signal, the Schmidt trigger output high level voltage letter
Number, the first opposite device output low level voltage signal, the level translator exports low level voltage signal.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, when described first
When the output voltage of power supply is 3.1V, the blanking voltage of first power on detection circuit is 0.72V~0.93V；
When the output voltage of first power supply is 3.3V, the blanking voltage of first power on detection circuit is
0.74V~0.95V；
When the output voltage of first power supply is 3.5V, the blanking voltage of first power on detection circuit is
0.77V~0.98V.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, described second answers
Position signal output apparatus include：Second power on detection circuit and the second opposite device；
The first input end of second power on detection circuit is connected with first power supply, electro-detection electricity on described second
Second input on road is connected with the second source；
The first input end of the second opposite device is connected with the second source, the second input of the second opposite device
End is connected with the output end of second power on detection circuit, and the output end of the second opposite device and described two is input into nor gates
The second input connection of logic chip.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, when described first
Stage be the second source to the reset signal output circuit output voltage when, and the second source output voltage it is steady
After fixed, second power on detection circuit exports low level voltage signal, the second opposite device output high level voltage signal；
When the second stage is first power supply and the second source respectively to the reset signal output circuit
During output voltage, during first power supply draws high voltage, and first power supply output voltage be not up to it is described
Before the blanking voltage of the second power on detection circuit, second power on detection circuit exports low level voltage signal, and described the
Two opposite device output high level voltage signals；Second power on detection circuit is reached in the voltage of first power supply output
After blanking voltage, the second power on detection circuit output high level voltage signal, the second opposite device output low level
Voltage signal.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, when described second
When the output voltage of power supply is 1.14V, the blanking voltage of second power on detection circuit is 2.18V~2.4V；
When the output voltage of the second source is 1.2V, the blanking voltage of second power on detection circuit is
2.28V~2.5V；
When the output voltage of the second source is 1.26V, the blanking voltage of second power on detection circuit is
2.39V~2.63V；
When the output voltage of the second source is 1.32V, the blanking voltage of second power on detection circuit is
2.49V~2.75V；
When the output voltage of the second source is 1.4V, the blanking voltage of second power on detection circuit is
2.64V~2.91V.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, it is described to wait to reset
Circuit includes phase-locked loop circuit.
A technical scheme in above-mentioned technical proposal has the advantages that：
In embodiments of the present invention, reset system is by reset signal output circuit and two input nor gate logic chip structures
Into, wherein, the first input end of the reset signal output circuit is connected with the first power supply, the reset signal output circuit
Second input is connected with second source, and the input of the two inputs nor gate logic chip exports electricity with the reset signal
The output end connection on road, the output end of the two inputs nor gate logic chip with treat reset circuit and be connected, the first power supply with
After second source is to reset signal output circuit input voltage, reset signal output circuit can be to two input nor gate logic cores
Piece is input into reset signal, and two input nor gate logic chips can treat that reset circuit is carried out according to the reset signal control for receiving
Reset.Because the reset system in the embodiment of the present invention is made up of digital circuit, and the design complexities of digital circuit are less than mould
Intend the design complexities of circuit, therefore the design complexities of the reset system in the embodiment of the present invention are relatively low.
Second aspect, the embodiment of the invention provides a kind of reset signal output circuit, be applied to above-mentioned reset system
In, including：
First reset signal output circuit, the first input end of the first reset signal output circuit and the first power supply connect
Connect, the second input of the first reset signal output circuit is connected with second source, the first reset signal output electricity
The output end on road is connected with the first input end of two input nor gate logic chips；
Second reset signal output circuit, the first input end of the second reset signal output circuit and the first power supply connect
Connect, the second input of the second reset signal output circuit is connected with second source, the second reset signal output electricity
The output end on road is connected with the second input of described two input nor gate logic chips.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, first electricity
Include two stages when source and the second source are to the reset signal output circuit output voltage, wherein, the first stage is
To the reset signal output circuit output voltage, second stage is first power supply and second electricity to first power supply
Source is respectively to the reset signal output circuit output voltage；Or, the first stage is that the second source is believed to described reset
Number output circuit output voltage, second stage is that first power supply and the second source are exported to the reset signal respectively
Circuit output voltage.
Aspect as described above and any possible implementation, it is further provided a kind of implementation, when described first
Stage be first power supply to the reset signal output circuit output voltage, the second stage be first power supply and
The second source respectively to the reset signal output circuit output voltage when, the first reset signal output circuit output
Voltage signal be followed successively by：Low level voltage signal-high level voltage signal-low level voltage signal, described second resets believes
Number output circuit persistently exports low level voltage signal；
When the first stage be the second source to the reset signal output circuit output voltage, the second-order
Section for first power supply and the second source respectively to the reset signal output circuit output voltage when, described first answers
Position signal output apparatus persistently export low level voltage signal, the voltage signal of the second reset signal output circuit output according to
It is secondary to be：High level voltage signal-low level voltage signal.
A technical scheme in above-mentioned technical proposal has the advantages that：
In embodiments of the present invention, reset signal output circuit includes the first reset signal output circuit and the second reset letter
Number output circuit, wherein, the second input of the first reset signal output circuit is connected with second source, and described first answers
The output end of position signal output apparatus is connected with the first input end of two input nor gate logic chips, second reset signal
The first input end of output circuit is connected with the first power supply, second input and second of the second reset signal output circuit
Power supply is connected, and the output end of the second reset signal output circuit is input into the second of described two input nor gate logic chips
End connection, because the first reset signal output circuit and the second reset signal output circuit are all input into nor gate logic chips with two
Connection, after the first power supply and second source output voltage, the first reset signal output circuit and the output of the second reset signal are electric
Road can be to two input nor gate logic chips input reset signals, so that two input nor gate logic chips are according to receiving
Reset signal control circuit downstream is resetted.Due in the embodiment of the present invention, constituting the electricity that control circuit downstream is resetted
Route digital circuit is constituted, and digital circuit design complexities of the design complexities less than analog circuit, therefore the present invention is real
Apply constitute in example the circuit that control circuit downstream is resetted design complexities it is relatively low.
The third aspect, the embodiment of the invention provides a kind of repositioning method, be applied in above-mentioned reset system, including：
When the first stage be first power supply to the reset signal output circuit output voltage when, and described the
After the voltage stabilization of one power supply output, the first power on detection circuit output high level voltage signal, high level voltage letter
Number with first power supply export voltage stabilization after voltage signal it is identical；Schmidt trigger output voltage is the low electricity of 0V
Flat voltage signal；First opposite device output high level voltage signal, electro-detection electricity on the high level voltage signal and described first
The high level voltage signal of road output is identical；The level translator output voltage is the low level voltage signal of 0V；On second
Power detection circuit output high level voltage signal, after the voltage stabilization that the high level voltage signal is exported with first power supply
Voltage signal is identical；Second opposite device output voltage is the low level voltage signal of 0V；Connect in two input nor gate logic chips
After receiving two low level voltage signals, the corresponding logical signal of output high level signal, phase-locked loop circuit does not reset；
When the second stage is first power supply and the second source respectively to the reset signal output circuit
During output voltage, during the second source draws high voltage, and second source output voltage be not up to it is described
Before the blanking voltage of the first power on detection circuit, the first power on detection circuit output high level voltage signal, height electricity
Flat voltage signal is identical with the voltage signal after the voltage stabilization that first power supply is exported；The Schmidt trigger output electricity
Press the low level voltage signal for 0V；The first opposite device output high level voltage signal, the high level voltage signal and institute
The high level voltage signal for stating the output of the first power on detection circuit is identical；The output high level voltage letter of the level translator
Number, the high level voltage signal and the second source to draw high voltage identical；The second power on detection circuit output electricity high
Flat voltage signal, the high level voltage signal is identical with the voltage signal after the voltage stabilization that first power supply is exported；It is described
Second opposite device output voltage is the low level voltage signal of 0V；Described two input nor gate logic chips receive one it is low
After level voltage signal and a high level voltage signal, the corresponding logical signal of output low level signal, phase-locked loop circuit is multiple
Position；
After the voltage of second source output reaches the blanking voltage of first power on detection circuit, described the
One power on detection circuit output voltage is the low level voltage signal of 0V；The Schmidt trigger output high level voltage letter
Number, the high level voltage signal is identical with the voltage signal after the voltage stabilization that first power supply is exported；Described first is opposite
Device output voltage is the low level voltage signal of 0V；The level translator output voltage is the low level voltage signal of 0V；Institute
State the second power on detection circuit output high level voltage signal, the voltage that the high level voltage signal is exported with first power supply
Voltage signal after stabilization is identical；The second opposite device output voltage is the low level voltage signal of 0V；In described two inputs
After nor gate logic chip receives two low level voltage signals, the corresponding logical signal of output high level signal, phaselocked loop
Circuit exits reset.
Fourth aspect, the embodiment of the invention provides a kind of repositioning method, be applied in above-mentioned reset system, including：
When the first stage be the second source to the reset signal output circuit output voltage when, and described the
After the voltage stabilization of two power supplys output, the second power on detection circuit output voltage is the low level voltage signal of 0V；Second
Opposite device output voltage is the high level voltage signal of 1.2V；First power on detection circuit output voltage is the low level voltage of 0V
Signal；Schmidt trigger output high level voltage signal, the voltage that the high level voltage signal is exported with the second source
Voltage signal after stabilization is identical；First opposite device output voltage is the low level voltage signal of 0V；Level translator output electricity
Press the low level voltage signal for 0V；A low level voltage signal is received in two input nor gate logic chips and one high
After level voltage signal, the corresponding logical signal of output low level signal, phase-locked loop circuit resets；
When the second stage is first power supply and the second source respectively to the reset signal output circuit
During output voltage, during first power supply draws high voltage, and first power supply output voltage be not up to it is described
Before the blanking voltage of the second power on detection circuit, the second power on detection circuit output voltage is believed for the low level voltage of 0V
Number；The second opposite device output voltage is the high level voltage signal of 1.2V；The first power on detection circuit output voltage
It is the low level voltage signal of 0V；The Schmidt trigger output high level voltage signal, the high level voltage signal and institute
State the first power supply to draw high voltage identical；The first opposite device output voltage is the low level voltage signal of 0V；The level
Converter output voltage is the low level voltage signal of 0V；A low level voltage is received in two input nor gate logic chips
After signal and a high level voltage signal, the corresponding logical signal of output low level signal, phase-locked loop circuit lasts for reset；
After the voltage of first power supply output reaches the blanking voltage of second power on detection circuit, described the
Two power on detection circuit output high level voltage signals, the corresponding voltage of high level voltage signal between 0.8V~3.3V it
Between；Voltage described in the second opposite device is the low level voltage signal of 0V；The first power on detection circuit output voltage is
The low level voltage signal of 0V；The Schmidt trigger output high level voltage signal, the high level voltage signal with it is described
First power supply to draw high voltage identical；The first opposite device output voltage is the low level voltage signal of 0V；The level turns
Parallel operation output voltage is the low level voltage signal of 0V；Two low level voltage letters are received in two input nor gate logic chips
After number, the corresponding logical signal of output high level signal, phase-locked loop circuit exits reset.
【Brief description of the drawings】
Technical scheme in order to illustrate more clearly the embodiments of the present invention, below will be attached to what is used needed for embodiment
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this area
For those of ordinary skill, without having to pay creative labor, can also obtain other attached according to these accompanying drawings
Figure.
Fig. 1 is a kind of structural representation of reset system provided in an embodiment of the present invention；
Fig. 2 is the structural representation of another reset system provided in an embodiment of the present invention；
Fig. 3 is a kind of structural representation of first reset signal output circuit provided in an embodiment of the present invention；
Fig. 4 is a kind of first power on detection circuit provided in an embodiment of the present invention, Schmidt trigger and the first opposite device
Between connection diagram；
Fig. 5 is a kind of structural representation of second reset signal output circuit provided in an embodiment of the present invention；
Fig. 6 is the connection signal between a kind of second power on detection circuit provided in an embodiment of the present invention and the second opposite device
Figure；
Fig. 7 is the structural representation of another reset system provided in an embodiment of the present invention.
【Specific embodiment】
In order to be better understood from technical scheme, the embodiment of the present invention is retouched in detail below in conjunction with the accompanying drawings
State.
It will be appreciated that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made it is all its
Its embodiment, belongs to the scope of protection of the invention.
The term for using in embodiments of the present invention is the purpose only merely for description specific embodiment, and is not intended to be limiting
The present invention." one kind ", " described " and " being somebody's turn to do " of singulative used in the embodiment of the present invention and appended claims
It is also intended to include most forms, unless context clearly shows that other implications.
It will be appreciated that though power supply and input may be described using term first, second in embodiments of the present invention,
But these power supplys and input should not necessarily be limited by these terms.These terms are only used for being distinguished from each other open power supply and input.Example
Such as, in the case where range of embodiment of the invention is not departed from, the first power supply can also be referred to as second source, similarly, second
Power supply can also be referred to as the first power supply.
Depending on linguistic context, word as used in this " if " can be construed to " ... when " or " when ...
When " or " in response to determining " or " in response to detection ".Similarly, depending on linguistic context, phrase " if it is determined that " or " if detection
(condition or event of statement) " can be construed to " when it is determined that when " or " in response to determine " or " when the detection (condition of statement
Or event) when " or " in response to detection (condition or event of statement) ".
For the design complexities of the reset circuit being made up of analog circuit in the prior art problem higher, the present invention is real
Example is applied there is provided corresponding resolving ideas：Because the design complexities of digital circuit are less than the design complexities of analog circuit, because
This constitutes reset circuit using digital circuit, to reduce design complexities.
Under the guiding of above-mentioned thinking, in embodiments of the present invention, reset system is defeated by reset signal output circuit and two
Enter nor gate logic chip composition, wherein, the first input end of the reset signal output circuit is connected with the first power supply, described
Second input of reset signal output circuit is connected with second source, it is described two input nor gate logic chip input with
The output end connection of the reset signal output circuit, described two are input into the output end of nor gate logic chip and treat reset circuit
Connection, after the first power supply and second source are to reset signal output circuit input voltage, reset signal output circuit can be to
Two input nor gate logic chip input reset signals, two input nor gate logic chips can be according to the reset signal for receiving
Control treats that reset circuit is resetted.Because the reset system in the embodiment of the present invention is made up of digital circuit, and digital circuit
Design complexities less than analog circuit design complexities, therefore the reset system in the embodiment of the present invention design complexities
It is relatively low.
Feasible implementation is described in detail below.
Embodiment one
The embodiment of the present invention provides a kind of reset system, and as shown in bold portion in Fig. 1, the reset system includes：
Reset signal output circuit 11, the first input end of the reset signal output circuit 11 connects with the first power supply 12
Connect, the second input of the reset signal output circuit 11 is connected with second source 13；
Two input nor gate logic chips 14, input and the letter that resets of the two input nor gates logic chip 14
The output end connection of number output circuit 11, the output end of the two input nor gates logic chip 14 with treat reset circuit 15 and connect
Connect.
In embodiments of the present invention, reset system is by reset signal output circuit and two input nor gate logic chip structures
Into, wherein, the first input end of the reset signal output circuit is connected with the first power supply, the reset signal output circuit
Second input is connected with second source, and the input of the two inputs nor gate logic chip exports electricity with the reset signal
The output end connection on road, the output end of the two inputs nor gate logic chip with treat reset circuit and be connected, the first power supply with
After second source is to reset signal output circuit input voltage, reset signal output circuit can be to two input nor gate logic cores
Piece is input into reset signal, and two input nor gate logic chips can treat that reset circuit is carried out according to the reset signal control for receiving
Reset.Because the reset system in the embodiment of the present invention is made up of digital circuit, and the design complexities of digital circuit are less than mould
Intend the design complexities of circuit, therefore the design complexities of the reset system in the embodiment of the present invention are relatively low.
In a feasible embodiment, first power supply 12 and the second source 13 are defeated to the reset signal
Include two stages when going out 11 output voltage of circuit, wherein, the first stage is that first power supply 12 is defeated to the reset signal
Go out the output voltage of circuit 11, second stage is that first power supply 12 and the second source 13 are defeated to the reset signal respectively
Go out the output voltage of circuit 11；Or, the first stage exports electricity for the second source 13 to the reset signal output circuit 11
Pressure, second stage is that first power supply 12 and the second source 13 export electricity to the reset signal output circuit 11 respectively
Pressure.
Specifically, the reset control in order to realize treating reset circuit 15, can be first to resetting by the first power supply 12
Reset signal output circuit in system is powered, in the mistake that the first power supply 12 is powered to the reset signal output circuit in reset system
Cheng Zhong, second source 13 is powered to the reset signal output circuit in reset system again, now the first power supply 12 and second source
13 power to the reset signal output circuit in reset system simultaneously, reset system is produced the letter that resets by above-mentioned power supply mode
Number, and the reset signal is sent to treats reset circuit 15, to control to treat that reset circuit 15 is resetted；In order to realize treating multiple
The reset control of position circuit 15, can also first be powered by second source 13 to the reset signal output circuit in reset system,
During second source 13 is powered to the reset signal output circuit in reset system, the first power supply 12 is again to reset system
In reset signal output circuit power, now the first power supply 12 and second source 13 are simultaneously to the reset signal in reset system
Output circuit is powered, and by above-mentioned power supply mode reset system can also be made to produce reset signal, and the reset signal is sent
To reset circuit 15 is treated, to control to treat that reset circuit 15 is resetted.Further, the first power supply 12 and second source 13 are to multiple
Position signal output apparatus include two stages, first stage when powering：First power supply 12 or second source 13 are first to reset signal
Output circuit 11 is powered, second stage：First power supply 12 and second source 13 are powered to reset signal output circuit 11 simultaneously, are led to
The above-mentioned two stage is spent, reset signal output circuit 11 patrols two input nor gates to the output of two input nor gate logic chip 14
The control signal that chip 14 produces reset signal is collected, be transferred to for the reset signal again by two input nor gate logic chips 14 treats multiple
Position circuit 15, makes to treat that reset circuit 15 is resetted, further, no matter the first power supply 12 and which elder generation of second source 13 to
Reset signal output circuit 11 is powered, and the first power supply 12 and second source 13 are then made again, and reset signal output circuit 11 is supplied simultaneously
Electricity, can make reset system produce reset signal so that reset system can treat reset circuit by multiple control modes
15 carry out reset control.
In a feasible embodiment, as shown in bold portion in Fig. 2, the reset signal output circuit 11 is wrapped
Include：First reset signal output circuit 111 and the second reset signal output circuit 112；The first reset signal output circuit
111 first input end is connected 12 with first power supply, the second input of the first reset signal output circuit 111 with
The second source connection 13, the output end of the first reset signal output circuit 111 and described two input nor gate logics
The first input end connection of chip 14；The first input end of the second reset signal output circuit 112 and first power supply
Connection 12, the second input of the second reset signal output circuit 112 is connected with the second source 13, and described second answers
The output end of position signal output apparatus 112 is connected with the second input of described two input nor gate logic chips 14.
In a feasible embodiment, reset system as shown in Figure 2 is the described first electricity when the first stage
To the output voltage of reset signal output circuit 11, the second stage is first power supply 12 and second electricity in source 12
Source 13 respectively to 11 output voltage of reset signal output circuit when, the first reset signal output circuit 111 output
Voltage signal is followed successively by：Low level voltage signal-high level voltage signal-low level voltage signal, second reset signal
Output circuit 112 persistently exports low level voltage signal；It is that the second source 13 is believed to described reset when the first stage
Number output voltage of output circuit 11, the second stage is first power supply 12 and the second source 13 respectively to described multiple
During 11 output voltage of signal output apparatus of position, the first reset signal output circuit 111 persistently exports low level voltage signal,
The voltage signal of the output of the second reset signal output circuit 121 is followed successively by：High level voltage signal-low level voltage letter
Number.
Specifically, the logic function of two input nor gate logic chips 14 is：When at least one high level voltage signal
When input two is input into nor gate logic chip 14, two input nor gate logic chips 14 export low level signal, when input two is defeated
When the signal for entering nor gate logic chip 14 is all low level voltage signal, two input nor gate logic chips 14 export high level
Signal, wherein, the low level signal of the output of two input nor gate logic chip 14 is reset signal, now treats that reset circuit 15 enters
Enter reset state or keep reset state；The high level signal of the output of two input nor gate logic chip 14 is working signal, this
When treat that reset circuit 15 keeps working condition or exiting reset state.Therefore above-mentioned power supply mode can make two input nor gates
Logic chip 14 produces two kinds of signal output patterns, when the voltage signal of the output of the first reset signal output circuit 111 is followed successively by：
Low level voltage signal-high level voltage signal-low level voltage signal, the lasting output of the second reset signal output circuit 112
The first signal output pattern of correspondence during low level voltage signal：Working signal-reset signal-working signal, now waits to reset
The corresponding state of circuit 15 is：Keep working condition-into reset state-exit reset state；When the output of the first reset signal
Circuit 111 persistently exports low level voltage signal, and the voltage signal of the output of the second reset signal output circuit 112 is followed successively by：It is high
Second signal output pattern of correspondence during level voltage signal-low level voltage signal：Reset signal-working signal, now treats
The corresponding state of reset circuit 15 is：Into reset state-exit reset state.Further, in the base of above-mentioned reset system
On plinth, power supply mode can be according to the actual requirements selected, but no matter can make to treat reset circuit using which kind of power supply mode
15 are resetted.
In a feasible embodiment, the output voltage of the output voltage more than second source 13 of the first power supply 12.
In a feasible embodiment, the output voltage of the first power supply 12 can be in 3.1V, 3.3V and 3.5V
One；The output voltage of second source 13 can be for one in 1.14V, 1.2V, 1.26V, 1.32V and 1.4V.
On the basis of above-mentioned feasible embodiment, realized such as Fig. 3 shown in part, the first reset signal output electricity
Road 111, including：First power on detection circuit 1111, Schmidt trigger 1112, the first opposite device 1113 and level translator
1114；The first input end of first power on detection circuit 1111 is connected with first power supply 12, electric-examination on described first
Second input of slowdown monitoring circuit 1111 is connected with the second source 13；The first input end of the Schmidt trigger 1112 with
First power supply 12 is connected, and the second input of the Schmidt trigger 1112 is defeated with the first power on detection circuit 1111
Go out end connection；The first input end of the first opposite device 1113 is connected with first power supply 12, the first opposite device
1113 the second input is connected with the output end of the Schmidt trigger 1112；The first of the level translator 1114 is defeated
Enter end to be connected with the second source 13, the second input device 1113 opposite with described first of the level translator 1114
Output end is connected, the first input end that the output end of the level translator 1114 is input into nor gate logic chips 14 with described two
Connection.
In a feasible embodiment, the first power on detection circuit 1111 can be equivalent to weak opposite of strong N of P
Device.
In a specific embodiment, as shown in figure 4, on first in above-mentioned first reset signal output circuit 111
The circuit diagram of power detection circuit 1111, the opposite device 1113 of Schmidt trigger 1112 and first, and its between annexation can
With reference to Fig. 4.
In a specific embodiment, a kind of working method of above-mentioned reset system is：It is when the first stage
When first power supply 12 is to 11 output voltage of reset signal output circuit, and the voltage of first power supply 12 output is steady
After fixed, the output high level voltage signal of first power on detection circuit 1111, the Schmidt trigger 1112 exports low electricity
Flat voltage signal, the output high level voltage signal of the first opposite device 1113, the output low level of the level translator 1114
Voltage signal；When the second stage is that first power supply 12 and the second source 13 are exported to the reset signal respectively
During 11 output voltage of circuit, during the second source 13 draws high voltage, and the voltage that the second source 13 is exported
Before the blanking voltage of not up to described first power on detection circuit 1111, first power on detection circuit 1111 exports electricity high
Flat voltage signal, the output low level voltage signal of the Schmidt trigger 1112, the first opposite device 1113 exports electricity high
Flat voltage signal, the output high level voltage signal of the level translator 1114；Reached in the voltage of the output of the second source 13
To after the blanking voltage of first power on detection circuit 1111, the output of the first power on detection circuit 1111 low level electricity
Pressure signal, the output high level voltage signal of the Schmidt trigger 1112, the output of the first opposite device 1113 low level electricity
Pressure signal, the output low level voltage signal of the level translator 1114.
Specifically, in foregoing circuit the effect of the first power on detection circuit 1111 be detection second source 13 whether reach it is tactile
Generate electricity pressure；The effect of Schmidt trigger 1112 includes two aspects, and first aspect is the waveform for changing output, makes the waveform of output
Just precipitous, second aspect is to improve circuit anti-noise ability；The effect of the first opposite device 1113 is to change phase；Level translator
1114 effect is that the level signal of the output of the first opposite device 1113 is converted into the corresponding level letter of the output voltage of second source 12
Number, and kernel circuitry is delivered to, to avoid kernel circuitry from being suffered damage because of high pressure.
In a specific embodiment, when the output voltage of first power supply 12 is 3.1V, on described first
The blanking voltage of power detection circuit 1111 is 0.72V~0.93V；When the output voltage of first power supply 12 is 3.3V, institute
The blanking voltage for stating the first power on detection circuit 1111 is 0.74V~0.95V；When the output voltage of first power supply 12 is
During 3.5V, the blanking voltage of first power on detection circuit 1111 is 0.77V~0.98V.
It is shown as shown in bold portion in Fig. 5 in a feasible embodiment, the second reset signal output electricity
Road 112 includes：Second power on detection circuit 1121 and the second opposite device 1122；The first of second power on detection circuit 1121
Input is connected with first power supply 12, the second input and the second source of second power on detection circuit 1121
13 connections；The first input end of the second opposite device 1122 is connected with the second source 13, the second opposite device 1122
The second input be connected with the output end of second power on detection circuit 1121, the output end of the second opposite device 1122
The second input with described two input nor gate logic chips 14 is connected.
In a specific embodiment, as shown in fig. 6, on second in above-mentioned second reset signal output circuit 112
The circuit diagram of the opposite device 1122 of power detection circuit 1121 and second, and its between annexation refer to Fig. 6.
In a specific embodiment, another working method of above-mentioned reset system is：When the first stage
During for the second source 13 to 11 output voltage of reset signal output circuit, and the voltage that the second source 13 is exported
After stabilization, second power on detection circuit 1121 exports low level voltage signal, and the second opposite device 1122 exports electricity high
Flat voltage signal；When the second stage is that first power supply 12 and the second source 13 are defeated to the reset signal respectively
When going out 11 output voltage of circuit, during first power supply 12 draws high voltage, and the electricity that first power supply 12 is exported
Before pressure is not up to the blanking voltage of second power on detection circuit 1121, second power on detection circuit 1121 exports low
Level voltage signal, the output high level voltage signal of the second opposite device 1122；In the voltage of first power supply 12 output
Reach after the blanking voltage of second power on detection circuit 1121, second power on detection circuit 1121 exports high level
Voltage signal, the second opposite device 1122 exports low level voltage signal.
Specifically, the second power on detection circuit 1121 detects whether the first power supply 12 reaches trigger voltage in foregoing circuit,
The effect of the second opposite device 1122 includes two aspects, and to be to carry out phase inverse processing to input signal, second aspect is first aspect
The level signal that second opposite device 1122 is exported is converted into the corresponding level signal of the output voltage of second source 12, and is delivered to interior
Nuclear power road, to avoid kernel circuitry from being suffered damage because of high pressure.
In a specific embodiment, when the output voltage of the second source 13 is 1.14V, on described second
The blanking voltage of power detection circuit 1121 is 2.18V~2.4V；It is described when the output voltage of the second source 13 is 1.2V
The blanking voltage of the second power on detection circuit 1121 is 2.28V~2.5V；When the output voltage of the second source 13 is 1.26V
When, the blanking voltage of second power on detection circuit 1121 is 2.39V~2.63V；When the output electricity of the second source 13
Press during for 1.32V, the blanking voltage of second power on detection circuit 1121 is 2.49V~2.75V；When the second source 13
Output voltage when being 1.4V, the blanking voltage of second power on detection circuit 1121 is 2.64V~2.91V.
It is described to treat that reset circuit 15 includes phase-locked loop circuit in a specific embodiment.
Embodiment two
On the basis of embodiment one, the embodiment of the present invention provides a kind of reset signal output circuit, as shown in Fig. 2 should
For in above-mentioned reset system, the reset signal output circuit to include：
First reset signal output circuit 111, the first input end and first of the first reset signal output circuit 111
Power supply 12 is connected, and the second input of the first reset signal output circuit 111 is connected with second source 13, and described first answers
The output end of position signal output apparatus 111 is connected with the first input end of two input nor gate logic chips 14；
Second reset signal output circuit 112, the first input end and first of the second reset signal output circuit 112
Power supply 12 is connected, and the second input of the second reset signal output circuit 112 is connected with second source 13, and described second answers
The output end of position signal output apparatus 112 is connected with the second input of described two input nor gate logic chips 14.
In embodiments of the present invention, reset signal output circuit includes the first reset signal output circuit and the second reset letter
Number output circuit, wherein, the second input of the first reset signal output circuit is connected with second source, and described first answers
The output end of position signal output apparatus is connected with the first input end of two input nor gate logic chips, second reset signal
The first input end of output circuit is connected with the first power supply, second input and second of the second reset signal output circuit
Power supply is connected, and the output end of the second reset signal output circuit is input into the second of described two input nor gate logic chips
End connection, because the first reset signal output circuit and the second reset signal output circuit are all input into nor gate logic chips with two
Connection, after the first power supply and second source output voltage, the first reset signal output circuit and the output of the second reset signal are electric
Road can be to two input nor gate logic chips input reset signals, so that two input nor gate logic chips are according to receiving
Reset signal control circuit downstream is resetted.Due in the embodiment of the present invention, constituting the electricity that control circuit downstream is resetted
Route digital circuit is constituted, and digital circuit design complexities of the design complexities less than analog circuit, therefore the present invention is real
Apply constitute in example the circuit that control circuit downstream is resetted design complexities it is relatively low.
In a feasible embodiment, first power supply 12 and the second source 13 are defeated to the reset signal
Include two stages when going out 11 output voltage of circuit, wherein, the first stage is that first power supply 12 is defeated to the reset signal
Go out the output voltage of circuit 11, second stage is that first power supply 12 and the second source 13 are defeated to the reset signal respectively
Go out the output voltage of circuit 11；Or, the first stage exports electricity for the second source 13 to the reset signal output circuit 11
Pressure, second stage is that first power supply 12 and the second source 13 export electricity to the reset signal output circuit 11 respectively
Pressure.
On the basis of above-mentioned feasible embodiment, when the first stage be first power supply 12 to the reset
The output voltage of signal output apparatus 11, the second stage is first power supply 12 and the second source 13 respectively to described
During reset signal 11 output voltage of output circuit, the voltage signal of the output of the first reset signal output circuit 111 is followed successively by：
Low level voltage signal-high level voltage signal-low level voltage signal, the second reset signal output circuit 112 continues
Output low level voltage signal；When the first stage for the second source 13 is exported to the reset signal output circuit 11
Voltage, the second stage is first power supply 12 and the second source 13 respectively to the reset signal output circuit 11
During output voltage, the first reset signal output circuit 111 persistently exports low level voltage signal, second reset signal
The voltage signal of the output of output circuit 112 is followed successively by：High level voltage signal-low level voltage signal.
In the embodiment of the present invention, explaining in detail referring to embodiment one on reset signal output circuit 11, herein no longer
It is described in detail.
Embodiment three
On the basis of embodiment one, reset system as shown in Figure 7, the embodiment of the present invention gives a kind of reset side
Method, the method is applied in above-mentioned reset system, i.e. the operation principle of the reset system, including：
When the first stage be first power supply 12 to 11 output voltage of reset signal output circuit when, and institute
After stating the voltage stabilization of the output of the first power supply 12, the output high level voltage signal of first power on detection circuit 1111, the height
Level voltage signal is identical with the voltage signal after the voltage stabilization that first power supply 12 is exported；Schmidt trigger 1112 is defeated
Go out the low level voltage signal that voltage is 0V；The output high level voltage signal of first opposite device 1113, the high level voltage signal
It is identical with the high level voltage signal that first power on detection circuit 1111 is exported；The output voltage of the level translator 1114
It is the low level voltage signal of 0V；The output high level voltage signal of second power on detection circuit 1121, the high level voltage signal
It is identical with the voltage signal after the voltage stabilization that first power supply 12 is exported；The output voltage of second opposite device 1122 is low for 0V's
Level voltage signal；After two input nor gate logic chips 14 receive two low level voltage signals, output high level letter
Number corresponding logical signal, phase-locked loop circuit 15 does not reset；
When the second stage is that first power supply 12 and the second source 13 are exported to the reset signal respectively
During 11 output voltage of circuit, during the second source 13 draws high voltage, and the voltage that the second source 13 is exported
Before the blanking voltage of not up to described first power on detection circuit 1111, first power on detection circuit 1111 exports electricity high
Flat voltage signal, the high level voltage signal is identical with the voltage signal after the voltage stabilization that first power supply 12 is exported；Institute
State the low level voltage signal that the output voltage of Schmidt trigger 1112 is 0V；The output of the first opposite device 1113 high level electricity
Pressure signal, the high level voltage signal is identical with the high level voltage signal that first power on detection circuit 1111 is exported；Institute
The output high level voltage signal of level translator 1114 is stated, the high level voltage signal draws high electricity with the second source 13
Pressure is identical；The output high level voltage signal of second power on detection circuit 1121, the high level voltage signal and described first
Voltage signal after the voltage stabilization of the output of power supply 12 is identical；The output voltage of second opposite device 1122 is the low level electricity of 0V
Pressure signal；A low level voltage signal and a high level voltage letter are received in described two input nor gate logic chips 14
After number, the corresponding logical signal of output low level signal, phase-locked loop circuit 15 resets；
After the voltage of the output of the second source 13 reaches the blanking voltage of first power on detection circuit 1111,
The output voltage of first power on detection circuit 1111 is the low level voltage signal of 0V；The Schmidt trigger 1112 is exported
High level voltage signal, the voltage signal phase after the voltage stabilization that the high level voltage signal is exported with first power supply 12
Together；The output voltage of first opposite device 1113 is the low level voltage signal of 0V；The output voltage of the level translator 1114
It is the low level voltage signal of 0V；The output high level voltage signal of second power on detection circuit 1121, the high level voltage
Signal is identical with the voltage signal after the voltage stabilization that first power supply 12 is exported；The output voltage of second opposite device 1122
It is the low level voltage signal of 0V；After described two input nor gate logic chips 14 receive two low level voltage signals,
The corresponding logical signal of output high level signal, phase-locked loop circuit 15 exits reset.
Example IV
On the basis of embodiment one, reset system as shown in Figure 7, the embodiment of the present invention gives another reset side
Method, the method is applied in above-mentioned reset system, i.e. the operation principle of the reset system, including：
When the first stage be the second source 13 to 11 output voltage of reset signal output circuit when, and institute
After stating the voltage stabilization of the output of second source 13, the output voltage of the second power on detection circuit 1121 is the low level voltage of 0V
Signal；The output voltage of second opposite device 1122 is the high level voltage signal of 1.2V；First power on detection circuit 1111 exports electricity
Press the low level voltage signal for 0V；The output high level voltage signal of Schmidt trigger 1112, the high level voltage signal with
Voltage signal after the voltage stabilization of the output of the second source 13 is identical；First opposite device defeated 1113 goes out the low electricity that voltage is 0V
Flat voltage signal；The output voltage of level translator 1114 is the low level voltage signal of 0V；Nor gate logic chip is input into two
After 14 receive a low level voltage signal and a high level voltage signal, the corresponding logic letter of output low level signal
Number, phase-locked loop circuit 15 resets；
When the second stage is that first power supply 12 and the second source 13 are exported to the reset signal respectively
During 11 output voltage of circuit, during first power supply 12 draws high voltage, and the voltage that first power supply 12 is exported
Before the blanking voltage of not up to described second power on detection circuit 1121, the output voltage of the second power on detection circuit 1121
It is the low level voltage signal of 0V；The output voltage of second opposite device 1122 is the high level voltage signal of 1.2V；Described
The output voltage of one power on detection circuit 1111 is the low level voltage signal of 0V；The Schmidt trigger 1112 exports high level
Voltage signal, the high level voltage signal and first power supply 12 to draw high voltage identical；The first opposite device 1113 is defeated
Go out the low level voltage signal that voltage is 0V；The output voltage of the level translator 1114 is the low level voltage signal of 0V；
After two input nor gate logic chips 14 receive a low level voltage signal and a high level voltage signal, low electricity is exported
The corresponding logical signal of ordinary mail number, the lasts for reset of phase-locked loop circuit 15；
After the voltage of first power supply 12 output reaches the blanking voltage of second power on detection circuit 1121,
The output high level voltage signal of second power on detection circuit 1121, the corresponding voltage of high level voltage signal is between 0.8V
Between~3.3V；Voltage described in the second opposite device 1122 is the low level voltage signal of 0V；Electro-detection electricity on described first
The output voltage of road 1111 is the low level voltage signal of 0V；The output high level voltage signal of the Schmidt trigger 1112, should
High level voltage signal and first power supply 12 to draw high voltage identical；The output voltage of first opposite device 1113 is 0V's
Low level voltage signal；The output voltage of the level translator 1114 is the low level voltage signal of 0V；Nor gate is input into two
After logic chip 14 receives two low level voltage signals, the corresponding logical signal of output high level signal, phase-locked loop circuit
15 exit reset.
It is apparent to those skilled in the art that, for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, may be referred to the corresponding process in preceding method embodiment, will not be repeated here.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Within god and principle, any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (10)
1. a kind of reset system, it is characterised in that the reset system includes：
Reset signal output circuit, the first input end of the reset signal output circuit is connected with the first power supply, the reset
Second input of signal output apparatus is connected with second source；
Two input nor gate logic chips, the input of the two inputs nor gate logic chip exports electricity with the reset signal
The output end connection on road, the output end of the two inputs nor gate logic chip with treat reset circuit and be connected.
2. reset system as claimed in claim 1, it is characterised in that
The output voltage of first power supply is in 3.1V, 3.3V and 3.5V；
The output voltage of the second source is one in 1.14V, 1.2V, 1.26V, 1.32V and 1.4V.
3. reset system as claimed in claim 2, it is characterised in that the first reset signal output circuit, including：First
Power on detection circuit, Schmidt trigger, the first opposite device and level translator；
The first input end of first power on detection circuit is connected with first power supply, first power on detection circuit
Second input is connected with the second source；
The first input end of the Schmidt trigger is connected with first power supply, the second input of the Schmidt trigger
End is connected with the output end of the first power on detection circuit；
The first input end of the first opposite device is connected with first power supply, the second input of the first opposite device with
The output end connection of the Schmidt trigger；
The first input end of the level translator is connected with the second source, the second input of the level translator with
The output end connection of the first opposite device, the output end of the level translator and described two input nor gate logic chips
First input end is connected.
4. reset system as claimed in claim 3, it is characterised in that
When the first stage be first power supply to the reset signal output circuit output voltage when, and it is described first electricity
After the voltage stabilization of source output, the first power on detection circuit output high level voltage signal, the Schmidt trigger is defeated
Go out low level voltage signal, the first opposite device output high level voltage signal, the level translator output low level electricity
Pressure signal；
When the second stage is that first power supply and the second source are exported to the reset signal output circuit respectively
During voltage, during the second source draws high voltage, and the voltage of second source output is not up to described first
Before the blanking voltage of power on detection circuit, the first power on detection circuit output high level voltage signal, the Schmidt
Trigger exports low level voltage signal, the first opposite device output high level voltage signal, the level translator output
High level voltage signal；The second source output voltage reach first power on detection circuit blanking voltage it
Afterwards, the first power on detection circuit output low level voltage signal, the Schmidt trigger output high level voltage signal,
The first opposite device output low level voltage signal, the level translator exports low level voltage signal.
5. reset system as claimed in claim 2, it is characterised in that the second reset signal output circuit includes：Second
Power on detection circuit and the second opposite device；
The first input end of second power on detection circuit is connected with first power supply, second power on detection circuit
Second input is connected with the second source；
The first input end of the second opposite device is connected with the second source, the second input of the second opposite device with
The output end connection of second power on detection circuit, the output end of the second opposite device and described two input nor gate logics
The second input connection of chip.
6. reset system as claimed in claim 5, it is characterised in that
When the first stage be the second source to the reset signal output circuit output voltage when, and it is described second electricity
After the voltage stabilization of source output, second power on detection circuit exports low level voltage signal, the second opposite device output
High level voltage signal；
When the second stage is that first power supply and the second source are exported to the reset signal output circuit respectively
During voltage, during first power supply draws high voltage, and the voltage of first power supply output is not up to described second
Before the blanking voltage of power on detection circuit, second power on detection circuit exports low level voltage signal, second phase
Anti- device output high level voltage signal；The cut-off of second power on detection circuit is reached in the voltage of first power supply output
After voltage, the second power on detection circuit output high level voltage signal, the second opposite device output low level voltage
Signal.
7. reset system as claimed in claim 1, it is characterised in that described to treat that reset circuit includes phase-locked loop circuit.
8. a kind of reset signal output circuit, it is characterised in that be applied in the reset system described in claim 1 to 7, wraps
Include：
First reset signal output circuit, the first input end of the first reset signal output circuit is connected with the first power supply,
Second input of the first reset signal output circuit is connected with second source, the first reset signal output circuit
Output end is connected with the first input end of two input nor gate logic chips；
Second reset signal output circuit, the first input end of the second reset signal output circuit is connected with the first power supply,
Second input of the second reset signal output circuit is connected with second source, the second reset signal output circuit
Output end is connected with the second input of described two input nor gate logic chips.
9. a kind of repositioning method, it is characterised in that be applied in the reset system described in claim 1 to 7, including：
When the first stage be first power supply to the reset signal output circuit output voltage when, and it is described first electricity
Source output voltage stabilization after, the first power on detection circuit output high level voltage signal, the high level voltage signal with
Voltage signal after the voltage stabilization of the first power supply output is identical；Schmidt trigger output voltage is the low level electricity of 0V
Pressure signal；First opposite device output high level voltage signal, the high level voltage signal is defeated with first power on detection circuit
The high level voltage signal for going out is identical；The level translator output voltage is the low level voltage signal of 0V；Electric-examination on second
Slowdown monitoring circuit output high level voltage signal, the voltage after the voltage stabilization that the high level voltage signal is exported with first power supply
Signal is identical；Second opposite device output voltage is the low level voltage signal of 0V；Received in two input nor gate logic chips
After two low level voltage signals, the corresponding logical signal of output high level signal, phase-locked loop circuit does not reset；
When the second stage is that first power supply and the second source are exported to the reset signal output circuit respectively
During voltage, during the second source draws high voltage, and the voltage of second source output is not up to described first
Before the blanking voltage of power on detection circuit, the first power on detection circuit output high level voltage signal, high level electricity
Pressure signal is identical with the voltage signal after the voltage stabilization that first power supply is exported；The Schmidt trigger output voltage is
The low level voltage signal of 0V；The first opposite device output high level voltage signal, the high level voltage signal and described
The high level voltage signal of one power on detection circuit output is identical；The output high level voltage signal of the level translator, should
High level voltage signal and the second source to draw high voltage identical；The second power on detection circuit output high level voltage
Signal, the high level voltage signal is identical with the voltage signal after the voltage stabilization that first power supply is exported；Second phase
Anti- device output voltage is the low level voltage signal of 0V；A low level electricity is received in described two input nor gate logic chips
After pressure signal and a high level voltage signal, the corresponding logical signal of output low level signal, phase-locked loop circuit resets；
After the voltage of second source output reaches the blanking voltage of first power on detection circuit, on described first
Power detection circuit output voltage is the low level voltage signal of 0V；The Schmidt trigger output high level voltage signal, should
High level voltage signal is identical with the voltage signal after the voltage stabilization that first power supply is exported；The first opposite device output
Voltage is the low level voltage signal of 0V；The level translator output voltage is the low level voltage signal of 0V；Described second
Power on detection circuit output high level voltage signal, after the voltage stabilization that the high level voltage signal is exported with first power supply
Voltage signal it is identical；The second opposite device output voltage is the low level voltage signal of 0V；Nor gate is input into described two
After logic chip receives two low level voltage signals, the corresponding logical signal of output high level signal, phase-locked loop circuit is moved back
Go out to reset.
10. a kind of changing method, it is characterised in that be applied in the reset system described in claim 1 to 7, including：
When the first stage be the second source to the reset signal output circuit output voltage when, and it is described second electricity
After the voltage stabilization of source output, the second power on detection circuit output voltage is the low level voltage signal of 0V；Second is opposite
Device output voltage is the high level voltage signal of 1.2V；First power on detection circuit output voltage is believed for the low level voltage of 0V
Number；Schmidt trigger output high level voltage signal, the high level voltage signal is steady with the voltage that the second source is exported
Voltage signal after fixed is identical；First opposite device output voltage is the low level voltage signal of 0V；Level translator output voltage
It is the low level voltage signal of 0V；A low level voltage signal and an electricity high are received in two input nor gate logic chips
After flat voltage signal, the corresponding logical signal of output low level signal, phase-locked loop circuit resets；
When the second stage is that first power supply and the second source are exported to the reset signal output circuit respectively
During voltage, during first power supply draws high voltage, and the voltage of first power supply output is not up to described second
Before the blanking voltage of power on detection circuit, the second power on detection circuit output voltage is the low level voltage signal of 0V；
The second opposite device output voltage is the high level voltage signal of 1.2V；The first power on detection circuit output voltage is 0V
Low level voltage signal；The Schmidt trigger output high level voltage signal, the high level voltage signal and described
One power supply to draw high voltage identical；The first opposite device output voltage is the low level voltage signal of 0V；The level conversion
Device output voltage is the low level voltage signal of 0V；A low level voltage signal is received in two input nor gate logic chips
After a high level voltage signal, the corresponding logical signal of output low level signal, phase-locked loop circuit lasts for reset；
After the voltage of first power supply output reaches the blanking voltage of second power on detection circuit, on described second
Power detection circuit output high level voltage signal, the corresponding voltage of high level voltage signal is between 0.8V~3.3V；Institute
State the low level voltage signal that voltage described in the second opposite device is 0V；The first power on detection circuit output voltage is low for 0V's
Level voltage signal；The Schmidt trigger output high level voltage signal, the high level voltage signal and the described first electricity
Source to draw high voltage identical；The first opposite device output voltage is the low level voltage signal of 0V；The level translator is defeated
Go out the low level voltage signal that voltage is 0V；After two input nor gate logic chips receive two low level voltage signals,
The corresponding logical signal of output high level signal, phase-locked loop circuit exits reset.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107634760A (en) * | 2017-09-28 | 2018-01-26 | 中国人民解放军国防科技大学 | Adaptive digital reset device for phase-locked loop |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107634760A (en) * | 2017-09-28 | 2018-01-26 | 中国人民解放军国防科技大学 | Adaptive digital reset device for phase-locked loop |
| CN107634760B (en) * | 2017-09-28 | 2020-09-11 | 中国人民解放军国防科技大学 | Adaptive digital reset device for phase-locked loop |
| CN113467591A (en) * | 2021-07-08 | 2021-10-01 | 南昌华勤电子科技有限公司 | Composite signal reset circuit, method and server |
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