CN107622956A - Possess the crystallite dimension encapsulation diode element and manufacture method of ultralow forward voltage - Google Patents
Possess the crystallite dimension encapsulation diode element and manufacture method of ultralow forward voltage Download PDFInfo
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- CN107622956A CN107622956A CN201610560122.5A CN201610560122A CN107622956A CN 107622956 A CN107622956 A CN 107622956A CN 201610560122 A CN201610560122 A CN 201610560122A CN 107622956 A CN107622956 A CN 107622956A
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Abstract
The invention discloses a kind of crystallite dimension encapsulation diode element for possessing ultralow forward voltage and its manufacture method, the diode element is directly to be used as first electrode by the use of the Zone Full beyond second electrode, and/or using perforation behind the positive back side of first electrode and conducting, the smaller crystallite dimension encapsulation diode element finished product of a volume can be formed after cleaved；Because the first electrode in the present invention need not be turned on by epitaxial layer or diffusion layer, therefore internal resistance can be avoided and reduce forward voltage, and possess many advantages, such as simplified processing procedure, lift quality, reduce cost and make diode element more compact.
Description
Technical field
The present invention relates to a kind of crystallite dimension encapsulation (Chip Scale Package, CSP) diode element and its manufacture
Method, technology contents are related to substrate (Substrate), epitaxial layer (Epitaxy), epitaxy disk (EPI Wafer), diffusion silicon wafer
Plate (Silicon Wafer), diffusion layer (Diffused), diffusion silicon wafer (Diffused Silicon Wafer).It is made
Diode element finished product possess the characteristic of ultralow forward voltage (VF), and can simplify processing procedure, lifted quality, reduce cost,
And many advantages, such as causing diode element more compact.
Background technology
General crystal covering type (Flip Chip) diode member using semi-conducting material manufacturing into crystallite dimension encapsulation (CSP)
Material used in part includes epitaxy disk (EPI Wafer) and diffusion silicon wafer (Diffused Silicon
Wafer).Wherein epitaxy disk includes one layer and is located at positive epitaxy positioned at the substrate (Substrate) at the back side and one layer
Layer (Epitaxy).And it is then to set a diffusion layer respectively at the positive and back side of one layer of silicon wafer material to spread silicon wafer
(Diffused), wherein the back portion of diffusion silicon wafer (Diffused Silicon Wafer) is defined as spreading silicon crystal slate
(Silicon Wafer), front portion are defined as diffusion layer (Diffused).
During the above-mentioned material making diode using epitaxy disk or diffusion silicon wafer etc., conventional process and step such as Fig. 1
And shown in Fig. 2, it is summarized as follows：
1st, epitaxy is utilized in the front of a substrate (Substrate) or diffusion silicon crystal slate (Silicon Wafer)
(Epitaxy) mode such as processing procedure, diffusion (Diffused) processing procedure or ion implant (Ion Implantation) make epitaxy/
Diffusion layer, to form an epitaxy disk (EPI Wafer)/(diffusion of diffusion silicon wafer (Diffused Silicon Wafer) 1
For silicon wafer if Double side diffusion, then spreading silicon wafer front and the back side all has diffusion layer).
2nd, multiple battle arrays are separated according to the specification and size of diode element, picture in the epitaxy disk/diffusion silicon wafer 1
The diode element region 2 that row mode arranges, and design in each diode element region 2 position of N poles 3 and P poles 4.
3rd, the electrical characteristic according to needed for diode element, gold-tinted, etching, ion implant or expansion are utilized on the region of N poles 3
The mode such as dissipate, make epitaxy/diffusion layer (not shown) of N poles forward conducting.
4th, the electrical characteristic according to needed for diode element, gold-tinted, etching, ion implant or diffusion etc. are utilized on P poles 4
Mode makes an electrical layer, such as：PN junctions or protection ring, Schottky energy barrier etc., and made around P poles 4 and N poles 3
Insulating protective layer 5, for N poles 3 are isolated with P poles 4.
5th, respectively in the covering surface layer of metal conductive layer of N poles 3 and P poles 4.
6th, according to the multiple diode element regions 2 separated drawn by foregoing second step, isolated using cutting mode cutting
Multiple diode element finished products for having encapsulated completion；In Fig. 2, diode element region 2 is the top view of diode element finished product.
Because the electrical characteristic of above-mentioned diode element all completes in an epitaxy disk/diffusion silicon wafer,
So that the chip core size and package dimension of each diode element are very close, therefore referred to as crystallite dimension encapsulates, can
Significantly to reduce the volume of diode element.But following deficiency is still suffered from above-mentioned processing procedure：
1st, the purpose of the epitaxy of N poles/diffusion layer script is that electronic energy passes through under relatively low internal resistance when allowing the electric current forward to turn on
The N poles polar region, but epitaxy/diffusion layer can produce extra internal resistance in itself, therefore forward voltage (VF) is still higher.
2nd, substrate or diffusion silicon crystal slate utilize the modes such as gold-tinted, etching, ion implant or diffusion on relative to N poles position
Epitaxy/diffusion layer of conducting is made, processing procedure is grown, and cost is higher.
3rd, the region beyond P, N pole is idle and not utilized because of the setting of protection ring and insulating protective layer, to forward leading
Forward voltage when logical also can be higher.
4th, Cutting Road is centered around the periphery of P poles and N poles, when element is cut, P poles and N poles while there is periphery to burst apart
(CHIPPING＆CRACK) the problem of, the quality stability of diode element finished product is had a strong impact on.
The content of the invention
It is a primary object of the present invention to provide a kind of method for improving above-mentioned processing procedure, the diode element is directly to utilize
Zone Full beyond second electrode turns on as first electrode, and/or after running through the positive back side of first electrode using perforation, through cutting
The smaller crystallite dimension encapsulation diode element finished product of a volume can be formed after cutting；And first electrode and second electrode are built jointly
Put and the smaller crystallite dimension encapsulation diode element of a volume is formed in the front of diode element.In addition, directly utilize the
Zone Full beyond two electrodes makes first electrode be turned on without epitaxial layer or diffusion layer, therefore can drop as first electrode
Low internal resistance and forward voltage simultaneously shorten processing procedure.
In order to achieve the above object, the invention provides a kind of crystallite dimension for possessing ultralow forward voltage to encapsulate diode
The manufacture method of element, it directly by the use of the Zone Full beyond second electrode as first electrode, makes first electrode without epitaxy
Layer or diffusion layer covering, this method comprise the steps of：
1st, the front of a substrate (Substrate) is divided into multiple diode element regions, each diode element region
Periphery is reserved with Cutting Road and interior enclose configures a second electrode area, and each diode element region is beyond its second electrode area
Position all as the first region.
2nd, an epitaxy platform is made on the second electrode area allocation position of above-mentioned each diode element region, makes the substrate
Zone Full in addition to epitaxy platform is all the electrical scope of the first region.
3rd, an electrical layer is made according to the electrical characteristic of diode element on foregoing epitaxy platform, such as：PN junctions or
Protection ring, energy barrier etc. are to complete the electrical making in second electrode area.
4th, the substrate surface of the first region and the electric layer surface difference floor gold of coating one in second electrode area are pointed to
After belonging to layer, cut by the Cutting Road position reserved around each diode element region.
The manufacture method for the crystallite dimension encapsulation diode element for possessing ultralow forward voltage the invention provides a kind of, its
Directly by the use of the Zone Full beyond second electrode as first electrode, first electrode is covered without epitaxial layer or diffusion layer, be somebody's turn to do
Method comprises the steps of：
1st, the front of an epitaxy disk (EPI Wafer) is divided into multiple diode element regions, each diode element
The periphery in area is reserved with Cutting Road and one second electrode area of configuration is enclosed according in, and each diode element region is in its second electrode area
Position in addition is all as the first region.
2nd, by above-mentioned each diode element region, the epitaxial layer on the first region surface all removes divided by exposed base
Plate, and the remaining epitaxial layer in second electrode area is formed an epitaxy platform, make whole areas of the substrate in addition to epitaxy platform
Domain is all the electrical scope of the first region.
3rd, on the epitaxy platform in foregoing second electrode area according to the electrical characteristic of diode element make an electrical layer with
Complete the electrical making in second electrode area.
4th, the substrate surface of the first region and the electric layer surface difference floor gold of coating one in second electrode area are pointed to
After belonging to layer, cut by the Cutting Road position reserved around each diode element region.
The manufacture method of the crystallite dimension encapsulation diode element provided by the invention for possessing ultralow forward voltage, its is direct
Zone Full beyond by the use of second electrode makes first electrode be covered without epitaxial layer or diffusion layer, this method as first electrode
Comprise the steps of：
1st, the front of an epitaxy disk (EPI Wafer) is divided into multiple diode element regions, each diode element
The periphery in area be reserved with Cutting Road and it is interior enclose configuration one second electrode area, and each diode element region second electrode area with
Outer position is all as the first region.
2nd, one will be made according to the electrical characteristic of diode element in the second electrode area of above-mentioned each diode element region
Electrical layer is to complete the electrical making in second electrode area.
3rd, the epitaxial layer that each diode element region is located to the first region surface all removes divided by exposed substrate, makes
Remaining epitaxial layer forms an epitaxy platform, and the second electrode area is built in the epitaxy platform and the electrical layer, and the base
Zone Full of the plate in addition to epitaxy platform and electrical layer is all the electrical scope of the first region.
4th, the substrate surface of the first region and the electric layer surface difference floor gold of coating one in second electrode area are pointed to
After belonging to layer, cut by the Cutting Road position reserved around each diode element region.
The invention described above because processing procedure used in base material for one be free of epitaxial layer substrate (Substrate), or
The one epitaxy disk (EPI Wafer) comprising substrate and epitaxial layer, and it is divided into three kinds of steps, but its feature is all direct profit
By the use of by the use of the Zone Full beyond second electrode as first electrode, first electrode is set to be covered without other epitaxial layers or diffusion layer,
So the characteristic with low internal resistance, along with the Zone Full beyond second electrode is all the electrical scope of first electrode, therefore
The utilization rate of first electrode can be allowed to maximize, and then diode element finished product is possessed the characteristic of ultralow forward voltage (VF).
According to the above method, the present invention provides a kind of crystallite dimension encapsulation diode element for possessing ultralow forward voltage,
Comprise at least：
One substrate, the substrate have a front and a back side；
One second electrode, include an epitaxy platform above the substrate front side, one be arranged on the epitaxy platform
Electrical layer and one set the electrical layer above metal level；And
One first electrode, it is made up of whole substrates in addition to second electrode, the first electrode further comprises one
It is coated on metal level of the substrate front side in the entire area in addition to second electrode.
During implementation, the first electrode and/or second electrode further set a Xi Tai, Er Qie in layer on surface of metal respectively
Insulating protective layer and/or groove are provided with around one electrode and/or second electrode.
A kind of manufacture method of crystallite dimension encapsulation diode element for possessing ultralow forward voltage provided by the invention, its
Directly by the use of the Zone Full beyond second electrode as first electrode, and led after being perforated at the positive back side of the first region
It is logical, first electrode is turned on without using epitaxial layer or diffusion layer, this method comprises the steps of：
1st, by the front of an epitaxy disk (EPI Wafer)/diffusion silicon wafer (Diffused Silicon Wafer)
Multiple diode element regions are divided into, the periphery of each diode element region is reserved with Cutting Road and the electricity of configuration one second is enclosed according in
Polar region, and position of each diode element region beyond its second electrode area is all as the first region.
2nd, one will be made according to the electrical characteristic of diode element in the second electrode area of above-mentioned each diode element region
Electrical layer is to complete the electrical making in second electrode area.
3rd, done in the first region through the front of epitaxy disk/diffusion silicon wafer and the perforation at the back side, and
Metallic conduction material is inserted in perforation and forms a conductive channel.
4th, the surface of the first region and the electric layer surface difference coating layer of metal floor in second electrode area are pointed to,
The metal level and the conductive channel for making the first region electrically conduct, and are cut afterwards by what is reserved around each diode element region
Position is cut to be cut.
According to the above method, the present invention provides a kind of crystallite dimension encapsulation diode element for possessing ultralow forward voltage,
Comprise at least：
The one diode element body cut out by epitaxy disk/diffusion silicon wafer, the diode element body
It is located at positive epitaxy/diffusion layer positioned at the substrate/diffusion silicon crystal slate at the back side and one layer comprising one layer；
One second electrode, include an electrical layer on epitaxy/diffusion layer and one and gold above the electrical layer is set
Belong to layer；And
One first electrode, it is coated on comprising one in the entire area above the epitaxy/diffusion layer in addition to second electrode
Metal level and one wearing for positive epitaxy/diffusion layer is extended through by the diode element body back substrate/diffusion silicon crystal slate
Hole, the perforation is interior to electrically conduct filled with conductive materials and the metal level of the first electrode and forms a conductive channel.
During implementation, the first electrode and/or second electrode further set a Xi Tai, Er Qie in layer on surface of metal respectively
Insulating protective layer and/or groove are provided with around one electrode and/or second electrode.
Compared to prior art, the present invention has following advantages on processing procedure and electrical characteristic：
If the 1st, diode element finished product with a substrate as a diode element first electrode, because first electrode is without other
Epitaxial layer or diffusion layer covering, so low internal resistance, and first electrode utilization rate is maximized, therefore when diode element finished product turns on
When can further reduce the forward voltage (VF) of element.
If the 2, through epitaxy disk/diffusion silicon wafer and filling conductive materials to form a conductive channel using perforation,
First electrode is set directly to be electrically conducted front and the back side by the conductive channel, without by epitaxial layer or diffusion layer, because
This can allow the forward voltage of diode element finished product further to reduce.
3rd, because the Zone Full in addition to second electrode area is all the electrical scope of first electrode, therefore Cutting Road is made
Positioned at the surrounding of the first electrode, the electricity of second electrode is not interfered with yet even if corner is burst apart during cutting (Chipping＆Crack)
Gas characteristic, make the electrical characteristic of diode element finished product more stable.
Based on the following the technological means of the present invention, include suitable for embodiments of the present invention, and coordinate schema explanation such as
Afterwards：
Brief description of the drawings
Fig. 1 is that conventional art draws epitaxy disk/diffusion silicon wafer in the schematic diagram for separating multiple diode element blocks；
Fig. 2 is the position signal that each diode element block is divided into first electrode and second electrode by conventional art
Figure；
Fig. 3 is that first embodiment of the invention draws a substrate front side in the schematic diagram for separating multiple diode element regions；
Fig. 4 is the schematic diagram that first embodiment of the invention makes epitaxy platform in second electrode area；
Fig. 5 is the schematic diagram that first embodiment of the invention makes electrical layer in second electrode area；
Fig. 6 is that electric layer surface of the first embodiment of the invention in the first region surface and second electrode area is draped over one's shoulders respectively
Cover the schematic diagram cut after layer of metal layer；
Fig. 7 is the structure sectional view of first embodiment of the invention diode element finished product；
Fig. 8 is the top view of first embodiment of the invention diode element finished product；
Fig. 9 is that first embodiment of the invention sets Xi Tai, protection ring, the structural representation of insulating protective layer；
Figure 10 is the structural representation that first embodiment of the invention sets groove；
Figure 11 is that second embodiment of the invention will be divided into multiple diode element regions on the front of an epitaxy disk, and often
One diode element region configures the first region and the schematic diagram in second electrode area；
Figure 12 is the schematic diagram that second embodiment of the invention all removes the epitaxial layer of the first region；
Figure 13 is the schematic diagram for the electrical making that second embodiment of the invention completes second electrode area；
Figure 14 is that second embodiment of the invention is distinguished in the electric layer surface in the first region surface and second electrode area
The schematic diagram cut after coating layer of metal layer；
Figure 15 is that third embodiment of the invention will be divided into multiple diode element regions on the front of an epitaxy disk, and often
One diode element region configures the first region and the schematic diagram in second electrode area；
Figure 16 is the schematic diagram for the electrical making that third embodiment of the invention completes second electrode area；
Figure 17 is third embodiment of the invention by the epitaxy beyond the second electrode allocation position of each diode element region
The schematic diagram that layer all removes；
Figure 18 is after the electric layer surface in the first region surface and second electrode area distinguishes coating layer of metal floor
The schematic diagram cut afterwards；
Figure 19 is that fourth embodiment of the invention will be divided into multiple two poles on the front of an epitaxy disk/diffusion silicon wafer
Tube elements area, and each diode element region configuration the first region and the schematic diagram in second electrode area；
Figure 20 is the schematic diagram for the electrical making that fourth embodiment of the invention completes second electrode area；
Figure 21 is the schematic diagram that fourth embodiment of the invention makes conductive channel；
Figure 22 is that fourth embodiment of the invention makes the schematic diagram cut after metal level；
Figure 23 is the diode element structural representation that fourth embodiment of the invention completes；
Figure 24 is to utilize positive-negative-positive center tapped full-wave rectifier schematic diagram made of the present invention.
Description of reference numerals：100a, 100b- epitaxy disk；100c- epitaxies disk/diffusion silicon wafer；10、10a、
10b- substrates；10c- substrates/diffusion silicon crystal slate；11st, 11a, 11b, 11c- Cutting Road；12c- perforates；13c- conductive materials；20、
20a, 20b, 20c- diode element region；30th, 30a, 30b, 30c- the first region；31c- conductive channels；40、40a、40b、
40c- second electrodes area；41st, 41a, 41b- epitaxy platform；41c- epitaxies/diffusion layer；42nd, 42a, 42b, 42c- electrical layer；51、
51a, 51b, 51c- metal level；52- Xi Tai；53- protection rings；54- insulating protective layers；55- grooves；D, D1- diode elements；N、
N1- first electrodes；P, P1- second electrodes.
Embodiment
For purposes of illustration only, following examples, based on N-type substrate or silicon wafer, the invention provides one kind to possess
The manufacture method of the crystallite dimension encapsulation diode element of ultralow forward voltage, its first embodiment comprise the steps of：
First step：As shown in figure 3, in the front of a substrate 10, the specification division according to needed for diode element
For multiple diode element regions 20, the periphery of each diode element region 20 is reserved with Cutting Road 11, and in each diode
Configuration the first region 30 and second electrode area 40 are enclosed in element region 20；Wherein, the diode element region 20 is in second electrode
Position beyond area 40 is all as the first region 30.
Second step：As shown in figure 4, on the allocation position of second electrode area 40 of above-mentioned each diode element region 20,
An epitaxy platform 41 is made using epitaxial growth process, makes the substrate 10 in the Zone Full in addition to epitaxy platform 41 be all first
The electrical scope of electrode district 30.
Third step：As shown in figure 5, using processing procedures such as gold-tinted, ion implant/diffusion, etching, insulation protections, foregoing
An electrical layer 42 is made according to the electrical characteristic of diode element on epitaxy platform 41, such as：PN junctions or protection ring 53, Xiao Te
Base energy barrier etc., to complete the electrical making in second electrode area 40.
Four steps：As shown in fig. 6, it is pointed to the positive surface of the first region 30 of diode element region 20, i.e. substrate
After the surface of electrical layer 42 in 10 surfaces and second electrode area 40 difference coating layer of metal floor 51, by each diode element region
Cut the position of Cutting Road 11 that 20 surroundings are reserved.
As shown in Figures 7 and 8, the diode element D finished products after the completion of being cut through above-mentioned 1~4 step, wherein, the second electricity
Polar region 40 includes an epitaxy platform 41, an electrical layer 42 and a metal level 51, can be construed as the second of a diode element D
Region beyond electrode P, second electrode P includes substrate 10 and the metal level 51 on the surface of the first region 30, that is, formed this two
Pole pipe element D first electrodes N.
By diode element D first electrode N is directly to be formed using substrate 10, and first electrode N is without it
His epitaxial layer or diffusion layer covering, so the characteristic with low internal resistance, along with the Zone Full of substrate 10 beyond second electrode P
Be all first electrode N electrical scope, therefore first electrode N utilization rate can be allowed to maximize, so make diode element into
Product possess the characteristic of ultralow forward voltage (VF).
In addition, as shown in Fig. 3 to Fig. 8, because position of the diode element region 20 beyond second electrode area 40 is all made
For the first region 30, make the electrical model that Zone Full of the substrate 10 in addition to second electrode area 40 is all the first region 30
Enclose, and allow Cutting Road 11 to be located at the surrounding of the first region 30, the can't be cut to when finally carrying out cutting step
Two electrode districts 40, even if producing the problem of periphery is burst apart during cutting, the electrical characteristic of second electrode, energy are not interfered with completely yet
The effectively quality stability of lifting diode element D finished products.
As shown in Fig. 9 Figure 10, during implementation, first electrode N and/or second electrode P enter one on the surface of metal level 51 respectively
Step sets a tin platform 52, and insulating protective layer 54 and/or ditch are set around the first region 30 and/or second electrode area 40
Groove 55 etc..This insulating protective layer 54 and/or groove 55 be in order to which first electrode N is isolated with second electrode P, and protect second
Electrode P；This is general processing procedure, is not repeated separately herein.
Above-mentioned Fig. 3 to Figure 10 and step explanation, are all that two poles are made directly as base material with a substrate (Substrate)
The method and step of tube elements, it is base that actually method of the invention, which is equally applicable in using epitaxy disk (EPI Wafer),
Diode element is made in material.It is well known that epitaxy disk (EPI Wafer) includes a laminar substrate (Substrate) and one layer
Positioned at the epitaxial layer (Epitaxy) of substrate front side, therefore the step of second embodiment of the present invention is as follows：
First step：As shown in figure 11, in the front of an epitaxy disk 100a, the specification chi according to needed for diode element
Very little to be divided into multiple diode element region 20a, each diode element region 20a periphery is reserved with Cutting Road 11a, and every
Configuration the first region 30a and second electrode area 40a is enclosed in one diode element region 20a；Wherein, the diode element region
Positions of the 20a beyond second electrode area 40a is all as the first region 30a.
Second step：As shown in figure 12, by above-mentioned each diode element region 20a, the first region 30a surfaces are built
Crystal layer all removes divided by exposed substrate 10a using processing procedures such as gold-tinted, etchings, allows the remaining epitaxial layer shapes of second electrode area 40a
Into an epitaxy platform 41a, make the electricity that Zone Fulls of the substrate 10a in addition to epitaxy platform 41a is all the first region 30a
Property scope.
Third step：As shown in figure 13, using processing procedures such as gold-tinted, ion implant/diffusion, etching, insulation protections, foregoing
An electrical layer 42a is made according to the electrical characteristic of diode element on second electrode area 40a epitaxy platform 41a, such as：PN connects
Face or protection ring 53a, Schottky energy barrier etc., to complete second electrode area 40a electrical making.
Four steps：As shown in figure 14, the first region 30a substrate 10a surfaces, and second electrode area are pointed to
40a electrical layer 42a surfaces, respectively after coating layer of metal layer 51a, by what is reserved around each diode element region 20a
Cutting Road 11a is cut position.
The invention described above second embodiment step and first embodiment step maximum are not both that the base material used is a base
A plate either epitaxy disk.Embodiment using substrate as base material, because substrate does not have epitaxial layer in itself, it is therefore necessary to
Two electrode districts make epitaxy platform；And the embodiment using epitaxy disk as base material, because epitaxy disk is comprehensive in substrate surface
One layer of epitaxial layer is made, therefore the epitaxial layer that the region beyond second electrode area is the first region surface is removed, it is remaining
Epitaxial layer just can form epitaxy platform in second electrode area.As for other embodiments of second embodiment of the invention,
Such as Xi Tai, insulating protective layer etc., it is all identical with first embodiment, do not repeat separately herein.
Based on the use of epitaxy disk being base material method that diode element is made, the step of third embodiment of the invention such as
Under：
First step：As shown in figure 15, in the front of an epitaxy disk 100b, the specification chi according to needed for diode element
Very little to be divided into multiple diode element region 20b, each diode element region 20b periphery is reserved with Cutting Road 11b, and every
Configuration the first region 30b and second electrode area 40b is enclosed in one diode element region 20b；Wherein, the diode element region
Positions of the 20b beyond second electrode area 40b is all as the first region 30b.
Second step：As shown in figure 16, by above-mentioned each diode element region 20b second electrode area 40b according to two
The electrical characteristic of pole pipe element makes an electrical layer 42b, such as：PN junctions or protection ring 53b, Schottky energy barrier etc., with complete
Into second electrode area 40b electrical making.
Third step：As shown in figure 17, each diode element region 20b is located to the epitaxy on the first region 30b surfaces
Layer all removes divided by exposed substrate 10b, remaining epitaxial layer is formed an epitaxy platform 41b, and second electrode area 40b is built
Structure allows substrate 10b except epitaxy platform 41b and electrical layer 42b on the epitaxy platform 41b and electrical layer 42b
Zone Full in addition is all the first region 30b electrical scope.
Four steps：As shown in figure 18, the first region 30b substrate 10b surfaces and second electrode area 40b are pointed to
Electrical layer 42b surfaces, respectively after coating layer of metal layer 51b, by the cutting reserved around each diode element region 20b
Cut road 11b positions.
Present embodiment is the epitaxial layer step of removal the first region with foregoing second embodiment difference, is complete
(second embodiment) or progress (3rd embodiment) afterwards into before the electrical layer in second electrode area, the two all meets the present invention
With a substrate as the spirit of the first electrode of a diode element.
According to made by above-mentioned three kinds of embodiments out diode element, its structure as shown in earlier figures 7 to Figure 10,
Diode element D is comprised at least：
One substrate 10, the substrate have a front and a back side；
One second electrode P, second electrode P include an epitaxy platform 41, one for being located at the upper front of substrate 10 and set
Electrical layer 42 and one on the epitaxy platform 41 sets the metal level 51 above the electrical layer 42；And
One first electrode N, it is made up of whole substrates 10 in addition to second electrode P, first electrode N is further wrapped
Include one and be coated on metal level 51 of the front of substrate 10 in the entire area in addition to second electrode P.
If likewise, diode element D added in processing procedure foregoing tin platform 52, insulating protective layer 54 and/or
During the grade of groove 55, its finished product structure as shown in FIG. 9 and 10, does not repeat separately herein.
The present invention, as the feature of first electrode, is also applied to diffusion directly by the use of the Zone Full beyond second electrode
Silicon wafer (Diffused Silicon Wafer) is as base material.The diffusion silicon wafer includes one layer of diffusion silicon crystal slate
(Silicon Wafer) and one layer are positioned at diffusion silicon crystal slate (Silicon Wafer) positive diffusion layer (Diffused), because expanding
Scattered silicon wafer is similar from epitaxy wafer architecture but material is different, therefore fourth embodiment of the invention with epitaxy simultaneously suitable for being justified
Piece or diffusion silicon wafer are the method that diode element is made in base material, and its step is as follows：
First step：An epitaxy disk/diffusion silicon wafer 100c front is divided into multiple two poles as shown in figure 19
Tube elements area 20c, each diode element region 20c periphery are reserved with Cutting Road 11c, and in each diode element region
Configuration the first region 30c and second electrode area 40c is enclosed in 20c；Wherein, diode element region 20c in second electrode
Position beyond area 40c is all as the first region 30c.
Second step：As shown in figure 20 by above-mentioned each diode element region 20c second electrode area 40c according to two poles
The electrical characteristic of tube elements makes an electrical layer 42c to complete second electrode area 40c electrical making；In this processing procedure, due to of heap of stone
Wafer/diffusion silicon wafer 100c is located at substrate/diffusion silicon comprising one laminar substrate/diffusion silicon crystal slate 10c and one layer in itself
Epitaxy/diffusion layer 41c above brilliant plate 10c, therefore electrical layer 42c is actually on epitaxy/diffusion layer 41c.
Third step：As shown in figure 21, done in the first region 30c through epitaxy disk (EPI Wafer)/diffusion silicon
Wafer 100c front and the perforation 12c at the back side, and insert metallic conduction material 13c in perforation 12c and form one
Conductive channel 31c.As previously described, because epitaxy disk/diffusion silicon wafer 100c in itself comprising one layer positioned at the back side substrate/
Spread silicon crystal slate 10c and one layer is located above substrate/diffusion silicon crystal slate 10c (i.e. positioned at epitaxy disk (EPI Wafer)/expansion
Dissipate silicon wafer 100c front) epitaxy/diffusion layer 41c, therefore disclosed in figure, perforation 12c is substrate/diffusion by the back side
Silicon crystal slate 10c extends through epitaxy/diffusion layer 41c.
Four steps：As shown in figure 22, be pointed to the first region 30c surface and second electrode area 40c it is electric
Layer 42c surfaces difference coating layer of metal layer 51c, makes the first region 30c metal level 51c and conductive channel 31c electrical
After conducting, cut by the Cutting Road 11c positions reserved around each diode element region 20c.
As previously described, because perforation 12c extends through positive epitaxy/diffusion layer by the substrate/diffusion silicon crystal slate 10c at the back side
41c simultaneously forms a conductive channel 31c after filling conductive materials 13c, therefore can allow the metal level on the first region 30c surfaces
51c electrically conducts with conductive channel 31c, so after dicing, you can forms a complete diode element.Further, since
First electrode is therefore this reality come the front and the back side of the epitaxy disk/diffusion silicon wafer that electrically conducts using conductive channel 31c
Applying example need not be by epitaxy disk/diffusion silicon wafer, and epitaxy/diffusion layer 41c positioned at the first region 30c surfaces is gone
Remove, and the forward voltage of diode element finished product can be allowed more to reduce.
As shown in figure 23, according to the above method, the present invention provides a kind of crystallite dimension encapsulation for possessing ultralow forward voltage
Diode element, comprise at least：
The one diode element D1 cut by epitaxy disk/diffusion silicon wafer, diode element D1 have one just
Face and a back side, and diode element D1 includes one layer and is located at positioned at the substrate/diffusion silicon crystal slate 10c at the back side and one layer
Positive epitaxy/diffusion layer 41c；
One second electrode P1, include an electrical layer 42c on the epitaxy/diffusion layer 41c and one and set this electric
Metal level 51c above layer 42c；And
One first electrode N1, the whole above the epitaxy/diffusion layer 41c in addition to second electrode P1 is coated on comprising one
Metal level 51c and one in area by diode element D1 back substrates/diffusion silicon crystal slate 10c extend through positive epitaxy/
Metal level 51c electricity filled with conductive materials 13c and first electrode N1 in diffusion layer 41c perforation 12c, the perforation 12c
Property conducting and formed a conductive channel 31c.
Likewise, when the diode element of the present embodiment is implemented, if diode element D1 is added in processing procedure such as preceding institute
When tin platform 52, insulating protective layer 54 and/or groove 55 for stating etc., its finished product structure is as shown in figure 23, does not repeat separately herein.
As shown in figure 24, foregoing manufacture method of the present invention is not limited to the bipolar face diode element of PN types, it is all have two with
Upper second electrode P and a first electrode N plural pole-face diode element, such as positive-negative-positive center tapped full-wave rectification
Device (center-tapped full-wave rectifier), also in present invention scope applicatory.
Implement only to illustrate presently preferred embodiments of the present invention shown in explanation and schema above, the present invention is not limited to this
Scope；Such as approximate with the construction, device, feature of invention etc. the or person that mutually duplicates, all should belong in protection scope of the present invention, sincerely
This statement.
Claims (8)
- A kind of 1. manufacture method for the crystallite dimension encapsulation diode element for possessing ultralow forward voltage, it is characterised in that：Directly Zone Full beyond by the use of second electrode makes first electrode without epitaxial layer or diffusion as the first electrode of a diode element Layer covering, this method comprise the steps of：First step：The front of one substrate is divided into multiple diode element regions, the periphery of each diode element region is reserved There are Cutting Road and interior enclose to configure a second electrode area, and position of each diode element region beyond its second electrode area is complete Portion is as the first region；Second step：An epitaxy platform is made on the second electrode area allocation position of above-mentioned each diode element region, makes this Zone Full of the substrate in addition to epitaxy platform is all the electrical scope of the first region；Third step：An electrical layer is made to complete the second electricity according to the electrical characteristic of diode element on foregoing epitaxy platform The electrical making of polar region；Four steps：It is pointed to the substrate surface of the first region and the electric layer surface difference floor of coating one in second electrode area After metal level, cut by the Cutting Road position reserved around each diode element region.
- A kind of 2. manufacture method for the crystallite dimension encapsulation diode element for possessing ultralow forward voltage, it is characterised in that：Directly Zone Full beyond by the use of second electrode makes first electrode be covered without epitaxial layer or diffusion layer, this method as first electrode Comprise the steps of：First step：The front of one epitaxy disk is divided into multiple diode element regions, the periphery of each diode element region It is reserved with Cutting Road and interior enclose configures a second electrode area, and position of each diode element region beyond its second electrode area Put all as the first region；Second step：By in above-mentioned each diode element region, the epitaxial layer on the first region surface all goes divided by exposed Substrate, and the remaining epitaxial layer in second electrode area is formed an epitaxy platform, make whole of the substrate in addition to epitaxy platform Region is all the electrical scope of the first region；Third step：An electrical layer is made according to the electrical characteristic of diode element on the epitaxy platform in foregoing second electrode area To complete the electrical making in second electrode area；Four steps：It is pointed to the substrate surface of the first region and the electric layer surface difference floor of coating one in second electrode area After metal level, cut by the Cutting Road position reserved around each diode element region.
- A kind of 3. manufacture method for the crystallite dimension encapsulation diode element for possessing ultralow forward voltage, it is characterised in that：Directly Zone Full beyond by the use of second electrode makes first electrode be covered without epitaxial layer or diffusion layer, this method as first electrode Comprise the steps of：First step：The front of one epitaxy disk is divided into multiple diode element regions, the periphery of each diode element region It is reserved with Cutting Road and interior enclose configures a second electrode area, and position of each diode element region beyond its second electrode area Put all as the first region；Second step：It will be made in the second electrode area of above-mentioned each diode element region according to the electrical characteristic of diode element One electrical layer is to complete the electrical making in second electrode area；Third step：The epitaxial layer that each diode element region is located to the first region surface all removes divided by exposed base Plate, remaining epitaxial layer is set to form an epitaxy platform, the second electrode area is built in the epitaxy platform and the electrical layer, and Zone Full of the substrate in addition to epitaxy/diffusion platform and electrical layer is all the electrical scope of the first region；Four steps：It is pointed to the substrate surface of the first region and the electric layer surface difference floor of coating one in second electrode area After metal level, cut by the Cutting Road position reserved around each diode element region.
- 4. a kind of crystallite dimension encapsulation diode element for possessing ultralow forward voltage, it is characterised in that comprise at least：One substrate, the substrate have a front and a back side；One second electrode, include an epitaxy platform above the substrate front side, one be arranged on electricity on the epitaxy platform Gas-bearing formation and one set the electrical layer above metal level；AndOne first electrode, it is made up of whole substrates in addition to second electrode, the first electrode further comprises a coating In metal level of the substrate front side in the entire area in addition to second electrode.
- 5. the crystallite dimension encapsulation diode element according to claim 4 for possessing ultralow forward voltage, it is characterised in that： The first electrode and/or second electrode further set a Xi Tai, and first electrode and/or second in layer on surface of metal respectively Insulating protective layer and/or groove are provided with around electrode.
- A kind of 6. manufacture method for the crystallite dimension encapsulation diode element for possessing ultralow forward voltage, it is characterised in that：Directly Zone Full beyond by the use of second electrode turns on as first electrode after being perforated to the positive back side of first electrode, makes first Electrode turns on without using epitaxial layer or diffusion layer, and this method comprises the steps of：First step：The front of one epitaxy disk/diffusion silicon wafer is divided into multiple diode element regions, each diode The periphery of element region is reserved with Cutting Road and interior enclose configures a second electrode area, and each diode element region is in its second electricity Position beyond polar region is all as the first region；Second step：It will be made in the second electrode area of above-mentioned each diode element region according to the electrical characteristic of diode element One electrical layer is to complete the electrical making in second electrode area；Third step：Done in the first region through the front of epitaxy disk/diffusion silicon wafer and the perforation at the back side, and Metallic conduction material is inserted in perforation and forms a conductive channel；Four steps：It is pointed to the surface of the first region and the electric layer surface difference coating layer of metal in second electrode area Layer, the metal level and the conductive channel for making the first region electrically conduct, afterwards by being reserved around each diode element region Cutting Road position cut.
- 7. a kind of crystallite dimension encapsulation diode element for possessing ultralow forward voltage, it is characterised in that comprise at least：The one diode element body cut out by epitaxy disk/diffusion silicon wafer, the diode element body include One layer is located at positive epitaxy/diffusion layer positioned at the substrate/diffusion silicon crystal slate at the back side and one layer；One second electrode, include an electrical layer on epitaxy/diffusion layer and one and metal level above the electrical layer is set； AndOne first electrode, the gold being coated on comprising one in the entire area above the epitaxy/diffusion layer in addition to second electrode Category layer and a perforation for extending through positive epitaxy/diffusion layer by the diode element body back substrate/diffusion silicon crystal slate, institute State in perforation and electrically conduct filled with conductive materials and the metal level of the first electrode and form a conductive channel.
- 8. the crystallite dimension encapsulation diode element according to claim 7 for possessing ultralow forward voltage, it is characterised in that： The first electrode and/or second electrode further set a Xi Tai, and first electrode and/or second in layer on surface of metal respectively Insulating protective layer and/or groove are provided with around electrode.
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| CN201610560122.5A CN107622956A (en) | 2016-07-15 | 2016-07-15 | Possess the crystallite dimension encapsulation diode element and manufacture method of ultralow forward voltage |
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|---|---|---|---|---|
| US6979835B1 (en) * | 2004-09-11 | 2005-12-27 | Formosa Epitaxy Incorporation | Gallium-nitride based light-emitting diode epitaxial structure |
| US20060249727A1 (en) * | 2004-09-11 | 2006-11-09 | Cheng-Tsang Yu | Gallium-Nitride Based Light Emitting Diode Light Emitting Layer Structure |
| CN102881783A (en) * | 2012-10-11 | 2013-01-16 | 施科特光电材料(昆山)有限公司 | Method for cutting light emitting diode chip through deep etching |
| CN103295897A (en) * | 2012-03-01 | 2013-09-11 | 美丽微半导体股份有限公司 | Well-through type diode element or diode assembly and method for manufacturing well-through type diode element or diode assembly |
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2016
- 2016-07-15 CN CN201610560122.5A patent/CN107622956A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6979835B1 (en) * | 2004-09-11 | 2005-12-27 | Formosa Epitaxy Incorporation | Gallium-nitride based light-emitting diode epitaxial structure |
| US20060249727A1 (en) * | 2004-09-11 | 2006-11-09 | Cheng-Tsang Yu | Gallium-Nitride Based Light Emitting Diode Light Emitting Layer Structure |
| CN103295897A (en) * | 2012-03-01 | 2013-09-11 | 美丽微半导体股份有限公司 | Well-through type diode element or diode assembly and method for manufacturing well-through type diode element or diode assembly |
| CN102881783A (en) * | 2012-10-11 | 2013-01-16 | 施科特光电材料(昆山)有限公司 | Method for cutting light emitting diode chip through deep etching |
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