TWI624884B - Grain size packaged diode element with ultra-low forward voltage and method of manufacturing the same - Google Patents

Abstract

The present invention is a chip size packaged diode element having an ultra-low forward voltage and a method of fabricating the same, wherein the diode element directly uses all regions except the second electrode as a first electrode, and/or uses a perforation After passing through the front side of the first electrode and conducting, after cutting, a smaller volume of the chip size package (CSP) diode element can be formed; since the first electrode of the invention does not need to pass through the epitaxial layer or the diffusion layer Turn-on, so it can avoid the internal resistance and reduce the forward voltage (VF), and has many advantages such as simplifying the process, improving the quality, reducing the cost, and making the diode components lighter, thinner and shorter.

Description

Grain size packaged diode element with ultra-low forward voltage and method of manufacturing the same

The invention relates to a chip scale package (CSP) diode component and a manufacturing method thereof, and relates to a substrate (Substrate), an epitaxial layer (Epitaxy), an epi-wafer (EPI Wafer), and a diffusion device. Silicon Wafer, Diffused, Diffused Silicon Wafer. The resulting diode component has ultra-low forward voltage (VF) characteristics, which simplifies the process, improves quality, reduces cost, and makes the diode components lighter, thinner and shorter.

Materials used in Flip Chip diode devices that are typically fabricated into semiconductor grain materials (CSP) include EPI Wafer and Diffused Silicon Wafer. . The Lei wafer includes a substrate on the back side and a layer of epitaxial layer on the front side. The diffusion germanium wafer is provided with a diffusion layer on the front and back sides of a layer of twinned material, wherein the back portion of the diffused silicon wafer is defined as a diffusion wafer (Silicon Wafer). The front part is defined as a diffusion layer (Diffused).

When the diode is fabricated from a material such as a bump wafer or a diffusion germanium wafer, the conventional processes and steps are as follows in the first and second figures, as follows:

1. Fabricate an epitaxial/diffusion layer on the front side of a substrate or a silicon wafer by an epitaxial process, a diffusion process, or an Ion Implantation process. To form an EPI Wafer/Diffused Silicon Wafer 1 (if the diffusion 矽 wafer is double-sided diffusion, the diffusion 矽 wafer has a diffusion layer on the front and back sides) .

2. Dividing a plurality of arrayed diode element regions 2 on the epitaxial wafer/diffusion wafer 1 according to the size and size of the diode element, and in each diode element Zone 2 design The positions of the N pole 3 and the P pole 4 are taken out.

3. Depending on the electrical characteristics required for the diode element, a N-pole-transformed general-purpose epitaxial/diffusion layer is formed on the N-pole 3 region by means of yellow light, etching, ion implantation or diffusion (not shown). .

4. Depending on the electrical characteristics required of the diode component, an electrical layer is formed on the P pole 4 by means of yellow light, etching, ion implantation or diffusion, for example: PN junction or guard ring, Schottky barrier And, an insulating protective layer 5 is formed around the P pole 4 and the N pole 3 for isolating the N pole 3 from the P pole 4.

5. A layer of metal conductive layer is coated on the surfaces of the N pole 3 and the P pole 4 respectively.

6. The plurality of diode element regions 2 separated by the second step are cut and separated by a cutting method to separate a plurality of finished packaged diode components; in the second figure, the diode element region 2 That is, a top view of the finished product of the diode element.

Since the electrical characteristics of the above-mentioned diode components are all fabricated on a stretch wafer/diffused germanium wafer, the core size of each of the diode components is very close to the package size, so it is called a grain size package. The volume of the diode element can be greatly reduced. However, the following processes still have the following deficiencies:

1. The original epitaxial/diffusion layer of the N-pole is intended to allow electrons to pass through the N-pole region at a lower internal resistance when the current is conducted in a forward direction, but the epitaxial/diffusion layer itself generates an additional internal resistance. The forward voltage (VF) is still high.

2. The substrate or the diffusion crystal plate is made of a common epitaxial/diffusion layer by means of yellow light, etching, ion implantation or diffusion with respect to the N-pole position, and has a long process and high cost.

3. The area other than the P and N poles is left unused due to the setting of the guard ring and the insulating protective layer, and the forward voltage is also high for the forward conduction.

4. The scribe line is surrounded by the periphery of the P pole and the N pole. When the component is cut, the P pole and the N pole have the problem of CHIPPING & CRACK, which seriously affects the quality stability of the finished component of the diode.

The main object of the present invention is to provide a method for improving the above process, wherein the diode element directly uses all regions except the second electrode as the first electrode, and/or the through hole is penetrated through the front surface of the first electrode, and is cut. After that, a smaller grain size can be formed. The finished diode component is finished; and the first electrode and the second electrode are jointly disposed on the front surface of the diode component to form a smaller-sized grain-sized packaged diode component. In addition, by directly using all the regions other than the second electrode as the first electrode, the first electrode does not need to be turned on by the epitaxial layer or the diffusion layer, so that the internal resistance and the forward voltage can be reduced, and the process can be shortened.

In order to achieve the above object, a method for fabricating a grain size packaged diode device having an ultra-low forward voltage is characterized in that all regions other than the second electrode are directly used as a first electrode, so that the first electrode has no Lei Covered by a crystal layer or a diffusion layer, the method comprises the following steps:

1. On the front side of a substrate (Substrate) is divided into a plurality of diode element regions, a periphery of each of the diode element regions is reserved with a dicing street, and an inner circumference is disposed with a second electrode region, and each diode body The element region is entirely the first electrode region at a position other than the second electrode region.

2. An epitaxial platform is formed on the second electrode region of each of the diode element regions, so that all regions except the epitaxial platform of the substrate are electrical ranges of the first electrode region.

3. On the epitaxial platform, an electrical layer is formed according to the electrical characteristics of the diode element, such as a PN junction or a guard ring, an energy barrier, etc. to complete the electrical fabrication of the second electrode region.

4. After the metal layer on the surface of the substrate in the first electrode region and the surface of the second electrode region are respectively covered with a metal layer, the position of the scribe line reserved around each of the diode element regions is cut.

A method for fabricating a grain size packaged diode device having an ultra-low forward voltage, characterized in that all regions other than the second electrode are directly used as a first electrode, so that the first electrode has no epitaxial layer or diffusion layer Override, the method consists of the following steps:

1. Divided into a plurality of diode element regions on the front surface of an EPI Wafer, each of which has a dicing street and a second electrode region disposed on the periphery of the diode element region, and Each of the diode element regions is entirely in the first electrode region at a position other than the second electrode region.

2. removing the epitaxial layer on the surface of the first electrode region in each of the diode element regions to expose the substrate, and forming the epitaxial layer remaining in the second electrode region to form an epitaxial platform, so that the substrate is All areas except the epitaxial platform are the electrical range of the first electrode region.

3. An electrical layer is formed on the epitaxial platform of the second electrode region according to the electrical characteristics of the diode element to complete the electrical fabrication of the second electrode region.

4. coating the surface of the substrate located in the first electrode region and the surface of the electrical layer of the second electrode region After the metal layer is layered, it is cut by the position of the scribe line reserved around each of the diode element regions.

A method for fabricating a grain size packaged diode device having an ultra-low forward voltage, characterized in that all regions other than the second electrode are directly used as a first electrode, so that the first electrode has no epitaxial layer or diffusion layer Override, the method consists of the following steps:

1. Divided into a plurality of diode element regions on the front surface of an EPI Wafer, each of which has a dicing street and a second electrode region disposed on the periphery of the diode element region, and Each of the diode element regions is entirely a first electrode region at a position other than the second electrode region.

2. An electrical layer is formed on the second electrode region of each of the diode element regions according to electrical characteristics of the diode element to complete electrical fabrication of the second electrode region.

3. The epitaxial layer of each of the diode element regions on the surface of the first electrode region is completely removed to expose the substrate, so that the remaining epitaxial layer forms an epitaxial platform, and the second electrode region is constructed on the epitaxial layer. The platform and the electrical layer, and the entire area of the substrate except the epitaxial platform and the electrical layer are electrical ranges of the first electrode region.

4. After the metal layer on the surface of the substrate in the first electrode region and the surface of the second electrode region are respectively covered with a metal layer, the position of the scribe line reserved around each of the diode element regions is cut.

The above invention is divided into three steps because the substrate used in the process is a substrate without an epitaxial layer, or an epi-wafer (EPI Wafer) comprising a substrate and an epitaxial layer. The feature is that all regions other than the second electrode are directly used as the first electrode, and the first electrode is not covered by other epitaxial layers or diffusion layers, so that the internal resistance is low, and all regions except the second electrode are added. Because of the electrical range of the first electrode, the utilization of the first electrode can be maximized, and the finished diode product can have ultra-low forward voltage (VF) characteristics.

According to the above method, the present invention provides a grain size packaged diode device having an ultra-low forward voltage, comprising at least: a substrate having a front surface and a back surface; and a second electrode including a front surface of the substrate An upper epitaxial platform, an electrical layer disposed on the epitaxial platform, a metal layer disposed above the electrical layer, and a first electrode composed of all substrates except the second electrode, the first electrode Further included is a metal layer overlying the entire surface of the substrate except for the second electrode.

In implementation, the first electrode and/or the second electrode are further provided with a tin pad on the surface of the metal layer, and an insulating protective layer and/or a trench are disposed around the first electrode and/or the second electrode.

A method for fabricating a grain size packaged diode device having an ultra-low forward voltage, characterized in that all regions other than the second electrode are directly used as a first electrode and perforated at the front and back sides of the first electrode region After the conduction, the first electrode is not required to be turned on by using the epitaxial layer or the diffusion layer, and the method comprises the following steps:

1. Divided into a plurality of diode element regions on the front side of an EPI Wafer/Diffused Silicon Wafer, and a scribe line is reserved on the periphery of each diode element region. A second electrode region is disposed in the inner circumference, and each of the diode element regions is entirely used as the first electrode region at positions other than the second electrode region.

2. An electrical layer is formed on the second electrode region of each of the diode element regions according to electrical characteristics of the diode element to complete electrical fabrication of the second electrode region.

3. Perforation through the front and back sides of the epitaxial wafer/diffusion wafer is performed in the first electrode region, and a metal conductive material is filled in the perforation to form a conduction channel.

4. coating a surface of the first electrode region and the surface of the second electrode region with a metal layer to electrically connect the metal layer of the first electrode region to the conductive channel, and then each of the diode elements The location of the cutting path reserved around the area is cut.

According to the above method, the present invention provides a grain size packaged diode device having an ultra-low forward voltage, comprising at least: a diode body that is cut by a stretch wafer/diffused germanium wafer, The diode body includes a substrate/diffused crystal plate on the back side and an epitaxial/diffusion layer on the front side; a second electrode includes an electrical layer on the epitaxial/diffusion layer, and the electrical layer is disposed a metal layer above the layer; and a first electrode comprising a metal layer overlying the entire area of the epitaxial/diffusion layer except the second electrode, and a back substrate/diffusion of the body of the diode body The crystal plate penetrates through the through hole of the front epitaxial/diffusion layer, and the through hole is filled with a conductive material and electrically connected to the metal layer of the first electrode to form a conduction channel.

In implementation, the first electrode and/or the second electrode are further provided with a tin pad on the surface of the metal layer, and an insulating protective layer and/or a trench are disposed around the first electrode and/or the second electrode.

Compared with the prior art, the present invention has the following advantages in terms of process and electrical characteristics:

1. If the second component of the diode element uses the substrate as the first electrode of the diode element, since the first electrode is not covered by other epitaxial layers or diffusion layers, the internal resistance is low, and the utilization ratio of the first electrode is maximized. Therefore, when the diode component is turned on, the forward voltage (VF) of the component can be further reduced.

2. If the via is used to penetrate the wafer/diffusion wafer and fill the conductive material to form a conduction channel, the first electrode can electrically conduct the front and back surfaces directly through the conduction channel without passing through the epitaxial layer or diffusion. The layer can therefore reduce the forward voltage of the finished diode component.

3. Since all the areas except the second electrode area are the electrical range of the first electrode, the scribe line is located around the first electrode, and even if the corner is cracked (Chipping & Crack) does not affect the first The electrical characteristics of the two electrodes make the electrical characteristics of the finished diode components more stable.

Hereinafter, according to the technical means of the present invention, an implementation method suitable for the present creation is listed, and the following description is in conjunction with the following:

100a, 100b‧‧‧ Lei wafers

100c‧‧‧ Lei wafer/diffusion wafer

10, 10a, 10b‧‧‧ substrate

10c‧‧‧Substrate/diffusion crystal plate

11, 11a, 11b, 11c‧‧ ‧ cutting road

12c‧‧‧Perforation

13c‧‧‧Conducting materials

20, 20a, 20b, 20c‧‧‧ diode element area

30, 30a, 30b, 30c‧‧‧ first electrode area

31c‧‧‧ conduction channel

40, 40a, 40b, 40c‧‧‧ second electrode area

41, 41a, 41b‧‧‧ epitaxial platform

41c‧‧‧ epitaxial/diffusion layer

42, 42a, 42b, 42c‧‧‧ electrical layer

51, 51a, 51b, 51c‧‧‧ metal layers

52‧‧‧ tin table

53‧‧‧Protection ring

54‧‧‧Insulation protective layer

55‧‧‧ trench

D, D1‧‧‧ diode components

N, N1‧‧‧ first electrode

P, P1‧‧‧ second electrode

First: A schematic diagram of a conventional technique of dividing a wafer/diffusion wafer into a plurality of diode component blocks.

Second: The conventional technique divides each of the diode element blocks into a positional view of the first electrode and the second electrode.

Third Embodiment: A schematic diagram of dividing a front surface of a substrate into a plurality of diode element regions according to a first embodiment of the present invention.

Fourth Figure: A schematic view of the first embodiment of the present invention for forming an epitaxial platform on a second electrode region.

Fig. 5 is a schematic view showing the fabrication of an electrical layer on the second electrode region in the first embodiment of the present invention.

Figure 6: Electrical layer table on the surface of the first electrode region and the second electrode region in the first embodiment of the present invention A schematic diagram of cutting the surface after coating a metal layer.

Figure 7 is a cross-sectional view showing the structure of the finished diode element of the first embodiment of the present invention.

Figure 8 is a plan view showing the finished product of the diode element of the first embodiment of the present invention.

Ninth view: A schematic structural view of a tin table, a guard ring, and an insulating protective layer in the first embodiment of the present invention.

Fig. 10 is a schematic view showing the structure of a groove in the first embodiment of the present invention.

Eleventh Embodiment: A second embodiment of the present invention divides a front surface of a wafer into a plurality of diode element regions, and each of the diode element regions is configured with a first electrode region and a second electrode region. .

Twelfth Embodiment: A schematic view showing the entire epitaxial layer of the first electrode region removed in the second embodiment of the present invention.

Thirteenth Diagram: A schematic view showing the electrical fabrication of the second electrode region in the second embodiment of the present invention.

Figure 14 is a schematic view showing the second embodiment of the present invention in which the surface of the first electrode region and the surface of the electrical layer of the second electrode region are respectively covered with a metal layer.

Fifteenth Embodiment: A third embodiment of the present invention divides a front surface of a wafer into a plurality of diode element regions, and each of the diode element regions is configured with a first electrode region and a second electrode region. .

Figure 16 is a schematic view showing the electrical fabrication of the second electrode region in the third embodiment of the present invention.

Figure 17 is a schematic view showing the third embodiment of the present invention in which all of the epitaxial layers other than the second electrode arrangement position of each of the diode element regions are removed.

Figure 18: Schematic diagram of cutting after coating a metal layer on the surface of the first electrode region and the surface of the second electrode region.

FIG. 19: a fourth embodiment of the present invention divides a front surface of a wafer/diffusion wafer into a plurality of diode element regions, and each of the diode element regions is configured with a first electrode region and A schematic representation of a second electrode zone.

Fig. 20 is a schematic view showing the electrical fabrication of the second electrode region in the fourth embodiment of the present invention.

Twenty-first drawing: A schematic view of the fourth embodiment of the present invention for fabricating a conduction path.

Twenty-second drawing: A schematic view of the fourth embodiment of the present invention after cutting a metal layer.

Twenty-third drawing: Schematic diagram of the structure of the diode element fabricated in the fourth embodiment of the present invention.

Twenty-fourth drawing: Schematic diagram of a PNP type center-tapped full-wave rectifier fabricated by the present invention.

For convenience of description, the following embodiments are based on an N-type substrate or a germanium wafer, and the present invention provides a method for fabricating a die-size packaged diode element having an ultra-low forward voltage, the first embodiment comprising the following steps :

The first step: as shown in the third figure, the front surface of a substrate 10 is divided into a plurality of diode element regions 20 according to the required size of the diode elements, and the periphery of each of the diode element regions 20 is pre-predicted. A dicing street 11 is left, and a first electrode region 30 and a second electrode region 40 are disposed in the inner circumference of each of the diode element regions 20; wherein the diode element region 20 is located outside the second electrode region 40 All are used as the first electrode region 30.

The second step: as shown in the fourth figure, in the position of the second electrode region 40 of each of the diode element regions 20, an epitaxial platform 41 is formed by an epitaxial process, so that the substrate 10 is in addition to epitaxy. All regions except the platform 41 are the electrical ranges of the first electrode region 30.

The third step: as shown in the fifth figure, using the process of yellow light, ion implantation/diffusion, etching, insulation protection, etc., on the epitaxial platform 41, an electrical layer 42 is fabricated according to the electrical characteristics of the diode element, for example : PN junction or guard ring 53, Schottky barrier, etc., to complete the electrical fabrication of the second electrode region 40.

Fourth step: as shown in the sixth figure, the surface of the first electrode region 30 on the front surface of the diode element region 20, that is, the surface of the substrate 10 and the surface of the electrical layer 42 of the second electrode region 40 are respectively covered with a metal layer 51. Thereafter, the position of the scribe line 11 reserved around each of the diode element regions 20 is cut.

As shown in the seventh and eighth figures, the completed diode device D is completed by the above steps 1 to 4, wherein the second electrode region 40 includes an epitaxial platform 41, an electrical layer 42 and a metal layer. 51. The second electrode P constituting the diode element D can be constructed, and the region other than the second electrode P includes the substrate 10 and the metal layer 51 on the surface of the first electrode region 30, that is, the diode element D is formed. An electrode N.

Since the first electrode N of the diode element D is directly formed by the substrate 10, and the first electrode N is covered by no other epitaxial layer or diffusion layer, it has a low internal resistance characteristic. In addition, the entire area of the substrate 10 other than the second electrode P is the electrical range of the first electrode N, so that the utilization ratio of the first electrode N can be maximized, and the finished product of the diode element has an ultra-low forward voltage. (VF) characteristics.

Further, as shown in the third to eighth figures, since the position of the diode element region 20 outside the second electrode region 40 is entirely the first electrode region 30, all the regions except the second electrode region 40 of the substrate 10 are It is the electrical range of the first electrode region 30, and the scribe line 11 is located around the first electrode region 30, and does not cut into the second electrode region 40 when the cutting step is finally performed, even if the peripheral crack occurs during cutting. The problem does not affect the electrical characteristics of the second electrode at all, and can effectively improve the quality stability of the finished product of the diode element D.

As shown in the ninth embodiment, the first electrode N and/or the second electrode P are further provided with a tin pad 52 on the surface of the metal layer 51, and the first electrode region 30 and/or the second electrode. An insulating protective layer 54 and/or a trench 55 and the like are provided around the region 40. The insulating protective layer 54 and/or the trench 55 is for isolating the first electrode N from the second electrode P and protecting the second electrode P; this is a general process and will not be further described herein.

The above third to tenth drawings and the description of the steps are all methods and steps for forming a diode element directly by using a substrate as a substrate. In practice, the method of the present invention can also be applied to the use of a stretch wafer (EPI Wafer). A diode element is made of a substrate. As is known, the epitaxial wafer (EPI Wafer) comprises a substrate (Substrate) and a layer of epitaxial layer (Epitaxy) on the front side of the substrate. Therefore, the steps of the second embodiment of the present invention are as follows:

The first step: as shown in FIG. 11 , the front surface of the epitaxial wafer 100a is divided into a plurality of diode element regions 20a according to the size required for the diode element, and each of the diode elements A dicing street 11a is reserved in the periphery of the region 20a, and a first electrode region 30a and a second electrode region 40a are disposed in the inner circumference of each of the diode element regions 20a; wherein the diode element region 20a is at the second electrode The position other than the region 40a is entirely the first electrode region 30a.

The second step: as shown in FIG. 12, in each of the diode element regions 20a, the epitaxial layer on the surface of the first electrode region 30a is completely removed by a process such as yellow light or etching to expose the substrate 10a. The remaining epitaxial layer of the second electrode region 40a forms an epitaxial land 41a such that all regions except the epitaxial land 41a of the substrate 10a are electrical ranges of the first electrode region 30a.

The third step: as shown in the thirteenth figure, using yellow light, ion implantation/diffusion, In the etching, insulation protection process, an electrical layer 42a is formed on the epitaxial land 41a of the second electrode region 40a according to the electrical characteristics of the diode element, for example, a PN junction or a guard ring 53a, a Schottky barrier, etc. Etc., to complete the electrical fabrication of the second electrode region 40a.

The fourth step: as shown in FIG. 14, the surface of the substrate 10a located in the first electrode region 30a and the surface of the electrical layer 42a of the second electrode region 40a are respectively covered with a metal layer 51a, and each of the two electrodes The position of the scribe line 11a reserved around the body element region 20a is cut.

The maximum difference between the steps of the second embodiment of the present invention and the steps of the first embodiment is that the substrate used is a substrate or a wafer. In the embodiment in which the substrate is used as the substrate, since the substrate itself does not have an epitaxial layer, an epitaxial platform must be fabricated in the second electrode region; and in the embodiment in which the wafer is used as a substrate, the wafer is on the substrate. An epitaxial layer has been completely formed on the surface, so that the epitaxial layer on the surface of the first electrode region except the second electrode region is removed, and the remaining epitaxial layer can form an epitaxial platform in the second electrode region. Other detailed embodiments of the second embodiment of the present invention, such as a tin table, an insulating protective layer, and the like, are the same as those of the first embodiment, and are not described herein.

The method of the third embodiment of the present invention is based on a method of fabricating a diode element using a bump wafer as a substrate:

The first step: as shown in the fifteenth figure, the front surface of the epitaxial wafer 100b is divided into a plurality of diode element regions 20b according to the required size of the diode element, and each of the diode elements A dicing street 11b is reserved in the periphery of the region 20b, and a first electrode region 30b and a second electrode region 40b are disposed in the inner circumference of each of the diode element regions 20b; wherein the diode element region 20b is at the second electrode The position other than the region 40b is entirely the first electrode region 30b.

The second step: as shown in the sixteenth figure, the second electrode region 40b of each of the diode element regions 20b is formed with an electrical layer 42b according to the electrical characteristics of the diode element, for example: PN junction or protection Ring 53b, Schottky barrier, etc., to complete the electrical fabrication of the second electrode region 40b.

The third step: as shown in FIG. 17, the epitaxial layer of each of the diode element regions 20b on the surface of the first electrode region 30b is completely removed to expose the substrate 10b, so that the remaining epitaxial layers form an epitaxial layer. The second electrode region 40b is constructed on the epitaxial platform 41b and the electrical layer 42b, and all the regions except the epitaxial platform 41b and the electrical layer 42b of the substrate 10b are the first electrode region 30b. Electrical range.

The fourth step: as shown in the eighteenth figure, the surface of the substrate 10b located in the first electrode region 30b and the surface of the electrical layer 42b of the second electrode region 40b are respectively covered with a metal layer 51b, respectively, by each of the two poles The position of the scribe line 11b reserved around the body element region 20b is cut.

The difference between the present embodiment and the foregoing second embodiment is that the step of removing the epitaxial layer of the first electrode region is performed before (the second embodiment) or after the completion of the electrical layer of the second electrode region (third embodiment), The invention is in accordance with the inventive spirit of the present invention using the substrate as the first electrode of a diode element.

The diode element fabricated according to the above three embodiments has a structure as shown in the seventh to tenth embodiments. The diode element D includes at least a substrate 10 having a front surface and a back surface. a second electrode P, the second electrode P includes an epitaxial platform 41 above the front surface of the substrate 10, an electrical layer 42 disposed on the epitaxial platform 41, and a metal layer 51 disposed above the electrical layer 42; And a first electrode N composed of all the substrates 10 except the second electrode P, the first electrode N further including a metal layer 51 covering the entire surface of the substrate 10 except the second electrode P.

Similarly, if the diode element D is added with the tin pad 52, the insulating protective layer 54 and/or the groove 55 as described above in the process, the finished structure is as shown in the ninth and tenth This will not be repeated.

The invention directly utilizes all regions except the second electrode as the characteristics of the first electrode, and is also suitable for using a diffusion silicon wafer as a substrate. The diffusion germanium wafer comprises a diffusion silicon wafer and a diffusion layer on the front surface of the diffusion silicon wafer. The diffusion germanium wafer has a similar structure to the epi-wafer structure but is made of a material. Differently, the fourth embodiment of the present invention is also applicable to a method for fabricating a diode element using a stretch wafer or a diffusion germanium wafer as follows:

The first step: as shown in FIG. 19, the front surface of the epitaxial wafer/diffusion wafer 100c is divided into a plurality of diode element regions 20c, and the periphery of each of the diode element regions 20c is reserved. There is a dicing street 11c, and a first electrode region 30c and a second electrode region 40c are disposed in the inner circumference of each of the diode element regions 20c; wherein the diode element region 20c is outside the second electrode region 40c The positions are all as the first electrode region 30c.

The second step: forming an electrical layer 42c according to the electrical characteristics of the diode element on the second electrode region 40c of each of the diode element regions 20c as shown in FIG. 20 to complete the electricity of the second electrode region 40c. In the process, since the epi wafer/diffusion wafer 100c itself comprises a substrate/diffusion crystal plate 10c and a layer of epitaxial/diffusion layer 41c above the substrate/diffusion crystal plate 10c, The electrical layer 42c is actually located on the epitaxial/diffusion layer 41c.

Third step: as shown in FIG. 21, a through hole 12c penetrating the front and back sides of the epitaxial wafer (EPI Wafer)/diffusion wafer 100c is formed in the first electrode region 30c, and the perforation 12c is formed in the first electrode region 30c. The metal conductive substance 13c is filled thereinto to form a conduction path 31c. As described above, since the epitaxial wafer/diffusion germanium wafer 100c itself includes a substrate/diffused crystal plate 10c on the back side and a layer above the substrate/diffusion crystal plate 10c (ie, on the epitaxial wafer ( The epitaxial/diffusion layer 41c of the EPI Wafer) is diffused from the front side of the wafer 100c. Therefore, it is disclosed that the through hole 12c is penetrated from the substrate/diffused crystal plate 10c on the back surface to the epitaxial/diffusion layer 41c.

The fourth step: as shown in the twenty-second figure, the surface of the electrical layer 42c located on the surface of the first electrode region 30c and the second electrode region 40c is respectively covered with a metal layer 51c to make the metal layer of the first electrode region 30c After being electrically conducted to the conduction path 31c, the 51c is cut by the position of the scribe line 11c reserved around each of the diode element regions 20c.

As described above, since the through hole 12c is penetrated from the back substrate/diffusion crystal plate 10c to the front epitaxial/diffusion layer 41c and filled with the conductive material 13c to form a conduction path 31c, the metal on the surface of the first electrode region 30c can be made. The layer 51c is electrically connected to the conduction channel 31c, so that after the cutting, a complete diode element can be formed. In addition, since the first electrode is electrically conductively conductive to the front and back sides of the wafer/diffusion wafer by the conduction channel 31c, the present embodiment does not need to be in the wafer/diffusion wafer. The epitaxial/diffusion layer 41c on the surface of one electrode region 30c is removed, and the forward voltage of the finished diode element can be further reduced.

As shown in the twenty-third figure, according to the above method, the present invention provides a grain size packaged diode device having an ultra-low forward voltage, comprising at least: a wafer cut by a spread wafer/diffusion wafer a diode element D1 having a front surface and a back surface, and the diode element D1 includes a substrate/diffused crystal plate 10c on the back side and a layer of epitaxial/diffusion layer on the front side 41c; a second electrode P1 includes an electrical layer 42c on the epitaxial/diffusion layer 41c, a metal layer 51c disposed over the electrical layer 42c, and a first electrode N1 including a layer of epitaxy/ a metal layer 51c over the entire area of the diffusion layer 41c except for the second electrode P1, and a through hole 12c penetrating the back substrate/diffusion crystal plate 10c of the diode element D1 to the front epitaxial/diffusion layer 41c. The conductive material 13c filled in the through hole 12c is electrically connected to the metal layer 51c of the first electrode N1 to form a conduction path 31c.

Similarly, when the diode element of the embodiment is implemented, if the diode element D1 is added with the tin pad 52, the insulating protective layer 54 and/or the groove 55 as described above in the process, the finished structure is As shown in the twenty-third figure, it will not be described here.

As shown in the twenty-fourth embodiment, the foregoing manufacturing method of the present invention is not limited to the PN type bipolar diode element, and the plurality of pole face diode elements having two or more second electrodes P and one first electrode N, For example, a PNP type center-tapped full-wave rectifier is also within the scope of the present invention.

The above description of the embodiments and the drawings are merely illustrative of the preferred embodiments of the present invention, and are not intended to limit the scope of the present invention; all of the structures, devices, features, etc. Within the scope of the patent application of the present invention, it is hereby stated.

Claims (8)

A method for manufacturing a grain size packaged diode device having an ultra-low forward voltage, characterized in that all regions other than the second electrode are directly used as a first electrode of a diode element, so that the first electrode has no Lei Covering with a crystal layer or a diffusion layer, the method comprises the following steps: a first step: dividing a front side of a substrate into a plurality of diode element regions, and a periphery of each of the diode element regions is provided with a cutting track and an inner circumference configuration a second electrode region, and each of the diode element regions is entirely used as a first electrode region at a position other than the second electrode region; and a second step: a second electrode region disposed in each of the diode element regions Forming an epitaxial platform, so that all areas except the epitaxial platform of the substrate are the electrical range of the first electrode region; and the third step: forming an electrical on the epitaxial platform according to the electrical characteristics of the diode element The layer is used to complete the electrical fabrication of the second electrode region; and the fourth step: after coating a surface of the substrate on the first electrode region and the surface of the second electrode region with a metal layer, each of the diode element regions Wai reserved scribe position to be cut. A method for fabricating a grain size packaged diode device having an ultra-low forward voltage, characterized in that all regions other than the second electrode are directly used as a first electrode, so that the first electrode is free of an epitaxial layer or a diffusion layer The method includes the following steps: the first step is divided into a plurality of diode element regions on a front surface of a slice of the wafer, and a scribe line and a inner circumference are disposed on a periphery of each of the diode element regions. An electrode region, and each of the diode element regions is entirely used as a first electrode region at a position other than the second electrode region; and a second step: epitaxially forming a surface of the first electrode region in each of the diode element regions The layer is completely removed to expose the substrate, and the remaining epitaxial layer of the second electrode region forms an epitaxial platform, so that all regions except the epitaxial platform of the substrate are electrical ranges of the first electrode region; Forming an electrical layer on the epitaxial platform of the second electrode region according to electrical characteristics of the diode element to complete electrical fabrication of the second electrode region; and fourth step: facing the surface of the substrate in the first electrode region and Two electrode Rear surface of the electric layer of cladding a metal layer, respectively, from the surrounding region of each diode element location reserved scribe Cut it. A method for fabricating a grain size packaged diode device having an ultra-low forward voltage, characterized in that all regions other than the second electrode are directly used as a first electrode, so that the first electrode is free of an epitaxial layer or a diffusion layer The method comprises the following steps: a first step: dividing a plurality of diode element regions on a front surface of a slice of the wafer, and arranging a cutting channel and a inner circumference for each of the diode element regions a second electrode region, and each of the diode element regions is entirely used as a first electrode region at a position other than the second electrode region; and a second step: applying a second electrode to the second electrode region of each of the diode element regions The electrical characteristics of the body element are used to form an electrical layer to complete the electrical fabrication of the second electrode region; and the third step: removing the epitaxial layer of each of the diode element regions on the surface of the first electrode region to expose the substrate, so that The remaining epitaxial layer forms an epitaxial platform, and the second electrode region is constructed on the epitaxial platform and the electrical layer, and the substrate is the first electrode except for the epitaxial/diffusion platform and the electrical layer. District's electrical range The fourth step: after the surface of the substrate located in the first electrode region and the surface of the electrical layer of the second electrode region are respectively covered with a metal layer, the position of the cutting channel reserved around each of the diode element regions is cut. . A die-size packaged diode component having an ultra-low forward voltage, comprising at least: a substrate having a front surface and a back surface; a second electrode comprising an epitaxial platform above the front surface of the substrate, An electrical layer disposed on the epitaxial platform, a metal layer disposed above the electrical layer; and a first electrode formed of all substrates except the second electrode, the first electrode further including a cladding layer A metal layer in the entire area of the front surface of the substrate except for the second electrode. A grain size packaged diode device having an ultra-low forward voltage according to claim 4, wherein the first electrode and/or the second electrode are further provided with a tin pad on the surface of the metal layer, and An insulating protective layer and/or a trench is disposed around the one electrode and/or the second electrode. A method for manufacturing a grain size packaged diode element having an ultra-low forward voltage, characterized in that all regions other than the second electrode are directly used as a first electrode, and the first electrode is The positive front side is perforated and turned on, so that the first electrode does not need to be turned on by the epitaxial layer or the diffusion layer. The method comprises the following steps: the first step: dividing the front surface of a stretch wafer/diffused germanium wafer into multiple a diode element region, a scribe line is disposed on a periphery of each of the diode element regions, and a second electrode region is disposed in the inner circumference, and each of the diode element regions is disposed at a position other than the second electrode region thereof. a first electrode region; a second step: forming an electrical layer on the second electrode region of each of the diode element regions according to electrical characteristics of the diode device to complete electrical fabrication of the second electrode region; : performing perforation on the front and back sides of the stretched wafer/diffusion wafer in the first electrode region, and filling a metal conductive material into the through hole to form a conduction channel; and fourth step: the first electrode is located at the first electrode The surface of the region and the surface of the electrical layer of the second electrode region are respectively covered with a metal layer, so that the metal layer of the first electrode region is electrically connected to the conduction channel, and then the cutting is reserved around each of the diode element regions. The track position is cut. A die-size packaged diode component having an ultra-low forward voltage, comprising at least: a diode body body cut from a bump wafer/diffused germanium wafer, the diode body body comprising a layer a substrate/diffused crystal plate on the back side and a layer of epitaxial/diffusion layer on the front side; a second electrode comprising an electrical layer on the epitaxial/diffusion layer, and a metal layer disposed above the electric layer; a first electrode comprising a metal layer overlying the entire area of the epitaxial/diffusion layer except the second electrode, and a back substrate/diffused crystal plate of the diode body body extending through the front surface The perforation of the crystal/diffusion layer is filled with a conductive material electrically conductive to the metal layer of the first electrode to form a conduction channel. A grain size packaged diode device having an ultra-low forward voltage according to claim 7, wherein the first electrode and/or the second electrode are further provided with a tin pad on the surface of the metal layer, and the first An insulating protective layer and/or a trench is disposed around the electrode and/or the second electrode.