CN107611121A - 用于静电放电保护的半导体结构 - Google Patents

用于静电放电保护的半导体结构 Download PDF

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CN107611121A
CN107611121A CN201610541426.7A CN201610541426A CN107611121A CN 107611121 A CN107611121 A CN 107611121A CN 201610541426 A CN201610541426 A CN 201610541426A CN 107611121 A CN107611121 A CN 107611121A
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semiconductor structure
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CN107611121B (zh
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黄崇佑
邱厚荏
唐天浩
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United Microelectronics Corp
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Abstract

本发明公开一种用于静电放电保护的半导体结构，其包括一基板、一第一掺杂阱、一源极掺杂区域、一漏极掺杂区域以及一栅极结构。第一掺杂阱设置于基板内，且具有一第一导电型。源极掺杂区域设置于基板内，且具有一第二导电型，第二导电型与第一导电型相反。漏极掺杂区域设置于基板内，且具有第二导电型。栅极结构设置于基板上，且位于源极掺杂区域与漏极掺杂区域之间。栅极结构与源极掺杂区域分开。

Description

用于静电放电保护的半导体结构
技术领域
本发明涉及一种半导体结构，且特别是涉及一种用于静电放电(electrostatic discharge,ESD)保护的半导体结构。
背景技术
芯片及/或集成电路(integrated circuit,IC)为现代资讯社会中最重要的硬件基础。随着芯片及/或集成电路的尺寸持续缩小，在互补式金属氧化物半晶体管(complementary metal oxide semiconductor,CMOS)的技术中，较浅的接面深度(junction depth)、更薄的栅极氧化层(gate oxide)的厚度，加入轻掺杂的漏极(light doped drain,LDD)、浅沟槽隔离(shallow trenchisolation,STI)，以及自对准金属硅化物(self-aligned silicide)等制作工艺已成为标准制作工艺。但是上述的制作工艺却使得集成电路产品更容易遭受静电放电(electrostatic discharge,ESD)的损害。因此，芯片及/或集成电路中需要加入静电放电的防护电路设计，来保护集成元件电路。
发明内容
本发明的目的在于提供一种半导体结构，通过在源极侧的结构设计，能防止静电放电造成的损伤，有效提升半导体结构的耐久性(robustness)，且不需要使用额外的光掩模，有效控制半导体结构的制造成本。
根据本发明的一方面，提出一种半导体结构，包括一基板、一第一掺杂阱、一源极掺杂区域、一漏极掺杂区域以及一栅极结构。第一掺杂阱设置于基板内，且具有一第一导电型。源极掺杂区域设置于基板内，且具有一第二导电型，第二导电型与第一导电型相反。漏极掺杂区域设置于基板内，且具有第二导电型。栅极结构设置于基板上，且位于源极掺杂区域与漏极掺杂区域之间。栅极结构与源极掺杂区域分开。
为让本发明的上述内容能更明显易懂，下文特举实施例，并配合所附附图，作详细说明如下：
附图说明
图1A为本发明一实施例的半导体结构的俯视图；
图1B为沿着图1A中的A-A’线所切的半导体结构的部分剖视图；
图2为本发明另一实施例的半导体结构的部分剖视图；
图3为本发明一实施例的半导体结构的部分剖视图；
图4为本发明另一实施例的半导体结构的部分剖视图；
图5为本发明又一实施例的半导体结构的部分剖视图。
主要元件符号说明
100、101、102、103、104：半导体结构
11：基板
13：第一掺杂阱
14：第二掺杂阱
21：源极掺杂区域
23：漏极掺杂区域
25：栅极结构
31、32：浅沟槽隔离
33：重掺杂区域
34：第一掺杂区域
35：轻掺杂漏极
36：轻掺杂区域
d：栅极结构与源极掺杂区域之间的距离
具体实施方式
以下是参照所附附图详细叙述本发明的实施态样。需注意的是，实施例所提出的结构和内容仅为举例说明之用，本发明欲保护的范围并非仅限于所述的态样。实施例中相同或类似的标号用以标示相同或类似的部分。需注意的是，本发明并非显示出所有可能的实施例。可在不脱离本发明的精神和范围内对结构加以变化与修饰，以符合实际应用所需。因此，未于本发明提出的其他实施态样也可能可以应用。再者，附图已简化以利清楚说明实施例的内容，附图上的尺寸比例并非按照实际产品等比例绘制。因此，说明书和附图内容仅作叙述实施例之用，而非作为限缩本发明保护范围之用。
图1A绘示本发明一实施例的半导体结构100的俯视图。图1B绘示沿着图1A中的A-A’线所切的半导体结构100的部分剖视图。要注意的是，为了更清楚绘示半导体结构100内部的元件之间的关系，可能会省略部分元件。
如图1A、图1B所示，半导体结构100包括一基板11、一第一掺杂阱13、一源极掺杂区域21、一漏极掺杂区域23以及一栅极结构25。第一掺杂阱13、源极掺杂区域21及漏极掺杂区域23设置于基板11内，栅极结构25设置于基板11上。
再者，源极掺杂区域21与漏极掺杂区域23设置于第一掺杂阱13内，而栅极结构25设置于第一掺杂阱13上且位于源极掺杂区域21与漏极掺杂区域23之间。
在本发明实施例中，栅极结构25可直接接触漏极掺杂区域23，但与源极掺杂区域21分开。也就是说，栅极结构25与源极掺杂区域21之间可具有一间距(interval)。在一实施例中，栅极结构25与源极掺杂区域21之间的距离d可例如介于0.1～1μm。然而，本发明并未限定于此。
在一实施例中，第一掺杂阱13例如为一高压阱(HV well)，具有一第一导电型，例如为P型；源极掺杂区域21与漏极掺杂区域23具有一第二导电型，第二导电型与第一导电型相反，例如为N型。
此外，如图1B所示，半导体结构100可还包括一浅沟槽隔离(shallowtrench isolation,STI)31、一重掺杂区域33及一轻掺杂漏极(lightly doped drain,LDD)35，设置于第一掺杂阱13内。举例来说，重掺杂区域33例如具有第一导电型，且重掺杂区域33的浓度大于第一掺杂阱13的浓度。轻掺杂漏极35可例如围绕漏极掺杂区域23。
一般而言，较低的维持电压(holding voltage,Vh)可使元件具有较佳的静电放电耐受度(ESD robustness)，但若元件的维持电压(Vh)值小于集成电路的正常工作电压(VDD)，一旦元件在正常操作情况下因外在杂讯干扰而被误触发，将造成闩锁效应(Latch Up)而毁损集成电路产品。
因此，为了有效提供内部电路适当的静电放电防护能力，并避免闩锁效应发生的可能，理想的静电放电防护元件，其电压-电流应落在理想静电放电防护设计区间(ESD Protection Window)内。
在高压制作工艺中，由于金属氧化物半晶体管所应用的正常工作电压(VDD)较高，导致维持电压(Vh)较难达到高于正常工作电压(VDD)，因此，高压金属氧化物半晶体管元件在闩锁效应防治上更为困难。通过本发明实施例的半导体结构(亦即，栅极结构25与源极掺杂区域21分开)，在高压制作工艺中可提升元件的维持电压，以增进高压集成电路产品对闩锁效应的抵抗能力。
要注意的是，前述实施例中栅极结构25与源极掺杂区域21之间的距离d可介于0.1～1μm，但此距离d会直接影响维持电压(Vh)，因此栅极结构25与源极掺杂区域21之间的距离d不会受限于此范围。此外，本发明的半导体结构实施例并未限定于图1A、图1B所绘示的结构。
图2绘示本发明另一实施例的半导体结构101的部分剖视图。半导体结构101的俯视图可类似于图1A所绘示半导体结构100的俯视图。此外，半导体结构101与图1A、图1B所绘示半导体结构100具有类似的元件，这些类似的元件将以相同的元件标号标示。
类似地，半导体结构101包括一基板11、一第一掺杂阱13、一源极掺杂区域21、一漏极掺杂区域23以及一栅极结构25。第一掺杂阱13、源极掺杂区域21及漏极掺杂区域23设置于基板11内，栅极结构25设置于基板11上。
再者，源极掺杂区域21与漏极掺杂区域23设置于第一掺杂阱13内，而栅极结构25设置于第一掺杂阱13上且位于源极掺杂区域21与漏极掺杂区域23之间。
如图2所示，半导体结构101还包括一第二掺杂阱14，第二掺杂阱14设置于基板11内。此外，至少部分第二掺杂阱14设置于源极掺杂区域21与栅极结构25之间。也就是说，栅极结构25可通过第二掺杂阱14与源极掺杂区域21分开。
在本实施例中，源极掺杂区域21与漏极掺杂区域23具有一第二导电型，例如为N型。此外，第二掺杂阱14同样具有第二导电型，且第二掺杂阱14的浓度小于源极掺杂区域21的浓度。也就是说，第二掺杂阱14可例如唯一淡掺杂高压N阱，但本发明并未限定于此。
如图2所示，第二掺杂阱14可围绕源极掺杂区域21。要注意的是，第二掺杂阱14的位置并未限定于图2所绘示的位置。在某些实施例中，第二掺杂阱14也可仅设置于源极掺杂区域21与栅极结构25之间，并未围绕源极掺杂区域21。
再者，栅极结构25与源极掺杂区域21之间的距离d可视设计需求而调整。下表一记录在不同的距离d下，半导体结构101的触发电压(TriggerVoltage,Vt1)与维持电压(Vh)。要注意的是，栅极结构25与源极掺杂区域21之间的距离d为0时，可视为本发明实施例的半导体结构101的一对照结构。
表一
如表一所示，栅极结构25与源极掺杂区域21之间的距离d不为0时，半导体结构101的维持电压(Vh)皆大于对照结构(即栅极结构25与源极掺杂区域21之间的距离d为0)的维持电压(Vh)。
此外，大体而言，随着栅极结构25与源极掺杂区域21之间的距离d增加，半导体结构101的维持电压(Vh)也会跟着增加。但触发电压(Vt1)几乎没有改变。也就是说，通过本发明实施例的半导体结构(亦即，栅极结构25与源极掺杂区域21分开)可提升元件的维持电压，但不影响高压集成电路产品的其他操作表现。
图3绘示本发明一实施例的半导体结构102的部分剖视图。半导体结构102的俯视图可类似于图1A所绘示半导体结构100的俯视图。此外，半导体结构102与图2所绘示半导体结构101具有类似的元件，这些类似的元件将以相同的元件标号标示，在此不多加赘述。
如图3所示，半导体结构102还包括一浅沟槽隔离32，浅沟槽隔离32设置于第二掺杂阱14内。在本实施例中，浅沟槽隔离32可位于源极掺杂区域21与栅极结构25之间。
图4绘示本发明另一实施例的半导体结构103的部分剖视图。半导体结构103的俯视图可类似于图1A所绘示半导体结构100的俯视图。此外，半导体结构103与图2所绘示半导体结构101具有类似的元件，这些类似的元件将以相同的元件标号标示，在此不多加赘述。
如图4所示，半导体结构103还包括一第一掺杂区域34，第一掺杂区域34设置于第二掺杂阱14内。在一实施例中，第一掺杂区域34具有该第一导电型，例如为P型。此外，第一掺杂区域34的浓度可大于第一掺杂阱13的浓度。也就是说，第一掺杂区域34可例如为一P型重掺杂区域。在本实施例中，第一掺杂区域34位于源极掺杂区域21与栅极结构25之间。
虽然图2～图4所绘示的半导体结构101、102、103皆包括第二掺杂阱14，但本发明并未限定于此。
图5绘示本发明又一实施例的半导体结构104的部分剖视图。类似地，半导体结构104的俯视图可类似于图1A所绘示半导体结构100的俯视图。此外，半导体结构104与第1A、1B图所绘示半导体结构100具有类似的元件，这些类似的元件将以相同的元件标号标示。
如图5所示，半导体结构104还包括一轻掺杂区域36，轻掺杂区域36设置于第一掺杂阱13内。在本实施例中，轻掺杂区域36围绕源极掺杂区域21，且轻掺杂区域36可例如为轻掺杂漏极(LDD)。
承上述实施例，本发明的用于静电放电保护的半导体结构，通过将栅极结构与源极掺杂区域分开的设计，在高压制作工艺中可提升元件的维持电压，以增进高压集成电路产品对闩锁效应的抵抗能力。同时，能防止静电放电造成的损伤，有效提升半导体结构的耐久性，且不需要使用额外的光掩模，有效控制半导体结构的制造成本。
综上所述，虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明。本发明所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作各种的更动与润饰。因此，本发明的保护范围应以附上的权利要求所界定的为准。

Claims (10)

1.一种用于静电放电保护的半导体结构，其特征在于，该半导体结构包括：
基板；
第一掺杂阱，设置于该基板内，且具有第一导电型；
源极掺杂区域，设置于该基板内，且具有第二导电型，该第二导电型与该第一导电型相反；
漏极掺杂区域，设置于该基板内，且具有该第二导电型；以及
栅极结构，设置于该基板上，且位于该源极掺杂区域与该漏极掺杂区域之间；
其中该栅极结构直接接触该漏极掺杂区域且与该源极掺杂区域分开。
2.如权利要求1所述的半导体结构，还包括第二掺杂阱，其中至少部分该第二掺杂阱设置于该源极掺杂区域与该栅极结构之间。
3.如权利要求2所述的半导体结构，其中该第二掺杂阱具有该第二导电型，且该第二掺杂阱的浓度小于该源极掺杂区域的浓度。
4.如权利要求2所述的半导体结构，其中该第二掺杂阱围绕该源极掺杂区域。
5.如权利要求2所述的半导体结构，还包括：
第一掺杂区域，设置于该第二掺杂阱内；
其中该第一掺杂区域具有该第一导电型。
6.如权利要求5所述的半导体结构，其中该第一掺杂区域的浓度大于该第一掺杂阱的浓度。
7.如权利要求5所述的半导体结构，其中该第一掺杂区域位于该源极掺杂区域与该栅极结构之间。
8.如权利要求2所述的半导体结构，还包括：
浅沟槽隔离，设置于该第二掺杂阱内；
其中该浅沟槽隔离位于该源极掺杂区域与栅极结构之间。
9.如权利要求1所述的半导体结构，还包括：
轻掺杂区域，围绕该源极掺杂区域。
10.如权利要求1所述的半导体结构，其中该栅极结构与该源极掺杂区域的距离介于0.1～1μm。
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