CN107611007A - The pre-cleaning method and 3D NAND preparation technologies of a kind of deep trench - Google Patents
The pre-cleaning method and 3D NAND preparation technologies of a kind of deep trench Download PDFInfo
- Publication number
- CN107611007A CN107611007A CN201710732699.4A CN201710732699A CN107611007A CN 107611007 A CN107611007 A CN 107611007A CN 201710732699 A CN201710732699 A CN 201710732699A CN 107611007 A CN107611007 A CN 107611007A
- Authority
- CN
- China
- Prior art keywords
- etching
- plasma
- deep trench
- cleaning method
- reaction cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention provides a kind of pre-cleaning method of deep trench, comprise the following steps：Processed part with deep trench is provided, and is placed in reaction cavity；Gas is passed through into the reaction cavity, and forms etching plasma；Plasma etching is carried out to the deep trench of the processed part using the etching plasma；After plasma etching the temperature of maintenance reaction cavity within the specific limits a period of time.The present invention passes through special plasma etching, remove effectively and uniformly the impurity such as natural oxide (native oxide) and the non-single silicon (amorphous silicon) of zanjon trench bottom, so as to obtain more preferable growing epitaxial silicon effect, and then improve the current capacity of polysilicon trench, the performance of access flash memories device is significantly improved, and product yield is obviously improved.
Description
Technical field
The present invention relates to deep trench in a kind of pre-cleaning techniques of deep trench, more particularly to a kind of 3D NAND flash memory structures
Plasma etching pre-cleaning techniques and 3D NAND flash memory structures preparation technology.
Background technology
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges：Physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty and most ask being produced into for lower unit storage unit that planar flash memory runs into
This, a variety of three-dimensional (3D) flash memories structures are arisen at the historic moment, such as 3D NOR (3D or non-) flash memories and 3D NAND
(3D with non-) flash memory.
Wherein, storage element is used three dimensional pattern stacked in multi-layers by 3D NAND using its small size, Large Copacity as starting point
It is highly integrated be design concept, produce high unit area storage density, the memory of efficient storage unit performance, into
The prevailing technology designed and produced for emerging memory.
In industrial manufacturing process in 3D NAND technologies, the surface of silicon for being typically employed in channel bottom forms silicon
Epitaxial layer (silicon epitaxygrowth, abbreviation SEG) technique, makes the polysilicon trench of trenched side-wall fully connect with substrate
Connect, form electronics groove, therefore it is particularly important step to form preparation of the silicon epitaxy layer for 3D NAND.And in extension work
Before skill, generally require and first remove the natural oxidizing layers (native oxide) such as the silica of semiconductor substrate surface and be etched
The impurity such as the silicon layer (damaged silicon by etching) of destruction, prepare the silicon table of cleaning for follow-up epitaxial growth
Surface state, otherwise, the problems such as influenceing subsequent epitaxial growth uniformity just occurs.The currently used removing natural oxidizing layer of going
Method mainly includes ammonium hydroxide and the aqueous solution wet method prerinse (SC1wet clean) of hydrogen peroxide and diluted hydrofluoric acid wet method
Wet method prerinse (wet pre-clean) including prerinse (DHF wet clean) etc..
However as in 3D nand flash memories O/N (Oxide/Nitride) stack stacking number it is more and more (such as up to
To 64 layer stacks or more) so that the gash depth formed in three-dimensional storage is increasing, and because liquid has surface
Power, traditional wet method prerinse (wet pre-clean) for high-aspect-ratio (>60) deep trench (deep trench) bottom
Cleaning performance have certain limitation, liquid is difficult to the natural oxide (native oxide) on base substrate surface and non-
Crystal silicon (amorphous silicon) etc. does thorough removing.The cleaning performance being mainly manifested between different grooves has differences, most
The uniformity of SEG height is caused to be deteriorated eventually.
Therefore, how effectively and uniformly deep trench (deep trench) to be cleaned, is always those skilled in the art
Endeavour the direction of research.
The content of the invention
It is an object of the invention to provide a kind of pre-cleaning method of deep trench, can obtain uniformly and effectively cleaning effect
Fruit, so as to improve the performance of the electronic component with deep trench such as 3D nand flash memories.
To achieve these goals, the present invention proposes a kind of pre-cleaning method of deep trench, it is characterised in that：Including with
Lower step：
Processed part with deep trench is provided, and is placed in reaction cavity；
Gas is passed through into the reaction cavity, and forms etching plasma；
Plasma etching is carried out to the deep trench of the processed part using the etching plasma；
After plasma etching the temperature of maintenance reaction cavity within the specific limits a period of time.
Further, it is to pass first into ammonia (NH to be passed through gas into the reaction cavity3) and nitrogen (N2) mixing
Gas is passed through Nitrogen trifluoride (NF again after for a period of time3)。
Further, the etching plasma is reacted by following reaction equations and formed：
N2+NH3→H*+NH* (1)
H*+NF3→NHxFy (2)
Further, it is to be passed through ammonia (NH to be passed through gas into the reaction cavity3) and Nitrogen trifluoride (NF3) it is mixed
Close gas.
Further, the processed part has multiple deep trench.
Further, the processed part is the part that then carry out growing epitaxial silicon.
Further, the processed part is the part with multilayer O/N (Oxide/Nitride) stacked structure.
Further, the condition of the plasma etching is plasma source power 2500-3000W, etching gas it is total
Flow is 1.5-4slm, and etching air pressure is 1.5-2.5Torr, etch period 30-60min.
Further, the temperature of the maintenance reaction cavity is 180-220 DEG C.
The invention also provides a kind of 3D NAND preparation technologies, comprise the following steps：
Prerinse is carried out to deep trench, the prerinse comprises the following steps, there is provided have deep trench be used for prepare 3D
The NAND part with multilayer O/N (Oxide/Nitride) stacked structure, and be placed in reaction cavity；To described anti-
Answer and gas is passed through in cavity, and form etching plasma；Institute using the etching plasma to the processed part
State deep trench and carry out plasma etching；After plasma etching the temperature of maintenance reaction cavity within the specific limits a period of time；
Surface of silicon after prerinse carries out growing epitaxial silicon so that polysilicon trench is fully connected with substrate, shape
Into electronics groove.
The invention also provides the 3D nand flash memories that a kind of above-mentioned 3D NAND preparation technologies are prepared.
The present invention mainly make use of following reaction equation：
N2+NH3→H*+NH* (1)
H*+NF3→NHxFy (2)
NHxFy+SiO2→(NH4)2SiF6 (3)
Then solid-state (NH is passed through4)2SiF6, can be natural by the silica of zanjon trench bottom well in the distillation of high temperature
Oxide layer is got rid of by plasma etching prerinse, so as to obtain clean quiet substrate surface, is given birth to carrying out follow-up silicon epitaxy
It is long.
Compared with prior art, the beneficial effects are mainly as follows：By special plasma etching, effectively simultaneously
And the uniform natural oxide (native oxide) and non-crystalline silicon (amorphous silicon) for removing zanjon trench bottom
Deng impurity, so as to obtain more preferable growing epitaxial silicon effect, and then improve the current capacity of polysilicon trench, significantly improve
The performance of flash memories device is accessed, and product yield is obviously improved.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area
Technical staff will be clear understanding.Accompanying drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention
Limitation.And in whole accompanying drawing, identical part is denoted by the same reference numerals.In the accompanying drawings：
Fig. 1 is the principle schematic for carrying out prerinse key step in the present invention to deep trench；
Fig. 2 a are the stereoscan photograph of the SEG after wet method prerinse processing in comparative example of the present invention；
Fig. 2 b are the stereoscan photograph of the SEG after plasma etching prerinse processing in the embodiment of the present invention.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in accompanying drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs
The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expended
Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that accompanying drawing is using very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
In one embodiment of the invention, it is proposed that a kind of to include the 3D NAND that prerinse step is carried out to deep trench
The preparation method of flash memory, comprises the following steps：
S100, prerinse being carried out to deep trench, the prerinse comprises the following steps,
S110, there is provided be used to prepare being stacked with multilayer O/N (Oxide/Nitride) for 3D NAND with deep trench
The part of structure, and be placed in reaction cavity；
S120, gas is passed through into the reaction cavity, and forms etching plasma；
S130, plasma etching is carried out to the deep trench of the processed part using the etching plasma；
S140, the temperature of maintenance reaction cavity a period of time within the specific limits after plasma etching；
S200, the surface of silicon after prerinse carry out growing epitaxial silicon so that polysilicon trench fully connects with substrate
Connect, form electronics groove.
Specifically, Fig. 2 a are refer to, in S100 steps,
First, carry out S110 steps, there is provided with deep trench for prepare 3D NAND with multilayer O/N
(Oxide/Nitride) part of stacked structure, and be placed in reaction cavity；
S120 steps are then carried out, being passed through gas into the reaction cavity is, specifically first carries out step S121, i.e.,
Pass first into ammonia (NH3) and nitrogen (N2) mixed gas for a period of time；Step S122 is then carried out, is passed through Nitrogen trifluoride
(NF3)；In S120 steps, the reaction refers to form plasma 1 in the condition that ion source power is 2500-3000W, such as
Following formula (1) and (2)：
N2+NH3→H*+NH* (1)
H*+NF3→NHxFy (2)
The step of being passed through reacting gas by above-mentioned two step can form plasma 1NHxFy(such as including NH4F,
NH4FHF etc. active materials), so as to which highly efficient removes removing natural oxidizing layer 2, and deep trench is avoided to a certain extent
Trench wall is destroyed by plasma.
S130 steps are then carried out, the deep trench of the processed part is carried out using the etching plasma
Plasma etching, the condition of specific plasma etching are plasma source power 2500-3000W, the total flow of etching gas
For 1.5-4slm, etching air pressure is 1.5-2.5Torr, etch period 30-60min；In S130 steps, by reacting as follows
Silica natural oxidizing layer is reacted generation (NH by formula (3)4)2SiF6Layer 3：
NHxFy+SiO2→(NH4)2SiF6 (3)
While the condition of above-mentioned plasma etching can ensure that the impurity such as natural oxidizing layer are removed efficiently, avoid as far as possible
Destroyed for the trench wall of deep trench by plasma；In order to optimize the effect above, preferably plasma source power is
2800W, the total flow of etching gas is 3slm, and etching air pressure is 2Torr, etch period 40min.
S140 steps are then carried out, the temperature of maintenance reaction cavity is one section in the range of 180-220 DEG C after plasma etching
Time, until (NH4)2SiF6All distillation removes；Preferable temperature is 200 DEG C, to ensure (NH4)2SiF6Abundant distillation.
S200 steps are then carried out, the surface of silicon 4 after prerinse carries out growing epitaxial silicon so that polysilicon trench
Fully it is connected with substrate, forms electronics groove.
SEG stereoscan photograph is referring to Fig. 2 b after this embodiment of the invention prerinse processing.
In another embodiment of the present invention, difference essentially consists in, when carrying out step S120, be passed directly into
Ammonia (NH3) and Nitrogen trifluoride (NF3) mixed gas, reaction generation plasma, rather than using substep be passed through three kinds of gases
Mode, remaining step is identical with previous embodiment.
In the comparative example of the present invention, a kind of 3D NAND sudden strains of a muscle for including and prerinse step being carried out to deep trench are also provided
The preparation method deposited, comprises the following steps：
S100 ', prerinse is carried out to deep trench, the prerinse is, using the ammonium hydroxide of routine and the water of hydrogen peroxide
Solution wet method prerinse (SC1wet clean)；
S200 ', the surface of silicon after prerinse carry out growing epitaxial silicon so that polysilicon trench fully connects with substrate
Connect, form electronics groove.
SEG stereoscan photograph is referring to Fig. 2 a after comparative example prerinse processing of the invention.
Comparison diagram 2a and Fig. 2 b it is seen that, through prerinse of the present invention processing after SEG high homogeneity apparently higher than
The prewashed situation of conventional wet.
To sum up, in the preparation method of 3D nand flash memories provided in an embodiment of the present invention, employ special plasma and carve
Erosion, remove effectively and uniformly the natural oxide (native oxide) and non-crystalline silicon (amorphous of zanjon trench bottom
The impurity such as silicon), so as to obtain more preferable growing epitaxial silicon effect, and then improve the current capacity of polysilicon trench,
The performance of access flash memories device is significantly improved, and product yield is obviously improved.
In addition, the present invention deep trench pre-cleaning method, both can as previously described be applied to 3D nand memories EPI or
Prerinse processing before polycrystalline silicon channel growth, before EPI or polycrystalline silicon growth can also be needed applied to all storage chips
Prerinse is handled, and should be said, it is the prerinse that one kind can apply to all deep trench (deep trench) structural base
Technique.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Enclose and be defined.
Claims (11)
1. a kind of pre-cleaning method of deep trench, it is characterised in that comprise the following steps：
Processed part with deep trench is provided, and is placed in reaction cavity；
Gas is passed through into the reaction cavity, and forms etching plasma；
Plasma etching is carried out to the deep trench of the processed part using the etching plasma；
After plasma etching the temperature of maintenance reaction cavity within the specific limits a period of time.
A kind of 2. pre-cleaning method according to claim 1, it is characterised in that：
It is to pass first into ammonia (NH to be passed through gas into the reaction cavity3) and nitrogen (N2) mixed gas for a period of time after
Nitrogen trifluoride (NF is passed through again3)。
A kind of 3. pre-cleaning method according to claim 2, it is characterised in that：
The etching plasma is reacted by following reaction equations to be formed：
N2+NH3→H*+NH* (1)
H*+NF3→NHxFy (2)。
A kind of 4. pre-cleaning method according to claim 1, it is characterised in that：
It is to be passed through ammonia (NH to be passed through gas into the reaction cavity3) and Nitrogen trifluoride (NF3) mixed gas.
A kind of 5. pre-cleaning method according to claim 1, it is characterised in that：
The processed part has multiple deep trench.
A kind of 6. pre-cleaning method according to claim 1, it is characterised in that：The processed part is then to carry out
The part of growing epitaxial silicon.
A kind of 7. pre-cleaning method according to claim 1, it is characterised in that：The processed part is with multilayer O/
The part of N (Oxide/Nitride) stacked structure.
A kind of 8. pre-cleaning method according to claim 1, it is characterised in that：The condition of the plasma etching is, etc.
Ion source power is 2500-3000W, and the total flow of etching gas is 1.5-4slm, and etching air pressure is 1.5-2.5Torr, etching
Time is 30-60min.
A kind of 9. pre-cleaning method according to claim 1, it is characterised in that：The temperature of the maintenance reaction cavity is
180-220℃。
10. a kind of 3D NAND preparation technologies, comprise the following steps：
Prerinse is carried out to deep trench, the prerinse comprises the following steps, there is provided have deep trench be used for prepare 3D NAND
The part with multilayer O/N (Oxide/Nitride) stacked structure, and be placed in reaction cavity；To the reaction chamber
Gas is passed through in body, and forms etching plasma；The depth using the etching plasma to the processed part
Groove carries out plasma etching；After plasma etching the temperature of maintenance reaction cavity within the specific limits a period of time；
Surface of silicon after prerinse carries out growing epitaxial silicon so that polysilicon trench is fully connected with substrate, forms electricity
Sub-trenches.
11. a kind of 3D NAND flash memory structures, it is prepared as the 3D NAND preparation technologies described in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710732699.4A CN107611007A (en) | 2017-08-24 | 2017-08-24 | The pre-cleaning method and 3D NAND preparation technologies of a kind of deep trench |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710732699.4A CN107611007A (en) | 2017-08-24 | 2017-08-24 | The pre-cleaning method and 3D NAND preparation technologies of a kind of deep trench |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107611007A true CN107611007A (en) | 2018-01-19 |
Family
ID=61065747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710732699.4A Pending CN107611007A (en) | 2017-08-24 | 2017-08-24 | The pre-cleaning method and 3D NAND preparation technologies of a kind of deep trench |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107611007A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166857A (en) * | 2018-09-03 | 2019-01-08 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1893016A (en) * | 2005-04-21 | 2007-01-10 | 海力士半导体有限公司 | Method for forming contact of semiconductor device using solid phase epitaxy |
| CN101231951A (en) * | 2007-01-11 | 2008-07-30 | 应用材料股份有限公司 | Oxide etch with NH3-NF3 chemical |
| CN101903984A (en) * | 2007-12-21 | 2010-12-01 | 应用材料股份有限公司 | Passivation layer formation by plasma clean process to reduce native oxide growth |
| US20110240600A1 (en) * | 2009-03-26 | 2011-10-06 | Ulvac ,Inc. | Vacuum processing method and vacuum processing apparatus |
| CN103718273A (en) * | 2011-08-02 | 2014-04-09 | 株式会社Eugene科技 | Equipment for manufacturing semiconductor for epitaxial process |
| CN103824746A (en) * | 2008-11-24 | 2014-05-28 | 应用材料公司 | Method and apparatus for trench and via profile modification |
| CN105390389A (en) * | 2014-08-29 | 2016-03-09 | 朗姆研究公司 | Contact clean in high-aspect ratio structures |
| US20170207103A1 (en) * | 2016-01-14 | 2017-07-20 | Tokyo Electron Limited | Gas phase etch of amorphous and poly-crystalline silicon from high aspect ratio features with high selectivity towards various films |
-
2017
- 2017-08-24 CN CN201710732699.4A patent/CN107611007A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1893016A (en) * | 2005-04-21 | 2007-01-10 | 海力士半导体有限公司 | Method for forming contact of semiconductor device using solid phase epitaxy |
| CN101231951A (en) * | 2007-01-11 | 2008-07-30 | 应用材料股份有限公司 | Oxide etch with NH3-NF3 chemical |
| CN101903984A (en) * | 2007-12-21 | 2010-12-01 | 应用材料股份有限公司 | Passivation layer formation by plasma clean process to reduce native oxide growth |
| CN103824746A (en) * | 2008-11-24 | 2014-05-28 | 应用材料公司 | Method and apparatus for trench and via profile modification |
| US20110240600A1 (en) * | 2009-03-26 | 2011-10-06 | Ulvac ,Inc. | Vacuum processing method and vacuum processing apparatus |
| CN103718273A (en) * | 2011-08-02 | 2014-04-09 | 株式会社Eugene科技 | Equipment for manufacturing semiconductor for epitaxial process |
| CN105390389A (en) * | 2014-08-29 | 2016-03-09 | 朗姆研究公司 | Contact clean in high-aspect ratio structures |
| US20170207103A1 (en) * | 2016-01-14 | 2017-07-20 | Tokyo Electron Limited | Gas phase etch of amorphous and poly-crystalline silicon from high aspect ratio features with high selectivity towards various films |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109166857A (en) * | 2018-09-03 | 2019-01-08 | 长江存储科技有限责任公司 | Semiconductor structure and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104900495B (en) | The preparation method of self-alignment duplex pattern method and fin formula field effect transistor | |
| CN108292602A (en) | Clean method | |
| CN102629559B (en) | Manufacture method of stacked gate SiC-metal insulator semiconductor (MIS) capacitor | |
| CN101752291B (en) | Method for making shallow groove isolation structure | |
| CN102117761B (en) | Wet process method for improving chamfer smoothness on top of shallow trench isolation | |
| CN107731735B (en) | SEG preparation process for improving SEG growth form through mild wet etching | |
| KR20130024691A (en) | Method and structure for advanced semiconductor channel substrate materials | |
| CN107706191A (en) | A kind of 3D nand flash memories raceway groove hole polysilicon articulamentum forming method | |
| CN103594337A (en) | A dual patterning method | |
| CN102339782B (en) | Production method of shallow channel isolation region | |
| CN107611007A (en) | The pre-cleaning method and 3D NAND preparation technologies of a kind of deep trench | |
| CN107658304A (en) | Prevent the 3D NAND preparation methods of SEG damages and the 3D nand flash memories of acquisition | |
| CN102243997A (en) | Process method for etching and cleaning oxide film in deep groove before epitaxial growth | |
| CN107611027A (en) | A kind of method for improving deep silicon etching sidewall roughness | |
| CN102403216B (en) | Wet etching method for preparation of super-junction device | |
| CN101894786A (en) | Method for preparing shallow trench isolation (STI) | |
| CN109346470A (en) | Three-dimensional storage and forming method thereof | |
| CN107968050A (en) | The bottom lithographic method in raceway groove hole | |
| CN110277313A (en) | The manufacturing method of side wall | |
| CN107731841A (en) | A kind of method of improvement 3D nand flash memory SEG growth qualities | |
| WO2019007346A1 (en) | Method for manufacturing semiconductor device having field plate structure with gradually varying thickness in trench | |
| CN106952911B (en) | The forming method of fin semiconductor devices | |
| CN111199881B (en) | Preparation method of semiconductor structure | |
| CN102412141A (en) | Method for removing oxide film residues in deep groove | |
| CN112542466A (en) | Three-dimensional memory manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180119 |