CN102403216B - Wet etching method for preparation of super-junction device - Google Patents

Wet etching method for preparation of super-junction device Download PDF

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Publication number
CN102403216B
CN102403216B CN 201010276031 CN201010276031A CN102403216B CN 102403216 B CN102403216 B CN 102403216B CN 201010276031 CN201010276031 CN 201010276031 CN 201010276031 A CN201010276031 A CN 201010276031A CN 102403216 B CN102403216 B CN 102403216B
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junction
super
deielectric
coating
epitaxial loayer
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CN102403216A (en
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杨华
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上海华虹Nec电子有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095Body region, i.e. base region, of DMOS transistors or IGBTs

Abstract

The invention discloses a wet etching method for preparation of a super-junction device, which includes firstly, forming an epitaxial layer on a silicon substrate, secondly, forming medium films on the front face and the back face of a silicon chip, thirdly, defining patterns on the front face by photoresist and opening the medium films by means of dry etching, fourthly, removing the photoresist and using the medium films as mask layers to form perpendicular deep grooves by means of wet anisotropic etching, fifthly, filling another epitaxial layer which is opposite to the epitaxial layer in the step one into the deep grooves to form a P-type structure and an N-type structure in an alternative array, sixthly, performing planarization by means of chemical mechanical polishing and standing on the medium films, seventhly, removing the medium films on the front face and the back face by means of wet etching, and eighthly, using mature longitudinal double-diffused metal-oxide semiconductor in the subsequent process to prepare a complete super-junction device. Using the wet etching method for preparation of the super-junction device has smaller damage to the silicon substrate, reduces defects of a PN junction surface and leakage current, and further can guarantee uniformity of perpendicular profiles of the deep grooves and the interior profiles of the faces and reduce production cost.

Description

Use wet etching to prepare the method for super-junction device

Technical field

The invention belongs to semiconductor integrated circuit and make the field, be specifically related to a kind of method of using wet etching to prepare super-junction device.

Background technology

Super-junction device is characterised in that P type semiconductor thin layer and the N type semiconductor thin layer that forms alternative arrangement, utilize P type semiconductor thin layer and N type semiconductor thin layer to exhaust, realize the principle that electric charge compensates mutually, make P type semiconductor thin layer and N type semiconductor thin layer can realize high puncture voltage under high-dopant concentration, thereby obtain simultaneously low on-resistance and high-breakdown-voltage.A kind of generation type of super-junction device structure is to open deep trench on the N-type epitaxial loayer, and then inserts P type extension, forms the P type of alternative arrangement and the structure of N-type.

In present technique, the deep plough groove etched dry etchings that adopt more, than being easier to the silicon substrate injury, and cost is also higher.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of method of using wet etching to prepare super-junction device, the method is less to the silicon substrate damage, can guarantee that follow-up outer layer growth quality is better, reduce the defective at PN junction interface, reduce leakage current, and can guarantee the uniformity of vertical profile and the interior pattern of face of deep trench, also can reduce production costs.

For solving the problems of the technologies described above, the invention provides a kind of method of using wet etching to prepare super-junction device, comprise the steps:

Step 1, the epitaxial loayer of growing up on silicon substrate;

Step 2 forms deielectric-coating simultaneously at the front and back of silicon chip;

Step 3, front define figure with photoresist, open deielectric-coating with the method for dry etching;

Step 4 is removed photoresist, utilizes deielectric-coating as mask layer, uses the wet method anisotropic etching to form vertical deep groove structure;

Step 5, the rear epitaxial loayer of filling the epitaxial loayer type opposite of growth and step 1 in deep trench of cleaning is with the P type of formation alternative arrangement and the structure of N-type;

Step 6 uses the method for chemico-mechanical polishing to carry out planarization, is parked on deielectric-coating;

Step 7 utilizes wet etching to remove the deielectric-coating of positive and negative, can form the structure of P type and N-type alternative arrangement;

Step 8, subsequent technique adopt ripe vertical double-diffused MOS can prepare complete super-junction device.

In step 1, the thickness of described epitaxial loayer is between the 5-80 micron.

In step 2, described formation deielectric-coating adopts the method for diffusion to form heat oxide film as deielectric-coating, and its thickness is between 1000 dusts-5000 dust; Perhaps adopt low-pressure chemical vapor deposition process formation oxide-film or nitride film as deielectric-coating, the thickness of oxide-film is between 2000 dusts-10000 dust, and the thickness of nitride film is between 100 dusts-500 dust.

It is the silicon substrate of high preferred orientation 110 at silicon substrate described in step 1, in step 3, define with photoresist figure, the design configuration opening of photolithography plate aligns with 111 crystal faces, this 111 crystal face refers to high preferred orientation 111, and this 111 crystal face is the crystal face of deep trench side in step 4.

In step 4, described removal photoresist adopts ashing or dioxysulfate aqueous mixtures to remove photoresist.

In step 4, the deielectric-coating at the back side plays the effect of protecting back side monocrystalline silicon, the vertical deep groove structure of positive formation, and the degree of depth of this deep trench is the 5-50 micron; Wet liquid medicine adopts the alkaline solution of potassium hydroxide, tetramethyl hydrogen-oxygen ammonium or ethylenediamine pyrocatechol, with the percentage by weight of deionized water be 1%-50%; Perhaps wet liquid medicine is used the admixing medical solutions of above-mentioned alkaline solution and isopropyl alcohol, and the percent by volume ratio of isopropyl alcohol and alkaline solution is 1%-30%.

If the epitaxial loayer of growing up in step 1 is P type epitaxial loayer, the epitaxial loayer of growing up in step 5 so is the N-type epitaxial loayer; If the epitaxial loayer of growing up in step 1 is the N-type epitaxial loayer, the epitaxial loayer of growing up in step 5 so is P type epitaxial loayer.

In step 5, the wet processing of dioxysulfate water+dilute hydrofluoric acid+ammoniacal liquor hydrogen peroxide+hydrochloric acid hydrogen peroxide is adopted in described cleaning.

In step 7, if deielectric-coating is oxide-film, wet liquid medicine is used buffer oxide film etching agent or hydrofluoric acid; If deielectric-coating is nitride film, wet liquid medicine is used hot phosphoric acid.

In step 8, subsequent technique comprises the steps:

A. the mode of using Implantation partly forms P well region, N+ well region and P+ source region at special pattern respectively;

B. use diffusion way to form grid oxygen, re-use the Low Pressure Chemical Vapor Deposition depositing polysilicon, and carry out dry etching, partly form polygate electrodes at special pattern;

C. use Low Pressure Chemical Vapor Deposition, aumospheric pressure cvd method or plasma reinforced chemical vapour deposition method to form the inter-level dielectric film, the kind of inter-level dielectric film is oxide-film, carry out subsequently dry etching, form polysilicon and the zone isolation of metal electrode and the contact hole of source region and metal electrode;

D. adopt the sputter physical vaporous deposition to form positive source metal electrode at front side of silicon wafer;

E. adopt the evaporating physical vapor deposition method to form the back side at silicon chip back side and leak metal electrode.

compared to the prior art, the present invention has following beneficial effect: utilization of the present invention on monocrystalline silicon due to the face of crystal face different orientation on the anisotropic etching that forms of wet-etch rate difference, utilize the method for wet etching to open vertical deep trench on the N-type epitaxial loayer, usually carry out anisotropic wet etching on the silicon substrate of high preferred orientation 110, can form vertical deep trench, the crystal face of deep trench side is 111, the benefit of doing like this is as follows: 1. wet etching is less to the silicon substrate damage, can guarantee that follow-up outer layer growth quality is better, reduce the defective at PN junction interface, reduce leakage current, 2. the production cost of wet etching is lower, 3. wet etching is controlled etch rate by high preferred orientation, can guarantee the uniformity of 90 vertical profiles of spending and the interior pattern of face of deep trench.

Description of drawings

Fig. 1 is the schematic flow sheet of the inventive method; Wherein,

Figure 1A is the schematic diagram after the inventive method step (1) is completed;

Figure 1B is the schematic diagram after the inventive method step (2) is completed;

Fig. 1 C is the schematic diagram after the inventive method step (3) is completed;

Fig. 1 D is the schematic diagram after the inventive method step (4) is completed;

Fig. 1 E is the schematic diagram after the inventive method step (5) is completed;

Fig. 1 F is the schematic diagram after the inventive method step (6) is completed;

Fig. 1 G is the schematic diagram after the inventive method step (7) is completed;

Fig. 2 is the structural representation that adopts the super-junction device of the inventive method preparation.

Wherein, are 1. N-type silicon substrate (110 crystal faces), the 2nd, N-type epitaxial loayer, the 3rd, deielectric-coating, the 4th, photoresist, the 5th, P type epitaxial loayer, the 6th, P well region, the 7th, N+ well region, the 8th, P+ source region, the 9th, inter-level dielectric film, the 10th, metal electrode, the 11st, positive source metal electrode, the 12nd, polysilicon, the 13rd, grid oxygen are leaked in the back side.

Embodiment

The present invention is further detailed explanation below in conjunction with drawings and Examples.

As depicted in figs. 1 and 2, the present invention's concrete steps of using wet etching to prepare the method for super-junction device comprise as follows:

(1) growth N-type epitaxial loayer 2 on the N-type silicon substrate 1 of 110 crystal faces (high preferred orientation 110), the thickness of N-type epitaxial loayer 2 is at the 5-80um(micron) between, see Figure 1A;

(2) front and back at silicon chip forms deielectric-coating 3 simultaneously, can use the method for diffusion to form heat oxide film as deielectric-coating 3, its thickness is between 1000 dusts-5000 dust, also can use the LPCVD(low-pressure chemical vapor deposition process) form oxide-film or nitride film as deielectric-coating 3, the thickness of oxide-film is between 2000 dusts-10000 dust, the thickness of nitride film can between 100 dusts-500 dust, be seen Figure 1B;

(3) front 4 definition figures with photoresist, the design configuration opening of photolithography plate and 111 crystal faces (high preferred orientation 111 is seen the crystal face of deep trench side in Fig. 1 C and Fig. 1 D) align, and open deielectric-coating 3 with the method for dry etching, see Fig. 1 C;

(4) remove photoresist 4, can use the ashing(ashing) or SPM(dioxysulfate water) mixture removes photoresist, utilize deielectric-coating 3 as mask layer, use the wet method anisotropic etching to form vertical deep groove structure, the deielectric-coating 3 at the back side plays the effect of protecting back side monocrystalline silicon, the vertical deep groove structure (degree of depth of deep trench can be 5um-50um) of positive formation, wet liquid medicine can be used KOH(potassium hydroxide), TMAH(tetramethyl hydrogen-oxygen ammonium) or the EDP(ethylenediamine pyrocatechol) etc. alkaline solution, with the percentage by weight of deionized water be 1%-50%, wet liquid medicine also can be used above-mentioned alkaline solution and IPA(isopropyl alcohol) admixing medical solutions, the percent by volume ratio of IPA and alkaline solution is 1%-30%, see Fig. 1 D,

(5) clean (cleaning the wet processing that adopts dioxysulfate water+dilute hydrofluoric acid+ammoniacal liquor hydrogen peroxide+hydrochloric acid hydrogen peroxide) and P type epitaxial loayer 5 and be filled to microscler conclusion of the business for the P type of arranging and the structure of N-type in deep trench, see Fig. 1 E;

(6) use the method for chemico-mechanical polishing to carry out planarization, be parked on deielectric-coating 3, see Fig. 1 F;

(7) utilize wet etching to remove the deielectric-coating 3 of positive and negative, can form the structure of P type and N-type alternative arrangement, if deielectric-coating 3 is oxide-films, wet liquid medicine can be used BOE(buffer oxide film etching agent) or HF(hydrofluoric acid), if deielectric-coating 3 is nitride films, wet liquid medicine can be used hot phosphoric acid, sees Fig. 1 G;

(8) subsequent technique can adopt ripe vertical double-diffused MOS can prepare complete super-junction device, sees Fig. 2.The step of subsequent technique is specific as follows:

A. the mode of using Implantation partly forms P well region 6(at special pattern respectively and can adopt boron to inject), N+ well region 7(can adopt phosphorus or arsenic to inject), P+ source region 8(can adopt boron to inject);

B. use diffusion way to form grid oxygen 13, re-use Low Pressure Chemical Vapor Deposition depositing polysilicon 12, and carry out dry etching, partly form polygate electrodes at special pattern;

C. use Low Pressure Chemical Vapor Deposition, aumospheric pressure cvd method or plasma reinforced chemical vapour deposition method form inter-level dielectric film 9, the kind of inter-level dielectric film 9 is oxide-films, carry out subsequently dry etching, form polysilicon and the zone isolation of metal electrode and the contact hole of source region and metal electrode;

D. adopt the sputter physical vaporous deposition to form positive source metal electrode 11 at front side of silicon wafer;

E. adopt the evaporating physical vapor deposition method to form the back side at silicon chip back side and leak metal electrode 10.

The present invention utilize on monocrystalline silicon due to the face of crystal face different orientation on the anisotropic etching of wet method, utilize the method for wet etching to open vertical deep trench on the N-type epitaxial loayer, usually carry out anisotropic wet etching on the silicon substrate of high preferred orientation 110, can form vertical deep trench, the crystal face of deep trench side is 111, the benefit of doing like this is as follows: 1. wet etching is less to the silicon substrate damage, can guarantee that follow-up outer layer growth quality is better, reduce the defective at PN junction interface, reduce leakage current; 2. the production cost of wet etching is lower; 3. wet etching is controlled etch rate by high preferred orientation, can guarantee the uniformity of 90 vertical profiles of spending and the interior pattern of face of deep trench.

Claims (9)

1. a method of using wet etching to prepare super-junction device, is characterized in that, comprises the steps:
Step 1, the epitaxial loayer of growing up on silicon substrate;
Step 2 forms deielectric-coating simultaneously at the front and back of silicon chip;
Step 3, front define figure with photoresist, open deielectric-coating with the method for dry etching;
Step 4 is removed photoresist, utilizes deielectric-coating as mask layer, uses the wet method anisotropic etching to form vertical deep groove structure;
Step 5, the rear epitaxial loayer of filling the epitaxial loayer type opposite of growth and step 1 in deep trench of cleaning is with the P type of formation alternative arrangement and the structure of N-type;
Step 6 uses the method for chemico-mechanical polishing to carry out planarization, is parked on deielectric-coating;
Step 7 utilizes wet etching to remove the deielectric-coating of positive and negative, can form the structure of P type and N-type alternative arrangement;
Step 8, subsequent technique adopt ripe vertical double-diffused MOS can prepare complete super-junction device, and subsequent technique comprises the steps:
A. the mode of using Implantation partly forms P well region, N+ well region and P+ source region at special pattern respectively;
B. use diffusion way to form grid oxygen, re-use the Low Pressure Chemical Vapor Deposition depositing polysilicon, and carry out dry etching, partly form polygate electrodes at special pattern;
C. use Low Pressure Chemical Vapor Deposition, aumospheric pressure cvd method or plasma reinforced chemical vapour deposition method to form the inter-level dielectric film, the kind of inter-level dielectric film is oxide-film, carry out subsequently dry etching, form polysilicon and the zone isolation of metal electrode and the contact hole of source region and metal electrode;
D. adopt the sputter physical vaporous deposition to form positive source metal electrode at front side of silicon wafer;
E. adopt the evaporating physical vapor deposition method to form the back side at silicon chip back side and leak metal electrode.
2. use wet etching as claimed in claim 1 prepares the method for super-junction device, it is characterized in that, in step 1, the thickness of described epitaxial loayer is between the 5-80 micron.
3. use wet etching as claimed in claim 1 prepares the method for super-junction device, it is characterized in that, in step 2, described formation deielectric-coating adopts the method for diffusion to form heat oxide film as deielectric-coating, and its thickness is between 1000 dusts-5000 dust; Perhaps adopt low-pressure chemical vapor deposition process formation oxide-film or nitride film as deielectric-coating, the thickness of oxide-film is between 2000 dusts-10000 dust, and the thickness of nitride film is between 100 dusts-500 dust.
4. use wet etching as claimed in claim 1 prepares the method for super-junction device, it is characterized in that, it is the silicon substrate of high preferred orientation 110 at silicon substrate described in step 1, in step 3, define with photoresist figure, the design configuration opening of photolithography plate aligns with 111 crystal faces, and this 111 crystal face refers to high preferred orientation 111, and this 111 crystal face is the crystal face of deep trench side in step 4.
5. use wet etching as claimed in claim 1 prepares the method for super-junction device, it is characterized in that, in step 4, described removal photoresist adopts ashing or dioxysulfate aqueous mixtures to remove photoresist.
6. use wet etching as claimed in claim 1 prepares the method for super-junction device, it is characterized in that, in step 4, the deielectric-coating at the back side plays the effect of protecting back side monocrystalline silicon, the vertical deep groove structure of positive formation, the degree of depth of this deep trench is the 5-50 micron; Wet liquid medicine adopts the alkaline solution of potassium hydroxide, tetramethyl hydrogen-oxygen ammonium or ethylenediamine pyrocatechol, with the percentage by weight of deionized water be 1%-50%; Perhaps wet liquid medicine is used the admixing medical solutions of above-mentioned alkaline solution and isopropyl alcohol, and the percent by volume ratio of isopropyl alcohol and alkaline solution is 1%-30%.
7. use wet etching as claimed in claim 1 prepares the method for super-junction device, it is characterized in that, if the epitaxial loayer of growing up in step 1 is P type epitaxial loayer, the epitaxial loayer of growing up in step 5 so is the N-type epitaxial loayer; If the epitaxial loayer of growing up in step 1 is the N-type epitaxial loayer, the epitaxial loayer of growing up in step 5 so is P type epitaxial loayer.
8. use wet etching as claimed in claim 1 prepares the method for super-junction device, it is characterized in that, in step 5, the wet processing of dioxysulfate water+dilute hydrofluoric acid+ammoniacal liquor hydrogen peroxide+hydrochloric acid hydrogen peroxide is adopted in described cleaning.
9. use wet etching as claimed in claim 1 prepares the method for super-junction device, it is characterized in that, in step 7, if deielectric-coating is oxide-film, wet liquid medicine is used buffer oxide film etching agent or hydrofluoric acid; If deielectric-coating is nitride film, wet liquid medicine is used hot phosphoric acid.
CN 201010276031 2010-09-09 2010-09-09 Wet etching method for preparation of super-junction device CN102403216B (en)

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