CN107591388A - Metal layer insulating metal level capacitor and forming method thereof - Google Patents
Metal layer insulating metal level capacitor and forming method thereof Download PDFInfo
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- CN107591388A CN107591388A CN201710777336.2A CN201710777336A CN107591388A CN 107591388 A CN107591388 A CN 107591388A CN 201710777336 A CN201710777336 A CN 201710777336A CN 107591388 A CN107591388 A CN 107591388A
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- 239000002184 metal Substances 0.000 title claims abstract description 258
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 258
- 239000003990 capacitor Substances 0.000 title claims abstract description 149
- 238000000034 method Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 219
- 239000011229 interlayer Substances 0.000 claims abstract description 84
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000004744 fabric Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
The present invention proposes a kind of metal layer insulating metal level capacitor and forming method thereof, is suitable for the application of in electric capacity in the piece of integrated circuit, forms the first metal layer, interlayer metal layer, second metal layer from the bottom to top, is spaced between each metal level by insulating barrier；The first metal layer includes the first metal layer a-quadrant and the first metal layer B area, and interlayer metal layer includes interlayer metal layer a-quadrant and interlayer metal layer B area；The bottom crown the first metal layer a-quadrant of MIM-_A capacitors is connected with the top crown interlayer metal layer B area of MIM_B capacitors by the part line of second metal layer, the top crown interlayer metal layer a-quadrant of MIM-_A capacitors is connected with the bottom crown the first metal layer B area of MIM_B capacitors by another part line of second metal layer, reduce the line impedance of upper capacitor plate, therefore the second metal layer of large area is no longer needed to reduce the line impedance of top crown, so as to save the area occupied of second metal layer, the utilization ratio of chip area is improved.
Description
Technical field
The present invention relates to a kind of metal-insulator-metal capacitor and forming method thereof.
Background technology
MIM（Metal-insulator-metal）Capacitor is a kind of common piece inner capacitor in integrated circuit technology
Part.Need to consider metallic area shared by it and spurious impedance to circuit when integrating large area MIM capacitor in chip
The influence of energy.
The cross-section structure of existing MIM capacitor in common technology is as shown in figure 1, the MIM capacitor includes from the bottom to top
The first metal layer 1, interlayer metal layer 2, second metal layer 3, it is spaced by insulating barrier 4 between each metal level.Wherein, the first gold medal
Belong to layer 1 and the corresponding composition MIM capacitor of interlayer metal layer 2, MIM capacitor is as a plate capacitor device, the first metal layer 1
For its bottom crown, interlayer metal layer 2 is its top crown.In general, the first metal layer 1 and second metal layer 3 are thicker, material
Resistivity is also smaller, and interlayer metal layer 2 therebetween is relatively thin, and the resistivity of material is also larger, in order to reduce MIM capacitor
Top crown interlayer metal layer 2 line impedance, usually using through hole 5 by the second metal layer 3 of large area and interlayer metal layer 2
Parallel connection, existing artwork distributing mode as shown in Fig. 2 the second metal layer 3 of large area occupies a large amount of areas on chip, and then
Influence the utilization ratio of chip area.
The content of the invention
It is an object of the invention to provide a kind of metal-insulator-metal capacitor and forming method thereof, can drop
The line impedance of low upper capacitor plate, and can save metal level area occupied, improve the utilization ratio of chip area.
Based on considerations above, one aspect of the present invention proposes a kind of formation of metal-insulator-metal capacitor
Method, it is suitable for the application of in electric capacity in the piece of integrated circuit, forms the first metal layer, interlayer metal layer, the second metal from the bottom to top
Layer, it is spaced between each metal level by insulating barrier；The first metal layer includes the first metal layer a-quadrant and the first metal layer B areas
Domain, interlayer metal layer include interlayer metal layer a-quadrant and interlayer metal layer B area, the first metal layer a-quadrant and interlayer metal layer
A-quadrant correspondingly forms MIM_A capacitors, and the first metal layer B area and interlayer metal layer B area correspondingly form MIM_B capacitors；
The bottom crown the first metal layer a-quadrant of MIM_A capacitors and the top crown interlayer metal layer B area of MIM_B capacitors pass through the
A part of line of two metal levels is connected, under the top crown interlayer metal layer a-quadrant of MIM_A capacitors and MIM_B capacitors
Pole plate the first metal layer B area is connected by another part line of second metal layer, to reduce the impedance of interlayer metal layer.
Preferably, MIM_A capacitors and MIM_B capacitors arrange along a direction, connect MIM_A capacitors and MIM_
The line of the second metal layer of B capacitor extends along the direction.
Preferably, MIM_A capacitors and MIM_B capacitors are arranged along a direction and staggeredly coupled on other direction
Set, the line for connecting the second metal layer of MIM_A capacitors and MIM_B capacitors extends along the other direction.
Preferably, the area of second metal layer is less than interlayer metal layer, the area of the first metal layer.
Preferably, the thickness of interlayer metal layer is less than the first metal layer, the thickness of second metal layer.
Preferably, interlayer metal layer, the first metal layer are connected by multiple through holes with second metal layer respectively.
Another aspect of the present invention proposes a kind of metal-insulator-metal capacitor, is suitable for the application of in integrated circuit
Piece in electric capacity, from the bottom to top including the first metal layer, interlayer metal layer, second metal layer, by insulating barrier between each metal level
It is spaced；The first metal layer includes the first metal layer a-quadrant and the first metal layer B area, and interlayer metal layer includes interlayer gold
Category layer a-quadrant and interlayer metal layer B area, the first metal layer a-quadrant and interlayer metal layer a-quadrant correspondingly form MIM_A electric capacity
Device, the first metal layer B area and interlayer metal layer B area correspondingly form MIM_B capacitors；The bottom crown of MIM_A capacitors
A part of line phase that the top crown interlayer metal layer B area of one metal layer A region and MIM_B capacitors passes through second metal layer
Even, the top crown interlayer metal layer a-quadrant of MIM_A capacitors passes through with the bottom crown the first metal layer B area of MIM_B capacitors
Another part line of second metal layer is connected, to reduce the impedance of interlayer metal layer.
Preferably, MIM_A capacitors and MIM_B capacitors arrange along a direction, connect MIM_A capacitors and MIM_
The line of the second metal layer of B capacitor extends along the direction.
Preferably, MIM_A capacitors and MIM_B capacitors are arranged along a direction and staggeredly coupled on other direction
Set, the line for connecting the second metal layer of MIM_A capacitors and MIM_B capacitors extends along the other direction.
Preferably, the area of second metal layer is less than interlayer metal layer, the area of the first metal layer.
Preferably, the thickness of interlayer metal layer is less than the first metal layer, the thickness of second metal layer.
Preferably, interlayer metal layer, the first metal layer are connected by multiple through holes with second metal layer respectively.
Metal-insulator-metal capacitor of the present invention and forming method thereof, utilizes the first metal layer of large area
Not only as the bottom crown of MIM capacitor, and two ports of capacitor are assigned to, reduce the company of upper capacitor plate
Line impedence, therefore the second metal layer of large area is no longer needed to reduce the line impedance of top crown, so as to save the second gold medal
Belong to the area occupied of layer, improve the utilization ratio of chip area.
Brief description of the drawings
By Figure of description and then it is used for the specific reality for illustrating some principles of the present invention together with Figure of description
Mode is applied, further feature and advantage will be clear or more specifically illustrated possessed by the present invention.
Fig. 1 is the sectional view of existing MIM capacitor；
Fig. 2 is the top view of existing MIM capacitor；
Fig. 3 is the top view according to the MIM capacitor of one embodiment of the invention；
Fig. 4 is the circuit diagram according to the MIM capacitor of one embodiment of the invention；
Fig. 5 is the top view according to the MIM capacitor of another embodiment of the present invention；
Fig. 6 is the top view according to the MIM capacitor of further embodiment of this invention.
Embodiment
To solve above-mentioned the problems of the prior art, the present invention provide a kind of metal-insulator-metal capacitor and
Its forming method, using the first metal layer of large area not only as the bottom crown of MIM capacitor, and it is assigned to capacitor
Two ports, reduce the line impedance of upper capacitor plate, therefore no longer need the second metal layer of large area to reduce
The line impedance of top crown, so as to save the area occupied of second metal layer, improve the utilization ratio of chip area.
In the specific descriptions of following preferred embodiment, by with reference to the appended accompanying drawing for forming a present invention part.Institute
Attached accompanying drawing, which has been illustrated by way of example, can realize specific embodiment.The embodiment of example is not intended as
Limit is according to all embodiments of the invention.It is appreciated that without departing from the scope of the present invention, other can be utilized
Embodiment, structural or logicality modification can also be carried out.Therefore, following specific descriptions and nonrestrictive, and this
The scope of invention is defined by the claims appended hereto.
Fig. 3 shows one embodiment of the MIM capacitor of the present invention, and the MIM capacitor is suitable for the application of in integrated circuit
Electric capacity in piece, from the bottom to top including the first metal layer 101, interlayer metal layer 102, second metal layer 103, between each metal level by
Insulating barrier（It is not shown）It is spaced；Wherein, the first metal layer 101 includes the first metal layer a-quadrant 101A and the first metal layer B
Region 101B, interlayer metal layer 102 include interlayer metal layer a-quadrant 102A and interlayer metal layer B area 102B, the first metal layer
A-quadrant 101A and interlayer metal layer a-quadrant 102A correspondingly forms MIM_A capacitors, the first metal layer B area 101B and interlayer gold
Category layer B area 102B correspondingly forms MIM_B capacitors；Bottom crown the first metal layer the a-quadrant 101A and MIM_ of MIM_A capacitors
The top crown interlayer metal layer B area 102B of B capacitor is connected by a part of line 103B of second metal layer 103, MIM_A
The bottom crown the first metal layer B area 101B of the top crown interlayer metal layer a-quadrant 102A and MIM_B capacitors of capacitor passes through
Another part line 103A of second metal layer 103 is connected, and circuit diagram is as shown in figure 4, the first metal layer 101 using large area
Not only as capacitor MIM_A, MIM_B bottom crown, and it is assigned to capacitor MIM_A, MIM_B two ports（Upper,
Bottom crown）, the line impedance of top crown interlayer metal layer 102 is reduced, therefore no longer need the second metal layer 103 of large area
To reduce the line impedance of top crown, so as to save the area occupied of second metal layer 103, the utilization of chip area is improved
Efficiency.
In a preferred embodiment shown in Fig. 3, MIM_A capacitors and MIM_B capacitors are along a direction（In figure
Vertical direction）Arrangement, connect MIM_A capacitors and MIM_B capacitors second metal layer 103 line 103A, 103B along
The direction is vertical direction extension.
In another preferred embodiment shown in Fig. 5, MIM_A capacitors and MIM_B capacitors are along a direction（In figure
Vertical direction）Arrange and in other direction（Horizontal direction in figure）Upper staggeredly coupling is set（Single Inserting structure）, add
Edge coupled capacitor between MIM_A capacitors and MIM_B capacitors, connect the second of MIM_A capacitors and MIM_B capacitors
Line 103A, 103B of metal level 103 are horizontal direction extension along the other direction, save more vertical direction cloth
Space of lines.
It will be understood by those skilled in the art that MIM_A capacitors and MIM_B capacitors interlock in the horizontal direction, coupling is set
Multiple Inserting structures can also be used by putting, as shown in Figure 6.
Preferably, the area of second metal layer 103 is less than interlayer metal layer 102, the area of the first metal layer 101.
Preferably, the thickness of interlayer metal layer 102 is less than the first metal layer 101, the thickness of second metal layer 103.
Preferably, interlayer metal layer 102, the first metal layer 101 pass through multiple through holes 105 and second metal layer 103 respectively
It is connected.
Another aspect of the present invention proposes a kind of forming method of MIM capacitor, is suitable for the application of in the piece of integrated circuit
Electric capacity, forms a metal level 101, interlayer metal layer 102, second metal layer 103 from the bottom to top, by insulating barrier between each metal level
（It is not shown）It is spaced；Wherein, the first metal layer 101 includes the first metal layer a-quadrant 101A and the first metal layer B area
101B, interlayer metal layer 102 include interlayer metal layer a-quadrant 102A and interlayer metal layer B area 102B, the first metal layer A areas
Domain 101A and interlayer metal layer a-quadrant 102A correspondingly form MIM_A capacitors, the first metal layer B area 101B and interlayer metal
Layer B area 102B correspondingly forms MIM_B capacitors；Bottom crown the first metal layer the a-quadrant 101A and MIM_B of MIM_A capacitors
The top crown interlayer metal layer B area 102B of capacitor is connected by a part of line 103B of second metal layer 103, MIM_A
The bottom crown the first metal layer B area 101B of the top crown interlayer metal layer a-quadrant 102A and MIM_B capacitors of capacitor passes through
Another part line 103A of second metal layer 103 is connected, to reduce the impedance of interlayer metal layer 102.
In a preferred embodiment shown in Fig. 3, MIM_A capacitors and MIM_B capacitors are along a direction（In figure
Vertical direction）Arrangement, connect MIM_A capacitors and MIM_B capacitors second metal layer 103 line 103A, 103B along
The direction is vertical direction extension.
In another preferred embodiment shown in Fig. 5, MIM_A capacitors and MIM_B capacitors are along a direction（In figure
Vertical direction）Arrange and in other direction（Horizontal direction in figure）Upper staggeredly coupling is set（Single Inserting structure）, add
Edge coupled capacitor between MIM_A capacitors and MIM_B capacitors, connect the second of MIM_A capacitors and MIM_B capacitors
Line 103A, 103B of metal level 103 are horizontal direction extension along the other direction, save more vertical direction cloth
Space of lines.
It will be understood by those skilled in the art that MIM_A capacitors and MIM_B capacitors interlock in the horizontal direction, coupling is set
Multiple Inserting structures can also be used by putting, as shown in Figure 6.
Preferably, the area of second metal layer 103 is less than interlayer metal layer 102, the area of the first metal layer 101.
Preferably, the thickness of interlayer metal layer 102 is less than the first metal layer 101, the thickness of second metal layer 103.
Preferably, interlayer metal layer 102, the first metal layer 101 pass through multiple through holes 105 and second metal layer 103 respectively
It is connected.
Metal-insulator-metal capacitor of the present invention and forming method thereof, utilizes the first metal layer of large area
Not only as the bottom crown of MIM capacitor, and two ports of capacitor are assigned to, reduce the company of upper capacitor plate
Line impedence, therefore the second metal layer of large area is no longer needed to reduce the line impedance of top crown, so as to save the second gold medal
Belong to the area occupied of layer, improve the utilization ratio of chip area.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
How from the point of view of, embodiment all should be regarded as exemplary, and be nonrestrictive.In addition, it will be evident that the word of " comprising " one not
Exclude other elements and step, and wording "one" be not excluded for plural number.The multiple element stated in device claim also may be used
To be realized by an element.The first, the second grade word is used for representing title, and is not offered as any specific order.
Claims (12)
1. a kind of forming method of metal-insulator-metal capacitor, it is suitable for the application of in electric capacity in the piece of integrated circuit,
Characterized in that,
The first metal layer, interlayer metal layer, second metal layer are formed from the bottom to top, between each metal level by insulating barrier to each other
Every；
The first metal layer includes the first metal layer a-quadrant and the first metal layer B area, and interlayer metal layer includes interlayer metal layer A
Region and interlayer metal layer B area, the first metal layer a-quadrant and interlayer metal layer a-quadrant correspondingly form MIM_A capacitors, the
One metal level B area and interlayer metal layer B area correspondingly form MIM_B capacitors；
The bottom crown the first metal layer a-quadrant of MIM_A capacitors and the top crown interlayer metal layer B area of MIM_B capacitors are led to
A part of line for crossing second metal layer is connected, top crown interlayer metal layer a-quadrant and the MIM_B capacitors of MIM_A capacitors
Bottom crown the first metal layer B area be connected by another part line of second metal layer, to reduce the resistance of interlayer metal layer
It is anti-.
2. the forming method of metal-insulator-metal capacitor according to claim 1, it is characterised in that MIM_
A capacitors and MIM_B capacitors arrange along a direction, connect the second metal layer of MIM_A capacitors and MIM_B capacitors
Line extend along the direction.
3. the forming method of metal-insulator-metal capacitor according to claim 1, it is characterised in that MIM_
A capacitors and MIM_B capacitors are arranged along a direction and staggeredly coupling is set on other direction, connect MIM_A electric capacity
The line of the second metal layer of device and MIM_B capacitors extends along the other direction.
4. the forming method of metal-insulator-metal capacitor according to claim 1, it is characterised in that second
The area of metal level is less than interlayer metal layer, the area of the first metal layer.
5. the forming method of metal-insulator-metal capacitor according to claim 1, it is characterised in that interlayer
The thickness of metal level is less than the first metal layer, the thickness of second metal layer.
6. the forming method of metal-insulator-metal capacitor according to claim 1, it is characterised in that interlayer
Metal level, the first metal layer are connected by multiple through holes with second metal layer respectively.
7. a kind of metal-insulator-metal capacitor, it is suitable for the application of in electric capacity in the piece of integrated circuit, it is characterised in that
Include the first metal layer, interlayer metal layer, second metal layer from the bottom to top, between each metal level by insulating barrier to each other
Every；
The first metal layer includes the first metal layer a-quadrant and the first metal layer B area, and interlayer metal layer includes interlayer metal layer A
Region and interlayer metal layer B area, the first metal layer a-quadrant and interlayer metal layer a-quadrant correspondingly form MIM_A capacitors, the
One metal level B area and interlayer metal layer B area correspondingly form MIM_B capacitors；
The bottom crown the first metal layer a-quadrant of MIM_A capacitors and the top crown interlayer metal layer B area of MIM_B capacitors are led to
A part of line for crossing second metal layer is connected, top crown interlayer metal layer a-quadrant and the MIM_B capacitors of MIM_A capacitors
Bottom crown the first metal layer B area be connected by another part line of second metal layer, to reduce the resistance of interlayer metal layer
It is anti-.
8. metal-insulator-metal capacitor according to claim 7, it is characterised in that MIM_A capacitors and
MIM_B capacitors arrange along a direction, connect the line edge of the second metal layer of MIM_A capacitors and MIM_B capacitors
The direction extension.
9. metal-insulator-metal capacitor according to claim 7, it is characterised in that MIM_A capacitors and
MIM_B capacitors are arranged along a direction and staggeredly coupling is set on other direction, connect MIM_A capacitors and MIM_B
The line of the second metal layer of capacitor extends along the other direction.
10. metal-insulator-metal capacitor according to claim 7, it is characterised in that second metal layer
Area is less than interlayer metal layer, the area of the first metal layer.
11. metal-insulator-metal capacitor according to claim 7, it is characterised in that interlayer metal layer
Thickness is less than the first metal layer, the thickness of second metal layer.
12. metal-insulator-metal capacitor according to claim 7, it is characterised in that interlayer metal layer,
One metal level is connected by multiple through holes with second metal layer respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710777336.2A CN107591388A (en) | 2017-09-01 | 2017-09-01 | Metal layer insulating metal level capacitor and forming method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710777336.2A CN107591388A (en) | 2017-09-01 | 2017-09-01 | Metal layer insulating metal level capacitor and forming method thereof |
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| Publication Number | Publication Date |
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| CN107591388A true CN107591388A (en) | 2018-01-16 |
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| CN201710777336.2A Pending CN107591388A (en) | 2017-09-01 | 2017-09-01 | Metal layer insulating metal level capacitor and forming method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1489213A (en) * | 2002-07-19 | 2004-04-14 | ���ǵ�����ʽ���� | Integrated circuit capacitor |
| US20050285226A1 (en) * | 2004-06-25 | 2005-12-29 | Magnachip Semiconductor, Ltd. | Parallel capacitor of semiconductor device |
| CN1771603A (en) * | 2003-04-09 | 2006-05-10 | 杰斯半导体公司纽波特工厂 | High density composite mim capacitor with reduced voltage dependence in semiconductor dies |
| CN102683319A (en) * | 2012-05-28 | 2012-09-19 | 上海华力微电子有限公司 | Layout structure of metal-insulator-metal (MIM) capacitor with inter-metallic air isolation structure |
| CN207303086U (en) * | 2017-09-01 | 2018-05-01 | 格科微电子（上海）有限公司 | Metal-insulator-metal capacitor |
-
2017
- 2017-09-01 CN CN201710777336.2A patent/CN107591388A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1489213A (en) * | 2002-07-19 | 2004-04-14 | ���ǵ�����ʽ���� | Integrated circuit capacitor |
| CN1771603A (en) * | 2003-04-09 | 2006-05-10 | 杰斯半导体公司纽波特工厂 | High density composite mim capacitor with reduced voltage dependence in semiconductor dies |
| US20050285226A1 (en) * | 2004-06-25 | 2005-12-29 | Magnachip Semiconductor, Ltd. | Parallel capacitor of semiconductor device |
| CN102683319A (en) * | 2012-05-28 | 2012-09-19 | 上海华力微电子有限公司 | Layout structure of metal-insulator-metal (MIM) capacitor with inter-metallic air isolation structure |
| CN207303086U (en) * | 2017-09-01 | 2018-05-01 | 格科微电子（上海）有限公司 | Metal-insulator-metal capacitor |
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