CN100446254C - Semiconductor capacity - Google Patents
Semiconductor capacity Download PDFInfo
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- CN100446254C CN100446254C CNB2005101115501A CN200510111550A CN100446254C CN 100446254 C CN100446254 C CN 100446254C CN B2005101115501 A CNB2005101115501 A CN B2005101115501A CN 200510111550 A CN200510111550 A CN 200510111550A CN 100446254 C CN100446254 C CN 100446254C
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- electric capacity
- trap
- polysilicon
- pip
- diffusion region
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Abstract
The invention is concerned with the semiconductor capacitance, includes a PIP capacitance and a N pitfall capacitance that parallel connect by the cascade mode. The invention can improve the unit capacitance density and the capability of semiconductor parts.
Description
Technical field
The present invention relates to a kind of semiconductor device, especially a kind of semicoductor capacitor.
Background technology
In present CMOS/BiCMOS technology, PiP (Poly-Insulator-Poly) electric capacity and N trap capacitance structure all extensively are used as capacitor element and use.
Fig. 1 is a PIP capacitance structure schematic diagram in the prior art.As shown in Figure 1, this electric capacity comprises as the underlying polysilicon 31 of electric capacity bottom crown with as the upper strata polysilicon 32 of electric capacity top crown, be filled with the insulator medium in the middle of this two-layer polysilicon, underlying polysilicon 31 is connected with metal level 34 respectively by the contact hole 33 that is filled with metal material with upper strata polysilicon 32.Fig. 4 is a kind of domain of making PIP electric capacity.As shown in Figure 4, in general CMOS/BiCMOS technology, make in the domain of above-mentioned PIP electric capacity, 1 is underlying polysilicon, and 2 is the upper strata polysilicon, and 3 is contact hole, and 4 is metal level.
Fig. 2 is a N trap capacitance structure schematic diagram in the prior art.As shown in Figure 2, this electric capacity comprises the N trap 42 as the electric capacity bottom crown that is arranged on the P type substrate 41, N trap 42 is provided with N type diffusion region " N+ " 43, this N type diffusion region arranged outside has an isolation 44, and N type diffusion region is connected with metal level 47 by connecing hole empty 46, N trap 42 is provided with the polysilicon 45 as this electric capacity top crown, and is filled with the insulator medium between N trap 42 and polysilicon 45, and polysilicon 45 is connected with metal level 47 by contact hole 48.Fig. 5 is a kind of domain of making Nwell Gate electric capacity.As shown in Figure 5, in general CMOS/BiCMOS technology, make in the domain of above-mentioned Nwell Gate electric capacity, 1 is underlying polysilicon, and 3 is contact hole, and 4 is metal level, and 5 is N type diffusion region " N+ ", and 6 is the N trap.
But in the prior art kind, general PiP electric capacity can be independently formed in the place, and N trap electric capacity is generally also formed separately.When using as big electric capacity, because the restriction of unit-area capacitance, identical electric capacity often will take big circuit area, has improved production cost.
Summary of the invention
Technical problem to be solved by this invention provides a kind of semicoductor capacitor, can be applicable to the semiconductor structure of more complicated, and can increase the electric capacity of unit are.
For solving the problems of the technologies described above, the technical scheme of a kind of semicoductor capacitor of the present invention is, comprise with laminated a PIP electric capacity and a N trap electric capacity parallel with one another, and the P type substrate of N trap electric capacity is provided with the N trap, the N trap is provided with N type diffusion region, there is an isolation in this outside, N type diffusion region, and N type diffusion region is connected with metal level by the contact hole that is filled with metal material, above the N trap, be disposed with the insulator medium according to from bottom to top order, underlying polysilicon with the overlapping PIP electric capacity of the polysilicon layer of N trap electric capacity, the insulator medium, PIP electric capacity upper strata polysilicon, described underlying polysilicon is connected with metal level by the contact hole that is filled with metal material with the upper strata polysilicon.
A kind of semicoductor capacitor of the present invention has improved the specific capacitance density of electric capacity and the performance of semiconductor device greatly by a stacked parallel connection PIP electric capacity and a N trap electric capacity.
Description of drawings
Below in conjunction with drawings and Examples the present invention is further described:
Fig. 1 is a PIP capacitance structure schematic diagram in the prior art;
Fig. 2 is a N trap capacitance structure schematic diagram in the prior art;
Fig. 3 is an electric capacity schematic diagram of the present invention;
Fig. 4 is a kind of domain of making PIP electric capacity;
Fig. 5 is a kind of domain of making N trap electric capacity;
Fig. 6 is a kind of domain of making electric capacity of the present invention.
Embodiment
Semicoductor capacitor of the present invention comprises with laminated a PIP electric capacity and a N trap electric capacity parallel with one another.As shown in Figure 3, semicoductor capacitor of the present invention comprises P type substrate 20, the P type substrate 20 that this P type substrate 20 is former N trap electric capacity, P type substrate 20 is provided with N trap 21, N trap 21 is provided with N type diffusion region " N+ " 22, there is an isolation 23 in these 22 outsides, N type diffusion region " N+ ", and N type diffusion region " N+ " 22 is connected with metal level 28 by the contact hole 27 that is filled with metal material, above N trap 21, be disposed with insulator medium 19 according to from bottom to top order, underlying polysilicon 24, this underlying polysilicon 24 is the overlapping of the polysilicon layer of in parallel N trap electric capacity and PIP electric capacity, insulator medium 18, upper strata polysilicon 25, contact hole 262 and metal level mutually 29 connections of described underlying polysilicon 24 by being filled with metal material, contact hole 261 and metal level mutually 28 connections of upper strata polysilicon 25 by being filled with metal material.
The manufacture method of semicoductor capacitor provided by the present invention is also very simple, only needs to change domain, and need not to change any technological process can produce.Fig. 6 is a kind of domain of making electric capacity of the present invention.As shown in Figure 6, in the domain of PIP electric capacity and N trap capacitor laminating shunt capacitance, 1 is underlying polysilicon, and 2 is the upper strata polysilicon, and 3 is contact hole, and 4 is metal level, and 5 is N type diffusion region " N+ ", and 6 is the N trap.
A kind of semicoductor capacitor of the present invention adopts stacked mode PIP electric capacity in parallel and N trap electric capacity, can improve the specific capacitance density of electric capacity and the performance of semiconductor device greatly, and its making only need change domain and needn't change any technological process.
Claims (1)
1. semicoductor capacitor, it is characterized in that, comprise with laminated a PIP electric capacity and a N trap electric capacity parallel with one another, and the P type substrate of N trap electric capacity is provided with the N trap, the N trap is provided with N type diffusion region, there is an isolation in this outside, N type diffusion region, and N type diffusion region is connected with metal level by the contact hole that is filled with metal material, above the N trap, be disposed with the insulator medium according to from bottom to top order, underlying polysilicon with the overlapping PIP electric capacity of the polysilicon layer of N trap electric capacity, the insulator medium, PIP electric capacity upper strata polysilicon, described underlying polysilicon is connected with metal level by the contact hole that is filled with metal material with the upper strata polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101115501A CN100446254C (en) | 2005-12-15 | 2005-12-15 | Semiconductor capacity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101115501A CN100446254C (en) | 2005-12-15 | 2005-12-15 | Semiconductor capacity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1983598A CN1983598A (en) | 2007-06-20 |
| CN100446254C true CN100446254C (en) | 2008-12-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005101115501A Active CN100446254C (en) | 2005-12-15 | 2005-12-15 | Semiconductor capacity |
Country Status (1)
| Country | Link |
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| CN (1) | CN100446254C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102420258A (en) * | 2011-07-12 | 2012-04-18 | 上海华力微电子有限公司 | Structure of metal-insulator-metal MOS (Metal Oxide Semiconductor) capacitor and manufacturing method of structure |
| CN106997878A (en) * | 2017-03-31 | 2017-08-01 | 无锡中微晶园电子有限公司 | The silicon capacitor and its manufacture method of double-decker |
| CN108335988A (en) * | 2018-02-12 | 2018-07-27 | 无锡中微晶园电子有限公司 | A kind of production method of silicon capacitance |
| CN112018070B (en) * | 2020-07-31 | 2022-04-08 | 复旦大学 | Three-dimensional integrated structure of nano capacitor and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05304250A (en) * | 1992-04-08 | 1993-11-16 | Nec Corp | Fabrication of semiconductor device |
| US5457065A (en) * | 1994-12-14 | 1995-10-10 | United Microelectronics Corporation | method of manufacturing a new DRAM capacitor structure having increased capacitance |
| CN1272687A (en) * | 1999-03-26 | 2000-11-08 | 因芬尼昂技术北美公司 | Laminated capacitor storage unit and its manufacturing method |
| CN1318869A (en) * | 2000-04-17 | 2001-10-24 | 国际商业机器公司 | Method for making polysilicon-polysilicon/MOS stacked capacitor |
| US20050093094A1 (en) * | 2003-08-05 | 2005-05-05 | Impinj, Inc. | High-voltage CMOS-compatible capacitors |
-
2005
- 2005-12-15 CN CNB2005101115501A patent/CN100446254C/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05304250A (en) * | 1992-04-08 | 1993-11-16 | Nec Corp | Fabrication of semiconductor device |
| US5457065A (en) * | 1994-12-14 | 1995-10-10 | United Microelectronics Corporation | method of manufacturing a new DRAM capacitor structure having increased capacitance |
| CN1272687A (en) * | 1999-03-26 | 2000-11-08 | 因芬尼昂技术北美公司 | Laminated capacitor storage unit and its manufacturing method |
| CN1318869A (en) * | 2000-04-17 | 2001-10-24 | 国际商业机器公司 | Method for making polysilicon-polysilicon/MOS stacked capacitor |
| US20050093094A1 (en) * | 2003-08-05 | 2005-05-05 | Impinj, Inc. | High-voltage CMOS-compatible capacitors |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1983598A (en) | 2007-06-20 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER NAME: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI |
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| CP03 | Change of name, title or address |
Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |