CN201247692Y - Capacitor of chip - Google Patents
Capacitor of chip Download PDFInfo
- Publication number
- CN201247692Y CN201247692Y CNU2008201505484U CN200820150548U CN201247692Y CN 201247692 Y CN201247692 Y CN 201247692Y CN U2008201505484 U CNU2008201505484 U CN U2008201505484U CN 200820150548 U CN200820150548 U CN 200820150548U CN 201247692 Y CN201247692 Y CN 201247692Y
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- CN
- China
- Prior art keywords
- capacitor
- daughter board
- bulge
- chip
- plates
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
The utility model relates to a capacitor which is arranged in a chip. The capacitor comprises at least two capacitor plates which are oppositely arranged, the opposite side surfaces of the capacitor plates are provided with a plurality of secondary plates which are arrayed in parallel, the secondary plates which are arranged on the two inner side surfaces of the opposite capacitor plates are alternately arrayed, and the side surfaces of the secondary plates are provided with convex structures. The utility model has the advantages that the convex structures are added on the side surfaces of the secondary plates of the capacitor plates, and consequently, the contact area among the capacitor plates is increased. On the premise that the additional chip area is not occupied, the capacitance value of the capacitor is increased.
Description
[technical field]
The utility model relates to integrated circuit fields, relates in particular to the capacitor in a kind of chip.
[background technology]
In integrated circuit manufacturing field, arrange that electric capacity is to be stranded to scratch one of difficult problem of engineer always.Arrange that electric capacity needs certain area as guarantee, the value of electric capacity is big more, and the area that takies is big more.And but save area is most important principle in the integrated circuit (IC) design.
For this reason, the electric capacity in the prior art chips generally adopts in the metal wiring layer of chip and forms capacitor plate, utilizes dielectric layer between capacitor plate as the medium of electric capacity.In order to obtain bigger capacitance on unit are, capacitor plate can be designed to insert finger.
Shown in the accompanying drawing 1, be the schematic top plan view of capacitor in the prior art chips, electric capacity includes to be and inserts two metal capacitance pole plates 111 and 112 that finger-like crosses one another and arranges in the described chip, is filled with dielectric material between the capacitor plate 111 and 112.Existence owing to dielectric material between two capacitor plates has capacitance characteristic.Described capacitor plate 111 has daughter board 111a, 111b and 111c, and capacitor plate 112 has daughter board 112a, 112b and 112c, interlaced arrangement between the daughter board.Owing to become to insert the mutual intersection of finger-like between the daughter board, increased the effective contact area between the pole plate, therefore can under the situation that does not increase additional areas, increase capacitance.
Shown in the accompanying drawing 2, be the profile of accompanying drawing 1 along AA ' direction.Under capacitor plate 111 and 112, arrange successively have other capacitor plates 121 and 122 identical with its shape, 131 and 132 and 141 and 142 etc., described capacitor plate also all has the daughter board of interlaced layout.Between capacitor plate, be filled with dielectric material, need between the upper and lower pole plate to carry out the position that electricity connects, can be connected by through hole.
Shown in the accompanying drawing 3, be the schematic top plan view of the relative position of capacitor plate 121 in the accompanying drawing 2 and 122.The position of AA ' direction is identical with the position in the accompanying drawing 1.1 to accompanying drawing 3 in conjunction with the accompanying drawings, shape between the capacitor plate of different layers is identical as can be seen, and staggered the each other distance of a daughter board of the relative position of vertically arranging, technique scheme can further increase the capacitance between the pole plate, obtains better technique effect.
Prior art adopts the daughter board of interlaced arrangement can increase capacitance, but only by single interlaced arrangement daughter board, increase rate to capacitance is limited, therefore need make improvement to the capacitor in the existing chip, under the prerequisite of not extra chip occupying area, further improve capacitance.
[summary of the invention]
Technical problem to be solved in the utility model is, the capacitor in a kind of chip is provided, and under the prerequisite that does not increase electric capacity shared area in chip, improves the condenser capacitance value.
In order to address the above problem, the utility model provides the capacitor in a kind of chip, described capacitor comprises at least two capacitor plates that are oppositely arranged, all be provided with some daughter boards that are arranged in parallel on the relative side of described capacitor plate, the interlaced arrangement of daughter board on relative two medial surfaces of the capacitor plate that is oppositely arranged, the side of described daughter board has bulge-structure.
As optional technical scheme, described daughter board is vertical with capacitor plate.
As optional technical scheme, described bulge-structure is a rectangle.
As optional technical scheme, described bulge-structure is a triangle.
As optional technical scheme, described bulge-structure is trapezoidal.
As optional technical scheme, the described side that is arranged at the daughter board of the interlaced arrangement on the different capacitor plates all is furnished with bulge-structure, and the position of the bulge-structure of two adjacent daughter board sides is interlaced.
As optional technical scheme, the minimum range between the bulge-structure edge on described setting and the daughter board is not less than the minimal design width of the design rule defined of this chip.
As optional technical scheme, be filled with dielectric layer between described capacitor plate and the daughter board.
Advantage of the present utility model is, increases bulge-structure by the side at the daughter board of capacitor plate, thereby increased the contact area between the capacitor plate, under the prerequisite that does not take additional chip area, improved the capacitance of capacitor.
[description of drawings]
Accompanying drawing 1 is depicted as the schematic top plan view of capacitor in the prior art chips;
Accompanying drawing 2 is depicted as the profile of accompanying drawing 1 along AA ' direction;
Accompanying drawing 3 is depicted as the schematic top plan view of the relative position of capacitor plate 121 in the accompanying drawing 2 and 122;
Accompanying drawing 4 is depicted as the schematic diagram of first kind of embodiment of the capacitor in the chip that the utility model provides;
Accompanying drawing 5 is depicted as the schematic diagram of second kind of embodiment of the capacitor in the chip that the utility model provides;
Accompanying drawing 6 is depicted as the schematic diagram of the third embodiment of the capacitor in the chip that the utility model provides.
[embodiment]
The embodiment of the capacitor in the chip that the utility model is provided below in conjunction with accompanying drawing elaborates.
Accompanying drawing 4 is depicted as the schematic diagram of first kind of embodiment of the capacitor in the chip that the utility model provides, and comprises the capacitor plate 210 and 220 with broach shape structure that is in same horizontal plane, and is filled in the dielectric material between the capacitor plate.Described capacitor plate 210 has daughter board 211 and 212, and capacitor plate 220 has daughter board 221 and 222.Interlaced arrangement between the daughter board.Described daughter board 211,212,221 and 222 side have the bulge-structure of rectangle, are positioned at the part in the dotted line outside shown in the respective figure 4, bulge- structure 211a, 211b, the 211c shown in the accompanying drawing 4 for example, and 222a, 222b and 222c.Adopt the capacitor of said structure,, therefore increased between the daughter board in order to form the effective area of electric capacity owing to increased bulge-structure in the side of daughter board.
Between described two capacitor plates 210 and 220 between the adjacent daughter board 211,212,221 and 222 relative side all be furnished with the bulge-structure of rectangle, and the position of the bulge-structure of two daughter boards is interlaced.The layout that bulge-structure is the interlaced distance between the daughter board that can further, and then avoided causing the phenomenon that the increase of coverage causes electric capacity to reduce between the daughter board owing to introducing raised structures.
Reduce distance between the bulge-structure edge and help increasing electric capacity between the capacitor plate, but the minimum range between the described bulge-structure edge that is arranged on the daughter board can not be less than the minimal design width L of the design rule defined of this chip
DFor example for the integrated circuit technology that the minimal design width is 0.13 μ m, L
D〉=0.13 μ m.
But above or below capacitor plate 210 and 220, can also arrange successively and have stagger mutually other capacitor plates of a sub-Board position of with its shape identical position, form the stacked structure of metal substrate, the relative position that capacitor plate and daughter board are arranged can be with reference to accompanying drawing in the prior art 1 to the stacked structure of the multi-layer capacity pole plate shown in the accompanying drawing 3 and the relative position between the pole plate.This technical scheme can further increase capacitance under the situation that does not increase the shared area of capacitor.
Accompanying drawing 5 is depicted as the schematic diagram of second kind of embodiment of the capacitor in the chip that the utility model provides, comprise the capacitor plate 310 and 320 that is in same horizontal plane with broach shape structure, and be filled in dielectric material between the capacitor plate, described capacitor plate 310 has daughter board 311 and 312, capacitor plate 320 has daughter board 321 and 322, described daughter board 311,312,321 and 322 side have leg-of-mutton bulge-structure, corresponding to the part that is positioned at the dotted line outside shown in the accompanying drawing 5.Bulge-structure is designed to triangle, also can plays the purpose that increases effective area between the pole plate.Other detail content of this embodiment can be with reference to the narration in first kind of embodiment.
Accompanying drawing 6 is depicted as the schematic diagram of the third embodiment of the capacitor in the chip that the utility model provides, and comprises the capacitor plate that is the broach shape 410 and 420 that is in same horizontal plane, and is filled in the dielectric material between the capacitor plate.Described capacitor plate 410 has daughter board 411 and 412, and capacitor plate 420 has daughter board 421 and 422, and described daughter board 411,412,421 and 422 side have trapezoidal bulge-structure, corresponding to the part that is positioned at the dotted line outside shown in the accompanying drawing 6.Bulge-structure is designed to trapezoidal, also can plays the purpose that increases effective area between the pole plate.Other detail content of this embodiment can be with reference to the narration in first kind of embodiment.
According to the needs of design, the bulge-structure that the side has of described daughter board also can be other arbitrary shapes, for example hexagon, circle, ellipse etc.But which kind of shape no matter, its purpose all is to increase the contact area between the capacitor plate, under the prerequisite that does not take additional chip area, improves the capacitance of capacitor, therefore all should be considered as not exceeding the scope that the utility model is protected.
The above only is a preferred implementation of the present utility model; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.
Claims (8)
1. the capacitor in the chip, described capacitor comprises at least two capacitor plates that are oppositely arranged, all be provided with some daughter boards that are arranged in parallel on the relative side of described capacitor plate, the interlaced arrangement of daughter board on relative two medial surfaces of the capacitor plate that is oppositely arranged, it is characterized in that the side of described daughter board has bulge-structure.
2. the capacitor in the chip according to claim 1 is characterized in that described daughter board is vertical with capacitor plate.
3. the capacitor in the chip according to claim 2 is characterized in that, described bulge-structure is a rectangle.
4. the capacitor in the chip according to claim 2 is characterized in that, described bulge-structure is a triangle.
5. the capacitor in the chip according to claim 2 is characterized in that, described bulge-structure is trapezoidal.
6. according to the capacitor in each described chip of claim 1 to 5, it is characterized in that, the described side that is arranged at the daughter board of the interlaced arrangement on the different capacitor plates all is furnished with bulge-structure, and the position of the bulge-structure of two adjacent daughter board sides is interlaced.
7. the capacitor in the chip according to claim 6 is characterized in that, the minimum range between the described bulge-structure edge that is arranged on the daughter board is not less than the minimal design width of the design rule defined of this chip.
8. the capacitor in the chip according to claim 1 is characterized in that, is filled with dielectric material between described capacitor plate and the daughter board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201505484U CN201247692Y (en) | 2008-07-04 | 2008-07-04 | Capacitor of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008201505484U CN201247692Y (en) | 2008-07-04 | 2008-07-04 | Capacitor of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201247692Y true CN201247692Y (en) | 2009-05-27 |
Family
ID=40731517
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2008201505484U Expired - Lifetime CN201247692Y (en) | 2008-07-04 | 2008-07-04 | Capacitor of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201247692Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701314A (en) * | 2015-03-24 | 2015-06-10 | 京东方科技集团股份有限公司 | Array substrate and display device |
-
2008
- 2008-07-04 CN CNU2008201505484U patent/CN201247692Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104701314A (en) * | 2015-03-24 | 2015-06-10 | 京东方科技集团股份有限公司 | Array substrate and display device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Free format text: FORMER OWNER: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION Effective date: 20121122 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201210 PUDONG NEW AREA, SHANGHAI TO: 100176 CHAOYANG, BEIJING |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20121122 Address after: 100176 Wenchang Avenue, Beijing Economic Development Zone, No. 18 Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201210 18 Zhangjiang Road, Shanghai, Pudong New Area Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| CX01 | Expiry of patent term |
Granted publication date: 20090527 |