KR101977760B1 - Multi chip semiconductor appratus - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor layout, and more particularly, to a layout of a power supply wiring in a multi-chip semiconductor device. A multi-chip semiconductor device comprising: a first region in which a first external power supply through electrode and a first ground power supply through electrode are alternately arranged while forming at least one row; And a second region in which a plurality of second external power supply penetrating electrode rows and a plurality of second ground power supply penetrating electrode rows are alternately arranged, and a distance between the penetrating electrodes in the penetrating electrode row of the second region Corresponds to a predetermined multiple of the distance between the penetrating electrodes arranged in the first region.

Description

[0001] MULTI CHIP SEMICONDUCTOR APPRATUS [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor layout, and more particularly, to a layout of a power supply wiring in a multi-chip semiconductor device.

BACKGROUND ART [0002] Packaging technology for semiconductor devices is continuously being developed for miniaturization and mounting reliability. For example, the demand for miniaturization is accelerating the development of technology for packages close to the chip size, and the demand for mounting reliability emphasizes the importance of packaging technology that can improve the efficiency of the mounting operation and the mechanical / electrical reliability after mounting I have to.

In addition, along with miniaturization of electrical and electronic products and high performance, various technologies for providing a high-capacity semiconductor module have been researched and developed. A method for providing a high-capacity semiconductor module may include high integration of a memory chip, and such high integration can be realized by integrating a larger number of cells in a limited space of the semiconductor chip.

However, the high integration of such a memory chip requires high technology and a lot of development time, such as requiring a precise line width. Thus, a stack technique has been proposed as another method for providing a high-capacity semiconductor module.

A stacked multi-chip semiconductor device is a package in which two or more semiconductor chips are stacked and mounted in one package. A structure using through silicon vias (TSV) has been introduced as an example of stacking semiconductor chips in a stacked structure and packaging them. A package using a TSV forms a hole penetrating the semiconductor chip in a semiconductor chip and forms a TSV by filling a conductive material in the hole. And the upper and lower semiconductor chips are electrically connected through the TSV.

1 is a view showing a multi-chip semiconductor device stacked using a conventional TSV.

The multi-chip semiconductor device shown in Fig. 1 includes first to fourth semiconductor chips CHIP1 to CHIP4. The multi-chip semiconductor device communicates with an external controller through an external connection pad (PAD) formed on the chip located at the bottom of the semiconductor chip, for example. The first to fourth semiconductor chips CHIP1 to CHIP4 are electrically connected through a penetrating electrode TSV so that the controller can control each semiconductor chip. The penetrating electrode TSV can transmit and receive various signals and data to and from each chip, and is also used as a means for supplying power required by the chip.

2 is a schematic view showing a power supply wiring structure of the first semiconductor chip CHIP1. In FIG. 2, the first semiconductor chip CHIP1 will be described as an example, and the second to fourth semiconductor chips CHIP2 to CHIP4 have the same structure as the first semiconductor chip CHIP1. The semiconductor chip described below corresponds to a memory chip that functions to store data in a memory cell.

The first semiconductor chip CHIP1 is supplied with power from the outside through the penetrating electrode. At this time, the penetrating electrode for supplying power is mainly arranged in a peripheral region located outside the memory cell area. 2 shows that the penetrating electrodes for supplying external power to the ferry area and the penetrating electrodes for supplying the ground power are alternately arranged in one row.

More specifically, the first semiconductor chip CHIP1 includes a plurality of first penetrating electrodes 10a, a plurality of second penetrating electrodes 10b, first and second power lines 15a and 15b, The first and second connection wirings 20a and 20b, the first connection wiring 25 and the second connection wiring 30, and the signal wiring 35. [

The plurality of first penetrating electrodes 10a may be arranged in a first direction of the drawing with a predetermined interval provided with an external power source VDD. The plurality of second penetrating electrodes 10b are provided with a ground power source (VSS) and arranged at regular intervals in the first direction. At this time, the first penetrating electrode 10a and the second penetrating electrode 10b may be alternately arranged in the first direction.

The first power wiring 15a and the second power wiring 15b extend in parallel along the first direction with the first penetrating electrode 10a therebetween. The first ground wiring 20a and the second ground wiring 20b also extend in parallel along the first direction with the second through electrode 10b therebetween. At this time, the first power wiring 15a and the first ground wiring 20a can be disposed in the upper row of the first and second penetrating electrodes 10a and 10b, and the second power wiring 15a and the second ground wiring 20b The wiring 20b may be disposed in the lower row of the first and second through electrodes 10b and 10b.

The first connection wiring 25 extends in a second direction substantially perpendicular to the first direction so as to connect the first and second power wiring 15a and 15b and the second connection wiring 30 extends in the second direction substantially perpendicular to the first direction, 1 and the second ground wirings 20a and 20b, as shown in FIG. Reference numeral CT denotes a contact portion.

The first and second connection wirings 25 and 30 are formed on the upper surfaces of the first and second power wirings 15a and 15b and the first and second ground wirings 20a and 20b, Can be placed.

The signal wiring 35 may be arranged parallel to the plane on which the first and second connection wirings 25 and 30 are formed.

However, as is known, since the area occupied by the through electrodes in the semiconductor chip is considerable, the number of the through electrodes is minimized and the through electrodes are efficiently arranged in order to increase the chip efficiency. In addition, when the power wiring or the like is disposed in the form of a mesh, the conductive layers included in the semiconductor chip need to be suitably arranged vertically.

Therefore, various measures for improving the area efficiency with respect to the layout of the power supply wiring of the semiconductor chip proposed by the prior art have been sought.

The present invention provides an efficient power supply wiring technique for each chip of a multi-chip semiconductor device.

A multi-chip semiconductor device according to an embodiment of the present invention includes a first region in which a first external power supply through electrode and a first ground power supply through electrode are alternately arranged while forming at least one row; And a second region in which a plurality of second external power supply penetrating electrode rows and a plurality of second ground power supply penetrating electrode rows are alternately arranged, and a distance between the penetrating electrodes in the penetrating electrode row of the second region Corresponds to a predetermined multiple of the distance between the penetrating electrodes arranged in the first region.

A multi-chip semiconductor device according to an embodiment of the present invention includes a plurality of semiconductor chips electrically connected and stacked through a plurality of through electrodes, each semiconductor chip including a plurality of memory cell regions and a plurality of Wherein a first external power supply through electrode and a first ground power supply through electrode are alternately arranged in at least one row in an edge ferry region of the ferry region, Wherein a plurality of second external power supply through electrode rows and a plurality of second ground power supply through electrode rows are alternately arranged in the center ferry region, Corresponds to a predetermined multiple of the distance between the electrodes.

According to this technique, the chip area efficiency of the multi-chip semiconductor device using the penetrating electrode can be increased.

1 is a view showing a multi-chip semiconductor device stacked using a conventional TSV,
2 is a view schematically showing the layout of the power supply wiring of the first semiconductor chip of Fig. 1, Fig.
3 is a view schematically showing a configuration of a semiconductor chip in a multi-chip semiconductor device according to an embodiment of the present invention,
FIG. 4 is a diagram showing a specific layout of a neighboring region of the memory cell region of FIG. 3;
Figure 5 is a diagram showing a specific layout for the center ferry area of Figure 3;
6 is a view schematically showing the configuration of the semiconductor chip shown in Figs. 3 to 5. Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, the embodiment of the present invention relates to a multi-chip semiconductor device including a plurality of semiconductor chips electrically connected and stacked through a penetrating electrode (TSV). The embodiment of the present invention specifically discloses the layout of the power supply wiring for each semiconductor chip included in the multi-chip semiconductor device.

3 is a view schematically showing a configuration of a semiconductor chip 1000 in a multi-chip semiconductor device according to an embodiment of the present invention.

In an embodiment of the present invention, a region where the penetrating electrode is formed in the semiconductor chip 1000 can be roughly divided into two parts. The penetrating electrode for supplying the power is located in a peripheral area of the semiconductor chip 1000. The ferrite area includes a first area adjacent to a memory cell area having a high power consumption, And a second region 200 that is a center ferry region located between the first regions 100A and 100B and the first regions 100A and 100B.

Since the first regions 100A and 100B are disposed adjacent to the memory cell region, the external power supply penetrating electrode VDD and the ground power supply penetrating electrode VSS, which are disposed in the first regions 100A and 100B, Are alternately arranged in a row direction with a first interval for tight supply of power voltage to the memory cell region. Although only the through electrodes are arranged alternately in one row in FIG. 3, it is needless to say that a plurality of rows may be arranged according to the amount of power required.

Since the second region 200 is spaced apart from the memory cell region in comparison with the first regions 100A and 100B, there is a relatively large margin in terms of power supply. Accordingly, the external power supply penetrating electrode VDD and the plurality of ground power supply penetrating electrodes VSS formed in the second region 200 are alternately arranged in a row unit. The penetrating electrodes VDD and VSS disposed in the respective rows of the second region 200 are arranged with a second gap larger than the first gap disposed in the first region 100. [ Specifically, considering the connection to the power line for the same power level, the second spacing may correspond to a predetermined multiple of the first spacing.

Meanwhile, the semiconductor chip 1000 may include a plurality of core regions. That is, when the semiconductor chip 1000 is a memory chip, the semiconductor chip 1000 may include a plurality of memory cell regions, which are located between the memory cell regions. Therefore, as shown in FIG. 3, since the two first regions 100A and 100B are arranged symmetrically about the second region 200, more accurate power supply to the corresponding memory cell region can be achieved do.

4 is a layout diagram showing the arrangement of the penetrating electrodes of the first regions 100A and 100B.

Specifically, the first external power supply penetrating electrode 110 and the first ground power supply penetrating electrode 120 are alternately arranged on the first regions 100A and 100B of the semiconductor chip 1000 at a first interval in the row direction .

 The first areas 100A and 100B include a pair of main external power supply lines 300 for providing external power provided from the first external power supply penetrating electrode 110 to a necessary area in the chip.

When the first external power supply penetrating electrode 110 and the first ground power supply penetrating electrode 120 are alternately arranged in the row direction, the main external power supply power line 300 is connected to the first external power supply through- And is electrically connected to the electrode 110 to extend in a thermal smell substantially perpendicular to the row direction. The reason that the main external power source power line 300 extends in a thermally induced manner is for connection to an external power source penetration electrode on the second region 200 to be described later. Accordingly, the main external power supply line 300 extends not only to the first regions 100A and 100B but also to the second region 200. [

Here, the first external power supply penetrating electrode 110 and the main external power supply power line 300 may be formed of the same conductive layer, for example, the highest conductive layer. For example, the main external power supply line 300 may extend along the left and right sides of the first external power supply penetrating electrode 110 and may be formed integrally with the first external power supply penetrating electrode 110 . Accordingly, the gap between the main external power supply line 300 and the penetrating electrode 110 can be reduced. In addition, since the main external power supply line 300 and the first external power supply through electrode 110 are formed of the same conductive layer, no separate contact is required.

The first areas 100A and 100B also include a pair of main ground power supply lines 400 for providing the ground power provided by the first ground power supply penetrating electrode 120 to the required area within the chip . As described above, when the first external power supply penetrating electrode 110 and the first ground power supply penetrating electrode 120 are alternately arranged in the row direction, the main ground power supply power line 400 is connected to the first And extends in the column direction while being connected to the ground power supply penetrating electrode 120 and the side portion. The reason that the main ground power supply line 400 extends in the column direction is for connection to the ground power supply through electrode located in the second region 200. Accordingly, the main ground power supply line 400 extends not only to the first regions 100A and 100B but also to the second region 200. [

The main ground power supply line 400 and the first ground power supply through electrode 120 may also be coplanar, for example, the topmost conductive layer. For example, the main ground power supply line 400 may be formed integrally with the first external power supply penetrating electrode 110 so as to extend along the left and right sides of the first ground power supply penetrating electrode 120.

Meanwhile, the main external power supply line 300 and the main ground power supply line 400 may be formed as a pair, and the first external power supply through electrode 110 and the first external power supply through- And the ground power supply penetrating electrode 120, respectively.

The first regions 100A and 100B may further include a sub power supply power line. The sub power source power line is a power line extending in the row direction and enhances the mesh effect of the main power source power line 300 extending in the column direction and thus has a power drop drop problem can be improved.

Specifically, the sub power supply power line includes a first sub external power supply line 130 and a first sub ground power supply line 140.

The first sub external power supply power line 130 may be arranged to connect the first external power supply through electrodes 110 arranged in the row direction.

Similarly, the first sub-ground power supply line 140 connects the first ground power supply through electrodes 120 arranged in the row direction as well. The first sub external power supply line 130 and the first sub ground power supply line 140 may be arranged in parallel to each other in the row direction so as to selectively connect the through electrodes arranged in the row direction.

The first sub external power supply line 130 and the first sub ground power supply line 140 are connected to the first external power supply through electrode 110 and the first ground power supply through electrode 120, And extend parallel to each other. For example, when the first sub external power supply power line 130 is disposed in the upper row of the penetrating electrodes 110 and 120, the first sub external power supply power line 130 may be connected to the first sub- Can be placed in the bottom row. The opposite is also possible.

On the other hand, the sub power source power line is formed in another layer separated from the conductive layer constituting the plurality of penetrating electrodes, the power line, and the ground line with an insulating film interposed therebetween. The sub power lines in this embodiment may be formed in the lower plane of the plane where the plurality of penetrating electrodes 110 and 120 are located.

5 is a diagram showing a specific layout of the second area 200. As shown in FIG.

More specifically, a plurality of second external power supply penetration electrodes 210A and 210B and a plurality of second ground power supply penetration electrodes 220A and 220B are formed in a plurality of rows in the second region 200 of the semiconductor chip 1000 Respectively. The distance between the penetrating electrodes disposed in each row of the second region 200 corresponds to a predetermined multiple of the distance between the penetrating electrodes disposed in the first regions 100A and 100B.

The second region 200 includes a main external power supply power line 300 and a main ground power supply power line 400 extending from the first region 100A and 100B. At this time, the main external power power line 300 and the main ground power power line 400 are alternately arranged in pairs as shown in FIG. Accordingly, the main external power supply line 300 is electrically connected to the second external power supply penetration electrode 210A located in a column in which the corresponding power line extends, and the main ground power supply line 400 is connected to the power supply line And is electrically connected to the second ground power supply penetrating electrode 220B located in the extended column.

At this time, since the second external power supply penetrating electrodes 210A and 210B and the second sub power supply penetrating electrodes 220A and 220B are formed in the uppermost conductive layer, 300 and the main sub power supply power line 400 and the through electrodes may be integrally connected without upper and lower connection contacts.

The second region 200 may further include a sub power supply power line. The sub power supply power line is a power line extending in the row direction and serves to enhance the mesh effect of the main power supply line extending in the column direction and thus can solve the power drop problem that may occur in the main power supply power line .

Specifically, the sub power supply power line includes a second sub external power supply line 230 and a second sub ground power supply line 240.

The second sub external power supply power line 230 connects the second external power supply through electrodes 210A and 210B that are continuously arranged in the row direction in the row direction.

The second sub-ground power supply line 240 connects the second external power supply through electrodes 220A and 220B that are continuously arranged in the row direction in the row direction.

At this time, the second sub external power supply power line 230 is disposed in the upper row and the lower row of the second external power supply penetrating electrodes 210A and 210B, respectively, and the second external power supply penetrating electrodes 210A and 210B, And may be electrically connected to the one side and the other side edge of the electrode terminal.

The second sub-ground power supply line 240 is also disposed in the upper row and the lower row of the second ground power supply through electrodes 220A and 220B so that the second ground power supply through electrodes 220A and 220B Side and the other-side edge.

Meanwhile, since the sub power source power line is formed in a separate layer from the uppermost conductive layer in which the plurality of through electrodes are formed, the upper and lower connection contacts must be connected to the through electrodes.

FIG. 6 is a view schematically showing the configuration of the semiconductor chip 1000 according to the embodiment of the present invention shown in FIG. 3 to FIG.

As described above, the penetration electrode for power supply is disposed mainly in the ferrite region of the semiconductor chip 1000. At this time, the ferry area is divided into a first area 100A and a second area 200, which are adjacent to a memory cell area (generally referred to as a core area), and a second area 200, which is a center ferry area.

In the first regions 100A and 100B, an external power supply through electrode and a ground power supply through electrode are alternately arranged in a row. On the other hand, in the second region 200, a plurality of external power supply through electrodes and a plurality of ground power supply through electrodes are arranged in a row, and are arranged alternately in rows.

The main power supply line extends in the column direction connecting the penetrating electrodes of the same potential across the first regions 100A and 100B and the second region 200. [ The main external power power line and the main ground power power line are alternately arranged in one column unit. At this time, the penetrating electrode and the main power supply power line may be formed in the same uppermost conductive layer M3.

The sub power source power line extends in the row direction connecting the penetrating electrodes of the same potential to the first areas 100A and 100B and the second area 200, respectively. In the first regions 100A and 100B, the sub external power supply line or the sub ground power supply power line is extended to the upper row or the lower row of the through electrodes. On the other hand, in the second region 200, the power line having the same potential is extended to the upper row and the higher row of the penetrating electrode depending on the potential of the penetrating electrode arranged for each row. At this time, since the sub power source power line is formed in the separate conductive layer M2 instead of the uppermost conductive layer, the sub power source power line is connected to the upper and lower connection contacts with the penetrating electrode.

According to the embodiment of the present invention, since the power supply layout can be realized by using only two conductive layers, it is possible to arrange signal lines for transmitting signals separately in the remaining conductive layers (M1, not shown).

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

1000: semiconductor chips 100A, 100B: first region
200: second region 110: first external power supply penetrating electrode
120: first ground power supply penetrating electrode
300: main external power power line 400: main ground power power line
130: first sub external power supply line
140: first sub-ground power supply line
210A and 210B: a second external power supply penetrating electrode
220A and 220B: the second sub power supply penetrating electrode
230: second sub external power supply line
240: Second sub-ground power supply line

Claims (20)

A first region where the first external power supply penetrating electrode and the first ground power supply penetrating electrode are alternately arranged while forming at least one row;
A second region in which a plurality of second external power supply through electrode rows and a plurality of second ground power supply through electrode rows are alternately arranged;
A plurality of main external power supply lines arranged to connect the first and second external power supply through electrodes arranged in the column direction in the column direction; And
And a plurality of main ground power supply power lines arranged to connect the first and second ground power supply through electrodes arranged in the column direction in the column direction,
Wherein the main external power supply line and the main ground power supply line are alternately arranged for every column,
Wherein the distance between the penetrating electrodes of the penetrating electrode rows of the second region corresponds to a predetermined multiple of the distance between the penetrating electrodes disposed in the first region. ◈ Claim 2 is abandoned due to payment of registration fee. The method according to claim 1,
Wherein the first and second regions are located in a peripheral region of the semiconductor device,
Wherein the first area corresponds to an edge ferry area,
And said second region corresponds to a center ferrier region. ◈ Claim 3 is abandoned due to the registration fee. The method according to claim 1,
Wherein the first and second regions correspond to a ferry region located between memory cell regions,
Wherein the first region corresponds to a region adjacent to the memory cell region,
And the second region is located between the first regions. delete ◈ Claim 5 is abandoned due to the registration fee. The method according to claim 1,
Each of said main external power supply power lines includes two power lines extending along both sides of said first and second external power supply penetrating electrodes. ◈ Claim 6 is abandoned due to the registration fee. 6. The method of claim 5,
Wherein the main external power supply power line is integrally formed on the same plane as the conductive layer that forms the plurality of penetrating electrodes. ◈ Claim 7 is abandoned due to registration fee. The method according to claim 1,
A first sub external power supply line connecting the first external power supply through electrodes arranged in a row direction perpendicular to the column direction; And
Further comprising: a first sub-ground power supply line connecting the first ground power supply through electrodes arranged in the row direction,
Wherein the first sub external power supply power line and the first sub ground power supply power line are connected to the first external power supply through electrode and the first ground power supply through electrode, A semiconductor device. ◈ Claim 8 is abandoned due to the registration fee. 8. The method of claim 7,
Wherein the first sub external power supply power line and the first sub ground power supply power line are formed in different planes with the plurality of penetrating electrodes and an insulating film interposed therebetween. ◈ Claim 9 is abandoned upon payment of registration fee. 8. The method of claim 7,
A second sub external power supply line connecting the second external power supply through electrodes arranged in the row direction; And
And a second sub-ground power supply line connecting the second ground power supply penetrating electrode arranged in the row direction. ◈ Claim 10 is abandoned due to the registration fee. 10. The method of claim 9,
Wherein the second sub external power supply power line includes two power lines extending along both sides of the second external power supply penetrating electrode and the second sub ground power supply line is located on both sides of the second ground power supply penetrating electrode And a power line extending along the power line. ◈ Claim 11 is abandoned due to registration fee. 11. The method of claim 10,
Wherein the second sub external power supply line and the second sub ground power supply line are formed in different planes with the plurality of through electrodes and the insulation film interposed therebetween and the first sub external power supply line and the first sub- Chip semiconductor device is formed on the same plane as the power line. delete delete delete delete delete delete delete delete delete

Images