CN116403995B - Low-loss on-chip capacitor - Google Patents
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- CN116403995B CN116403995B CN202310665303.4A CN202310665303A CN116403995B CN 116403995 B CN116403995 B CN 116403995B CN 202310665303 A CN202310665303 A CN 202310665303A CN 116403995 B CN116403995 B CN 116403995B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 49
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- 239000002184 metal Substances 0.000 claims abstract description 286
- 238000000034 method Methods 0.000 claims description 11
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- 230000000712 assembly Effects 0.000 claims description 7
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- 230000005540 biological transmission Effects 0.000 description 7
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- 239000004065 semiconductor Substances 0.000 description 6
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Abstract
The application discloses a low-loss on-chip capacitor, which comprises a first electrode assembly and a second electrode assembly; the first electrode assembly and the second electrode assembly comprise a plurality of metal layers, and the metal layers are connected through a plurality of connecting pieces; the number of the metal layers of the first electrode assembly is equal to that of the metal layers of the second electrode assembly, and each metal layer of the first electrode assembly and each metal layer of the second electrode assembly form an interdigital structure in the horizontal direction; the thicknesses of the topmost metal layer of the first electrode assembly and the topmost metal layer of the second electrode assembly are not smaller than a preset first thickness threshold, the thicknesses of other metal layers of the first electrode assembly and other metal layers of the second electrode assembly are not larger than a preset second thickness threshold, and the first thickness threshold is larger than the second thickness threshold. The low-loss on-chip capacitor has smaller loss, larger capacitance capacity and better interface compatibility.
Description
Technical Field
The present application relates to the field of semiconductor integrated circuits, and more particularly, to a low-loss on-chip capacitor.
Background
On-chip Capacitors (On-chip Capacitors) are very important considerations in terms of capacity and loss in high Frequency Radio Frequency (RF) circuits. With the increasing operating frequencies of millimeter Wave (mm-Wave) and Terahertz (Terahertz) systems and the decreasing semiconductor process, the layout area occupied by a single device is smaller and smaller, and on-chip capacitors are required to generate larger capacitance and higher quality factor under smaller layout area.
The Metal-Oxide-Metal (MOM) capacitor is a common on-chip capacitor in an integrated circuit, and mainly utilizes an interdigital structure of the same layer of Metal to construct the capacitor, and has the characteristics of high capacitor density, good linearity and the like. However, in order to increase the capacitance density, a conventional MOM capacitor generally adopts a relatively thin metal layer with a relatively close distance to form a capacitor, if a multi-layer structure is adopted, the structure of each layer is similar, and when the structure is used for constructing a capacitor with large capacity, the length of an interdigital is too long, so that the problem of relatively large loss exists; in addition, when devices such as inductors, transmission lines and interconnecting wires in millimeter wave and terahertz circuits are interconnected with the traditional MOM capacitor, the devices need to be connected with different metal layers through holes, so that parasitic parameters of the circuits are increased, and the performance of the circuits is affected.
Disclosure of Invention
In view of the above, the present application provides a low-loss on-chip capacitor to solve at least one of the above-mentioned technical problems.
In order to achieve the above object, the present application provides a low-loss on-chip capacitor including a first electrode assembly and a second electrode assembly;
the first electrode assembly includes a plurality of metal layers, each metal layer being connected by a plurality of first connecting members;
the second electrode assembly includes a plurality of metal layers, each metal layer being connected by a plurality of second connecting members;
the number of the metal layers of the first electrode assembly is equal to that of the metal layers of the second electrode assembly, and each metal layer of the first electrode assembly and each metal layer of the second electrode assembly form an interdigital structure in the horizontal direction;
the thicknesses of the topmost metal layer of the first electrode assembly and the topmost metal layer of the second electrode assembly are not smaller than a preset first thickness threshold, the thicknesses of other metal layers of the first electrode assembly and other metal layers of the second electrode assembly are not larger than a preset second thickness threshold, and the first thickness threshold is larger than the second thickness threshold.
Preferably, the other metal layers except the topmost metal layer in the first electrode assembly and the other metal layers except the topmost metal layer in the second electrode assembly also form an interdigitated structure in the vertical direction.
Preferably, each metal layer of the first electrode assembly is provided with a corresponding through hole, the first connecting piece is a metal connecting column, and each metal layer of the first electrode assembly is connected through a plurality of metal connecting columns penetrating through the through hole of each metal layer;
the metal layers of the second electrode assembly are provided with corresponding through holes, the second connecting piece is a metal connecting column, and the metal layers of the second electrode assembly are connected through a plurality of metal connecting columns penetrating through the through holes of each metal layer.
Preferably, the topmost metal layer of the first electrode assembly includes a first rectangular metal strip and a plurality of first gate fingers extending vertically outward from one side of the first rectangular metal strip;
the topmost metal layer of the second electrode assembly comprises a second rectangular metal strip and a plurality of second grid fingers extending outwards vertically at one side of the second rectangular metal strip;
the plurality of first gate fingers and the plurality of second gate fingers form an inter-finger structure in a horizontal direction.
Preferably, each metal layer of the first electrode assembly except the topmost metal layer comprises a plurality of first fishbone type metal assemblies tiled;
the first fishbone type metal component comprises a first metal trunk and a plurality of third grid fingers extending outwards vertically at two sides of the first metal trunk;
each first metal trunk of each layer is vertically aligned with one first gate finger;
each metal layer except the topmost metal layer in the second electrode assembly comprises a plurality of tiled second fishbone type metal assemblies;
the second fishbone type metal component comprises a second metal trunk and a plurality of fourth grid fingers which extend outwards vertically at two sides of the second metal trunk;
each second metal backbone of each layer is vertically aligned with one second gate finger.
Preferably, each metal layer of the first electrode assembly corresponds to each metal layer of the second electrode assembly one by one;
the first fishbone metal component and the second fishbone metal component which are adjacent left and right in each metal layer realize mutual interdigital in the horizontal direction through each third grid finger and each fourth grid finger on opposite sides.
Preferably, in the upper and lower adjacent metal layers, the first fishbone metal assembly and the second fishbone metal assembly realize inter-pointing in the vertical direction through each third gate finger and each fourth gate finger on the same side.
Preferably, the first gate finger and the first metal trunk are respectively provided with a corresponding first through hole, the first connecting piece is a metal connecting column, and each metal layer of the first electrode assembly is connected through a plurality of metal connecting columns penetrating through the first through holes of each metal layer;
the second gate finger and the second metal trunk are respectively provided with a corresponding second through hole, the second connecting piece is a metal connecting column, and each metal layer of the second electrode assembly is connected through a plurality of metal connecting columns penetrating through the second through holes of each metal layer.
Preferably, an oxide filling layer is arranged between adjacent metal layers in the first electrode assembly; an oxide filling layer is arranged between adjacent metal layers in the second electrode assembly.
Preferably, the specific values of the first thickness threshold and the second thickness threshold are dependent on the process employed by the low-loss on-chip capacitor.
As can be seen from the above technical solution, the low-loss on-chip capacitor of the present application includes a first electrode assembly and a second electrode assembly. Wherein the first electrode assembly comprises a plurality of metal layers, each metal layer being connected by a plurality of first connecting members; likewise, the second electrode assembly includes a plurality of metal layers, each of which is connected by a plurality of second connecting members. The number of the metal layers of the first electrode assembly is equal to that of the metal layers of the second electrode assembly, and each metal layer of the first electrode assembly and each metal layer of the second electrode assembly form an interdigital structure in the horizontal direction. The thicknesses of the topmost metal layer of the first electrode assembly and the topmost metal layer of the second electrode assembly are not smaller than a preset first thickness threshold, the thicknesses of other metal layers of the first electrode assembly and other metal layers of the second electrode assembly are not larger than a preset second thickness threshold, and the first thickness threshold is larger than the second thickness threshold. It is understood that the thicknesses of the topmost metal layers of the first electrode assembly and the second electrode assembly are relatively large, while the thicknesses of the other metal layers of the first electrode assembly and the second electrode assembly are relatively small. The advantage is that, on one hand, as the metal layers of the first electrode assembly are mutually communicated and the metal layers of the second electrode assembly are mutually communicated, the total resistance of the low-loss on-chip capacitor is equal to the parallel parasitic resistance of the metal layers, and as the thickness of the top-most metal layer is relatively larger and the parasitic resistance is smaller, the total resistance of the low-loss on-chip capacitor, namely the loss, is also smaller; on the other hand, the thicknesses of the other metal layers of the first electrode assembly and the second electrode assembly are relatively small, and small and dense metal interdigital can be formed, so that larger capacitance capacity is generated; on the other hand, since the thickness of the topmost metal layer is relatively large, and devices such as inductors, transmission lines and interconnection lines in millimeter wave and terahertz circuits usually adopt thick metal layers as signal lines, the devices on the RF semiconductor chip such as inductors and transmission lines can be directly connected into the capacitor through the topmost metal layer, so that the low-loss on-chip capacitor has better interconnection and interface compatibility.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present application, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic perspective view of a low-loss on-chip capacitor according to an embodiment of the present application;
FIG. 2 is a top view of a low loss on-chip capacitor according to an embodiment of the present application;
FIG. 3 is a cross-sectional view of a low-loss on-chip capacitor in section one according to an embodiment of the present application;
FIG. 4 is a cross-sectional view of a low-loss on-chip capacitor in section two according to an embodiment of the present application;
FIG. 5 is a top view of the topmost metal layer of a low-loss on-chip capacitor according to an embodiment of the present application;
FIG. 6 is a top view of a low-loss on-chip capacitor including metal layers according to an embodiment of the present application;
FIG. 7 illustrates a high capacitance density portion of a first electrode assembly disclosed in an embodiment of the present application;
FIG. 8 illustrates a first fishbone metal assembly in accordance with an embodiment of the application;
FIG. 9 illustrates a first fishbone metal element and a second fishbone metal element in accordance with embodiments of the application;
fig. 10 illustrates an interdigitated structure of a first fishbone metal element and a second fishbone metal element in accordance with an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The low-loss on-chip capacitor provided by the embodiment of the application is described below. Referring to fig. 1 to 3, the low-loss on-chip capacitor according to the embodiment of the present application may include a first electrode assembly 100 and a second electrode assembly 200.
The first electrode assembly 100 includes a plurality of metal layers, and the metal layers on the first electrode assembly 100 are connected by a plurality of first connecting members.
The second electrode assembly 200 includes a plurality of metal layers, and the metal layers on the second electrode assembly 200 are connected by a plurality of second connecting members.
The number of metal layers of the first electrode assembly 100 is equal to the number of metal layers of the second electrode assembly 200, and each metal layer of the first electrode assembly 100 and each metal layer of the second electrode assembly 200 form an interdigitated structure in the horizontal direction.
The thickness of the topmost metal layer 001 of the first electrode assembly 100 and the second electrode assembly 200 is not less than a preset first thickness threshold, and the thickness of each of the other metal layers 002 of the first electrode assembly 100 and the second electrode assembly 200 is not greater than a preset second thickness threshold, wherein the first thickness threshold is greater than the second thickness threshold.
The low-loss on-chip capacitor of the present application includes a first electrode assembly and a second electrode assembly. Wherein the first electrode assembly comprises a plurality of metal layers, each metal layer being connected by a plurality of first connecting members; likewise, the second electrode assembly includes a plurality of metal layers, each of which is connected by a plurality of second connecting members. The number of the metal layers of the first electrode assembly is equal to that of the metal layers of the second electrode assembly, and each metal layer of the first electrode assembly and each metal layer of the second electrode assembly form an interdigital structure in the horizontal direction. The thicknesses of the topmost metal layer of the first electrode assembly and the topmost metal layer of the second electrode assembly are not smaller than a preset first thickness threshold, the thicknesses of other metal layers of the first electrode assembly and other metal layers of the second electrode assembly are not larger than a preset second thickness threshold, and the first thickness threshold is larger than the second thickness threshold. It is understood that the thicknesses of the topmost metal layers of the first electrode assembly and the second electrode assembly are relatively large, while the thicknesses of the other metal layers of the first electrode assembly and the second electrode assembly are relatively small. The advantage is that, on one hand, as the metal layers of the first electrode assembly are mutually communicated and the metal layers of the second electrode assembly are mutually communicated, the total resistance of the low-loss on-chip capacitor is equal to the parallel parasitic resistance of the metal layers, and as the thickness of the top-most metal layer is relatively larger and the parasitic resistance is smaller, the total resistance of the low-loss on-chip capacitor, namely the loss, is also smaller; on the other hand, the thicknesses of the other metal layers of the first electrode assembly and the second electrode assembly are relatively small, and small and dense metal interdigital can be formed, so that larger capacitance capacity is generated; on the other hand, since the thickness of the topmost metal layer is relatively large, and devices such as inductors, transmission lines and interconnection lines in millimeter wave and terahertz circuits usually adopt thick metal layers as signal lines, the devices on the RF semiconductor chip such as inductors and transmission lines can be directly connected into the capacitor through the topmost metal layer, so that the low-loss on-chip capacitor has better interconnection and interface compatibility.
In some embodiments of the present application, an Oxide filling layer is disposed between adjacent Metal layers in the first electrode assembly 100, and similarly, an Oxide filling layer is disposed between adjacent Metal layers in the second electrode assembly 200, where each Metal layer and each Oxide layer together form a MOM (Metal-Oxide-Metal) capacitor.
In some embodiments of the present application, the specific values of the aforementioned first thickness threshold and second thickness threshold are dependent on the process employed by the low-loss on-chip capacitor.
Illustratively, under certain processes, the first thickness threshold may be 3.5 μm and the first thickness threshold may be 0.145 μm. In this thickness configuration, the thicknesses of the topmost metal layer of the first electrode assembly 100 and the topmost metal layer of the second electrode assembly 200 are not less than 3.5 μm, the thicknesses of the other metal layers of the first electrode assembly 100 and the other metal layers of the second electrode assembly 200 are not more than 0.145 μm, and specific thickness values may be according to actual needs, it being understood that the topmost metal layers of the first electrode assembly 100 and the second electrode assembly 200 form low-loss capacitance portions; other metal layers of the first electrode assembly 100 and the second electrode assembly 200 form a high capacitance density portion. This configuration enables the thickness of the top layer of the low-loss on-chip capacitor to be adapted to other connections of the RF semiconductor on-chip device, reducing overall resistive losses while improving interface compatibility and capacitance capacity.
In some embodiments of the present application, as shown in fig. 4, other metal layers except for the topmost metal layer in the first electrode assembly 100 and other metal layers except for the topmost metal layer in the second electrode assembly 200 also form an interdigitated structure in the vertical direction.
In some embodiments of the present application, each metal layer of the first electrode assembly 100 is provided with a corresponding through hole, and the first connection member is a metal connection post, and each metal layer of the first electrode assembly 100 is connected by a plurality of metal connection posts penetrating through the through hole of each metal layer.
Similarly, each metal layer of the second electrode assembly 200 is provided with a corresponding through hole, the second connecting member is a metal connecting post, and each metal layer of the second electrode assembly 200 is connected by a plurality of metal connecting posts penetrating through the through hole of each metal layer.
In some embodiments of the present application, referring to fig. 1, 2 and 5, the topmost metal layer of the first electrode assembly 100 includes a first rectangular metal strip 101 and a plurality of first gate fingers 102 extending vertically outward on one side of the first rectangular metal strip 101.
The topmost metal layer of the second electrode assembly 200 includes a second rectangular metal strip 201 and a plurality of second gate fingers 202 extending vertically outward from one side of the second rectangular metal strip 201.
Each first gate finger 102 and each second gate finger 202 form an interdigitated structure in the horizontal direction.
In some embodiments of the present application, referring to fig. 6 to 9, each of the metal layers except the topmost metal layer in the first electrode assembly 100 includes a plurality of first fishbone metal assemblies 120 tiled; each first gate finger 102 of the topmost metal layer of the first electrode assembly 100 corresponds to a first fishbone metal element 120 distributed over the underlying metal layers.
The first fishbone metal element 120 includes a first metal stem 121 and a plurality of third gate fingers 122 extending vertically outward from both sides of the first metal stem 121.
The first metal stem 121 of each layer is vertically aligned with one first gate finger 102 of the topmost metal layer of the first electrode assembly 100.
Similarly, each of the metal layers of the second electrode assembly 200, except for the topmost metal layer, includes a plurality of second fishbone metal assemblies 220 tiled, similar to the first electrode assembly 100; each of the second gate fingers 202 of the topmost metal layer of the second electrode assembly 200 corresponds to a second fishbone metal assembly 220 distributed over the underlying metal layers.
The second fishbone metal element 220 includes a second metal trunk 221 and a plurality of fourth gate fingers 222 extending vertically outward from both sides of the second metal trunk 221.
The second metal stem 221 of each layer is vertically aligned with one second gate finger 202 of the topmost metal layer of the second electrode assembly 200.
In some embodiments of the present application, the metal layers of the first electrode assembly 100 correspond one-to-one to the metal layers of the second electrode assembly 200, and as shown in fig. 9 and 10, the first and second fishbone metal assemblies 120 and 220 adjacent left and right in each metal layer achieve mutual interdigitation in the horizontal direction by the third and fourth gate fingers 122 and 222 on opposite sides.
In some embodiments of the present application, the first and second fishbone metal elements 120 and 220 are interdigitated in the vertical direction by the third and fourth gate fingers 122 and 222 on the same side in the upper and lower adjacent metal layers.
Specifically, referring to fig. 7, fig. 7 shows the first fishbone metal element 120 of the plurality of metal layers in the first electrode assembly 100, in which it is seen that the first metal stems 121 of the first fishbone metal element 120 of each layer are vertically aligned, and the third gate fingers 122 of each adjacent layer are offset from each other by one finger. The structure of the second electrode assembly 200 is similar to that of the first electrode assembly 100, and thus, when the first electrode assembly 100 and the second electrode assembly 200 are combined, a structure may be formed in which the two electrodes are interdigitated in both the horizontal direction and the vertical direction as shown in fig. 4.
In some embodiments of the present application, referring to fig. 7 and fig. 9, corresponding first through holes 123 are formed in the first gate finger 102 and the first metal stem 121, and the first connecting member is a metal connecting post, and the metal layers of the first electrode assembly 100 are connected by a plurality of metal connecting posts 300 penetrating through the first through holes 123 of each metal layer.
Similarly, the second gate finger 202 and the second metal trunk 221 are respectively provided with a corresponding second through hole 223, the aforementioned second connecting member is a metal connecting post, and the metal layers of the second electrode assembly 200 are connected by a plurality of metal connecting posts penetrating through the second through hole 223 of each metal layer.
To sum up:
the low-loss on-chip capacitor of the present application includes a first electrode assembly and a second electrode assembly. Wherein the first electrode assembly comprises a plurality of metal layers, each metal layer being connected by a plurality of first connecting members; likewise, the second electrode assembly includes a plurality of metal layers, each of which is connected by a plurality of second connecting members. The number of the metal layers of the first electrode assembly is equal to that of the metal layers of the second electrode assembly, and each metal layer of the first electrode assembly and each metal layer of the second electrode assembly form an interdigital structure in the horizontal direction. The thicknesses of the topmost metal layer of the first electrode assembly and the topmost metal layer of the second electrode assembly are not smaller than a preset first thickness threshold, the thicknesses of other metal layers of the first electrode assembly and other metal layers of the second electrode assembly are not larger than a preset second thickness threshold, and the first thickness threshold is larger than the second thickness threshold. It is understood that the thicknesses of the topmost metal layers of the first electrode assembly and the second electrode assembly are relatively large, while the thicknesses of the other metal layers of the first electrode assembly and the second electrode assembly are relatively small. The advantage is that, on one hand, as the metal layers of the first electrode assembly are mutually communicated and the metal layers of the second electrode assembly are mutually communicated, the total resistance of the on-chip capacitor is equal to the parallel parasitic resistance of the metal layers, and as the thickness of the top-most metal layer is relatively larger, the parasitic resistance is smaller, so that the total resistance of the on-chip capacitor, namely the loss, is also smaller; on the other hand, the thicknesses of the other metal layers of the first electrode assembly and the second electrode assembly are relatively small, and small and dense metal interdigital can be formed, so that larger capacitance capacity is generated; on the other hand, since the thickness of the topmost metal layer is relatively large, and devices such as inductors, transmission lines and interconnection lines in millimeter wave and terahertz circuits usually adopt thick metal layers as signal lines, the devices on the RF semiconductor chip such as inductors and transmission lines can be directly connected into the capacitor through the topmost metal layer, so that the on-chip capacitor has better interconnection and interface compatibility.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the present specification, each embodiment is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and may be combined according to needs, and the same similar parts may be referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (3)
1. A low-loss on-chip capacitor comprising a first electrode assembly and a second electrode assembly;
the first electrode assembly includes a plurality of metal layers, each metal layer being connected by a plurality of first connecting members;
the second electrode assembly includes a plurality of metal layers, each metal layer being connected by a plurality of second connecting members;
the number of the metal layers of the first electrode assembly is equal to that of the metal layers of the second electrode assembly, and each metal layer of the first electrode assembly and each metal layer of the second electrode assembly form an interdigital structure in the horizontal direction;
the thicknesses of the topmost metal layer of the first electrode assembly and the topmost metal layer of the second electrode assembly are not smaller than a preset first thickness threshold, the thicknesses of other metal layers of the first electrode assembly and the other metal layers of the second electrode assembly are not larger than a preset second thickness threshold, and the first thickness threshold is larger than the second thickness threshold;
the topmost metal layer of the first electrode assembly comprises a first rectangular metal strip and a plurality of first grid fingers extending outwards vertically at one side of the first rectangular metal strip;
the topmost metal layer of the second electrode assembly comprises a second rectangular metal strip and a plurality of second grid fingers extending outwards vertically at one side of the second rectangular metal strip;
the first grid fingers and the second grid fingers form an interdigital structure in the horizontal direction;
each metal layer except the topmost metal layer in the first electrode assembly comprises a plurality of first fishbone-shaped metal assemblies which are tiled;
the first fishbone type metal component comprises a first metal trunk and a plurality of third grid fingers extending outwards vertically at two sides of the first metal trunk;
each first metal trunk of each layer is vertically aligned with one first gate finger;
each metal layer except the topmost metal layer in the second electrode assembly comprises a plurality of tiled second fishbone type metal assemblies;
the second fishbone type metal component comprises a second metal trunk and a plurality of fourth grid fingers which extend outwards vertically at two sides of the second metal trunk;
each second metal trunk of each layer is vertically aligned with one second gate finger;
each metal layer of the first electrode assembly corresponds to each metal layer of the second electrode assembly one by one;
the first fishbone-shaped metal components and the second fishbone-shaped metal components which are adjacent left and right in each metal layer realize mutual interdigital in the horizontal direction through each third grid finger and each fourth grid finger on opposite sides;
in the upper and lower adjacent metal layers, the first fishbone type metal component and the second fishbone type metal component realize mutual interdigital in the vertical direction through each third grid finger and each fourth grid finger on the same side;
the first gate finger and the first metal trunk are respectively provided with a corresponding first through hole, the first connecting piece is a metal connecting column, and each metal layer of the first electrode assembly is connected through a plurality of metal connecting columns penetrating through the first through hole of each metal layer;
the second gate finger and the second metal trunk are respectively provided with a corresponding second through hole, the second connecting piece is a metal connecting column, and each metal layer of the second electrode assembly is connected through a plurality of metal connecting columns penetrating through the second through holes of each metal layer;
the first thickness threshold is 3.5 μm and the second thickness threshold is 0.145 μm.
2. The low loss on-chip capacitor of claim 1, wherein an oxide fill layer is between adjacent metal layers in the first electrode assembly; an oxide filling layer is arranged between adjacent metal layers in the second electrode assembly.
3. The low-loss on-chip capacitor of claim 1, wherein the specific values of the first thickness threshold and the second thickness threshold depend on the process employed by the low-loss on-chip capacitor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310665303.4A CN116403995B (en) | 2023-06-07 | 2023-06-07 | Low-loss on-chip capacitor |
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| CN202310665303.4A CN116403995B (en) | 2023-06-07 | 2023-06-07 | Low-loss on-chip capacitor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200901247A (en) * | 2007-06-27 | 2009-01-01 | Ind Tech Res Inst | Interdigital capacitor |
| US8536016B2 (en) * | 2009-05-22 | 2013-09-17 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit system with hierarchical capacitor and method of manufacture thereof |
| US9269492B2 (en) * | 2012-10-02 | 2016-02-23 | Qualcomm Incorporated | Bone frame, low resistance via coupled metal oxide-metal (MOM) orthogonal finger capacitor |
| US9331013B2 (en) * | 2013-03-14 | 2016-05-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated capacitor |
| US9685433B2 (en) * | 2013-09-25 | 2017-06-20 | Taiwan Semiconductor Manufacturing Company Ltd. | Capacitor device |
| US11552030B2 (en) * | 2018-07-31 | 2023-01-10 | Intel Corporation | High frequency capacitor with inductance cancellation |
| EP4007001A1 (en) * | 2020-11-30 | 2022-06-01 | NXP USA, Inc. | Integrated capacitors in an integrated circuit |
| CN115528024A (en) * | 2021-06-25 | 2022-12-27 | 瑞昱半导体股份有限公司 | Compact capacitor structure |
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