CN101419969A - Metal-oxide-metal capacitor construction - Google Patents
Metal-oxide-metal capacitor construction Download PDFInfo
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- CN101419969A CN101419969A CNA2008101864049A CN200810186404A CN101419969A CN 101419969 A CN101419969 A CN 101419969A CN A2008101864049 A CNA2008101864049 A CN A2008101864049A CN 200810186404 A CN200810186404 A CN 200810186404A CN 101419969 A CN101419969 A CN 101419969A
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Abstract
The invention provides a metal-oxide-metal capacitor structure which comprises a dielectric layer, a first net-shaped metal layer and a second net-shaped metal layer. The first net-shaped metal layer and the second net-shaped metal layer are embedded into the dielectric layer, and the second net-shaped metal layer is parallel stacked above the first net-shaped metal layer; each net-shaped metal layer is provided with a plurality of openings which are arranged in an array; net intersection points in the first net-shaped metal layer are respectively corresponding to the openings arranged in the second net-shaped metal layer, and the net intersection points in the second net-shaped metal layer are respectively corresponding to the openings arranged in the first net-shaped metal layer. The metal-oxide-metal capacitor structure can effectively improve the gradient variation and linearity of the manufacturing process, thus further improving the efficiency of integrated circuits.
Description
Technical field
The present invention is relevant for a kind of integrated circuit (IC) design, particularly relevant for a kind of metal-oxide-metal electric capacity (MOM) structure with minimum graded (minimized gradient variation) characteristic and linearity (linearity).
Background technology
Many numerals and analog component and circuit successfully apply to semiconductor integrated circuit, for example radio frequency (radio-freq uency, RF) circuit or composite signal integrated circuits (mixed-signal integrated circuit, MSIC).Above-mentioned parts have comprised passive device, for example resistance, electric capacity or inductance or the like.Typical semiconductor integrated circuit comprises a silicon base.The above dielectric layer of one deck is arranged in the substrate, and the above metal level of one deck is arranged in the dielectric layer.These metal levels can form the built-in parts of wafer by existing manufacture of semiconductor technology, wafer built-in (on-chip) metal-insulator-metal (metal-insulator-metal for example, MIM) capacity cell or metal-oxide-metal (metal-oxide-metal, MOM).
Typical metal-insulator-metal (MIM) capacity cell comprises a metal level and a conducting plate, and this conducting plate is positioned at above-mentioned metal level below and is parallel to each other, and a dielectric materials layer, and it is between above-mentioned conducting plate and above-mentioned metal level.The shortcoming of this capacitance structure is that it needs extra light shield to become the original conducting plate of making original metal level below, causes the increase of manufacturing cost.
In order to reduce the cost of manufacture of the required wafer of MIM capacity cell, use the MOM capacity cell mostly instead.Because the unit-area capacitance value of MOM capacity cell does not have the MIM capacity cell big, so in order to improve the capacitance of unit are, most MOM capacity cells adopts and piles up finger-fork type (stacked interdigital finger) capacity cell.Above-mentioned capacity cell has vertical parallel plate structure (vertical parallelplate structure) and forms and to have large-area side direction MOM capacitance and to make unit are have higher capacitance.Figure 1A shows the existing finger-fork type capacitance structure 100 that is used for integrated circuit.Finger-fork type capacitance structure 100 comprise by a plurality of plate electrodes that are arranged in parallel 110 and 120 and intervenient dielectric layer (not illustrating) constituted.Plate electrode 110 is by a plurality of metal level 110a that pile up and therebetweenly constituted in order to interlayer connector (via plug) 110b that electrically connects metal level 110a, and plate electrode 120 is made of a plurality of metal level 120a that pile up and therebetween interlayer connector 120b in order to electric connection metal level 120a.Moreover a metal level (not illustrating) is connected in the same side of each metal level 110a that is positioned at top layer (uppermost) and is electrically connected to a node A (not illustrating).Similarly, another metal level (not illustrating) is connected in the same side of each metal level 120a that is positioned at top layer and is electrically connected to a Node B (not illustrating), shown in Figure 1B.Because adjacent plate electrode 110 and 120 forms large-area side direction electric capacity, so unit are has higher capacitance.Moreover, can be used for the standard CMOS processing procedure usually as the metal level 110a and the 120a of capacitance electrode, need extra light shield cost, so can reduce manufacturing cost.
Yet, plate electrode 110 and 120 in the above-mentioned capacity cell with finger-fork type structure for example, is symmetrical in the one dimension direction respectively on one side, and be asymmetric, and make finger-fork type capacitance structure 100 suffer the problem and the not good problem of the linearity of processing procedure character gradient in other dimensions.
Summary of the invention
In view of this, the invention provides a kind of MOM capacitance structure, wherein MOM electric capacity piles up by a plurality of net metal electrodes and forms a network (latticestructure), and makes the MOM capacity cell have two dimension and three-dimensional symmetrical structure, thereby improves the electric capacity matching properties and the linearity.
The invention provides a kind of MOM capacitance structure.This capacitance structure comprises: a dielectric layer, one first net-shaped metal layer and one second net-shaped metal layer.Dielectric layer is arranged in the substrate.First net-shaped metal layer is embedded in a ground floor position of dielectric layer and has a plurality of first openings that are arranged in an array, and second net-shaped metal layer is embedded in a second layer position of the ground floor position that is higher than dielectric layer and have a plurality of second openings that are arranged in an array.Wherein, a plurality of first net intersection points in first net-shaped metal layer correspond respectively to second opening, and a plurality of second net intersection points in second net-shaped metal layer correspond respectively to first opening.
The invention provides a kind of MOM capacitance structure.This capacitance structure comprises: be arranged at a suprabasil dielectric layer and a plurality of net-shaped metal layer of stacked in parallel in it.Each net-shaped metal layer has a plurality of openings that are arranged in an array.A plurality of net intersection points in each odd number net-shaped metal layer correspond respectively to the opening in each even number net-shaped metal layer, and a plurality of net intersection points in each even number net-shaped metal layer correspond respectively to the opening in each odd number net-shaped metal layer.The odd number net-shaped metal layer is electrically connected to a first node, and the even number net-shaped metal layer is electrically connected to a Section Point.
Metal-oxide-metal capacitance structure of the present invention can effectively improve the processing procedure character gradient and the linearity, and further promotes the usefulness of integrated circuit.
Description of drawings
Figure 1A shows the existing finger-fork type capacitance structure sectional perspective perspective diagram that is used for integrated circuit.
Figure 1B is the floor map that shows Figure 1A.
Fig. 2 is metal-oxide-metal (MOM) the capacitance structure sectional perspective perspective diagram that shows according to the embodiment of the invention.
Fig. 3 shows an odd number net-shaped metal layer part plan schematic diagram among Fig. 5.
Fig. 4 shows an even number net-shaped metal layer part plan schematic diagram among Fig. 5.
Fig. 5 shows the floor map of piling up net-shaped metal layer among the 3rd and 4 figure.
Fig. 6 is the volume rendering schematic diagram that shows the net-shaped metal layer of piling up among Fig. 5.
Embodiment
The present invention is applicable to different integrated circuit (IC) design about a kind of capacitance structure of improvement, for example mixed signal circuit, radio circuit and analog circuit.Below cooperate Fig. 2 to Fig. 5 that the capacitor structure of integrated circuit that is used for of the embodiment of the invention is described.Please refer to Fig. 2, it shows metal-oxide-metal (MOM) the capacitance structure sectional perspective perspective diagram according to the embodiment of the invention.MOM capacitance structure 300 comprises: a dielectric layer 202, embed a plurality of netted (net-shaped) metal level 210 and 220 and in order to electrically connect the internal connection-wire structure of odd number net-shaped metal layer 210 and even number net-shaped metal layer 220 wherein.
Odd number net-shaped metal layer 210 and even number net-shaped metal layer 220 are embedded in the different layers position of dielectric layer 202 in regular turn.That is odd number net-shaped metal layer 210 and even number net-shaped metal layer 220 replace stacked in parallel in dielectric layer 202 with a spacing.The quantity that is noted that net-shaped metal layer is at least two, yet is understandable that in fact the quantity of net-shaped metal layer depends on circuit design.Herein for convenience of description, present embodiment only illustrates four-layer network shape metal level and illustrates as example.Herein, label " 210 " expression is positioned at odd number net-shaped metal layer in the substrate 200, and label " 220 " expression is positioned at even number net-shaped metal layer in the substrate 200.Odd number net-shaped metal layer 210 and even number net-shaped metal layer 220 can be made of copper metal, aluminum metal or its alloy, and can form by existing embedding technique.Moreover in the present embodiment, odd number net-shaped metal layer 210 is of similar shape and size each other, and the complete each other overlapping arrangement of the projection on plane, substrate place.Even number net-shaped metal layer 220 also is of similar shape and size each other, and the complete each other overlapping arrangement of the projection on plane, substrate place.Moreover odd number net-shaped metal layer 210 can have size identical or inequality with even number net-shaped metal layer 220.
In addition, odd number net-shaped metal layer 210 is electrically connected to each other by internal connection-wire structure, and is electrically connected to a first node (not illustrating).Similarly, even number net-shaped metal layer 220 is electrically connected to each other by internal connection-wire structure, and is electrically connected to a Section Point (not illustrating) that is different from a first node.First node and Section Point make adjacent net-shaped metal layer have different polarity as two end points of MOM capacitance structure 300.In the present embodiment, internal connection-wire structure is made of a plurality of contact mat 210b and 220b and a plurality of interlayer connector (via plug) 240 and will be illustrated after a while in this paper.Moreover graphic clearer in order to make, Fig. 2 only selectivity shows a little interlayer connector 240, and omits a little contact mat 220b.
Please refer to Fig. 3, it shows one of them part plan schematic diagram of odd number net-shaped metal layer among Fig. 2 210.Net-shaped metal layer 210 has a plurality of opening 210a that are arranged in an array.A plurality of contact mat 210b correspondences are embedded in the dielectric layer 202 in each opening 210a, and are positioned at identical layer position with net-shaped metal layer 210.That is a plurality of contact mat 210b and net-shaped metal layer 210 can be formed by same metal level definition.Each contact mat 210b can have rectangle, square, polygon or the circular profile of overlooking.In the present embodiment, each contact mat 210b is as the example explanation with square.Moreover each contact mat 210b is positioned at the center of corresponding opening 210a substantially.
Then, please refer to Fig. 4, it shows one of them part plan schematic diagram of even number net-shaped metal layer among Fig. 2 220.Similar in appearance to net-shaped metal layer 210, net-shaped metal layer 220 has a plurality of opening 220a that are arranged in an array.A plurality of contact mat 220b correspondences are embedded in the dielectric layer 202 in each opening 220a, and are positioned at identical layer position with net-shaped metal layer 220.That is a plurality of contact mat 220b and net-shaped metal layer 220 can be formed by same metal level definition.Each contact mat 220b can have rectangle, square, polygon or the circular profile of overlooking equally.In the present embodiment, each contact mat 220b is as the example explanation with square.Moreover each contact mat 220b is positioned at the center of corresponding opening 220a substantially.
In the present embodiment, specifically a plurality of net intersection points (dashed region) 210c in the odd number net-shaped metal layer 210 corresponds respectively to the opening 220a in the even number net-shaped metal layer 220 among Fig. 4 among Fig. 3, and a plurality of net intersection points (dashed region) 220c in the even number net-shaped metal layer 220 corresponds respectively to the opening 210a in the odd number net-shaped metal layer 210.
Please refer to Fig. 2 to Fig. 5, wherein Fig. 5 shows the floor map of piling up net-shaped metal layer among Fig. 3 and Fig. 4.Because the net intersection point 210c in the odd number net-shaped metal layer 210 corresponds respectively to the opening 220a in the even number net-shaped metal layer 220, and the net intersection point 220c in the even number net-shaped metal layer 220 corresponds respectively to the opening 210a in the odd number net-shaped metal layer 210, make the contact mat 220b of the opening 220a that is positioned at even number net-shaped metal layer 220 distinguish aligned in general, and make the contact mat 210b of the opening 210a that is positioned at odd number net-shaped metal layer 210 distinguish aligned in general in the net intersection point 220c of even number net-shaped metal layer 220 in the net intersection point 210c of odd number net-shaped metal layer 210.
A plurality of interlayer connectors 240 are arranged at adjacent odd number net-shaped metal layer 210 and the dielectric layer 202 between the even number net-shaped metal layer 220, be connected to the net intersection point 210c of odd number net-shaped metal layer 210 with the contact mat 220b of the opening 220a that will be positioned at even number net-shaped metal layer 220, and the contact mat 210b that will be positioned at the opening 210a of odd number net-shaped metal layer 210 is connected to the net intersection point 220c of even number net-shaped metal layer 220, as Fig. 2 and shown in Figure 5.Thus, the MOM capacity cell piles up by odd number net-shaped metal layer 210 and even number net-shaped metal layer 220 and forms a network (latticestructure), makes it have two dimension and three-dimensional symmetrical structure.
Can form by existing embedding technique by a plurality of contact mat 210b and 220b and a plurality of interlayer connector (via plug) 240 internal connection-wire structures that constituted.Therefore, according to the MOM capacitance structure of the embodiment of the invention, can form the built-in parts of wafer by existing manufacture of semiconductor technology equally, with effective reduction cost of manufacture.
Moreover, but the above-mentioned MOM capacitance structure along continuous straight runs that piles up extends and repeated arrangement and constitute a multiple MOM capacitance structure vertically.
In above-mentioned multiple MOM capacitance structure, adjacent net-shaped metal layer can form an electric capacity.Moreover the interlayer connector can be respectively forms two electric capacity with adjacent net-shaped metal layer.In addition, contact mat and adjacent net-shaped metal layer also can form an electric capacity, as shown in Figure 6.Therefore, the unit are of above-mentioned capacitance structure has high capacitance, and increases the total capacitance value of MOM capacitive element.
In addition, be different from existing finger-fork type capacitance structure, the MOM capacitance structure with two dimension and three-dimensional symmetric net lattice structure according to the embodiment of the invention can effectively improve the processing procedure character gradient and the linearity, and further promotes the usefulness of integrated circuit.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
100: the finger-fork type capacitance structure
110,120: plate electrode
110a, 120a: metal level
110b, 120b: interlayer connector
200: substrate
202: dielectric layer
210,220: net-shaped metal layer
210a, 220a: opening
210b, 220b: contact mat
210c, 220c: net intersection point
The 300:MOM capacitance structure.
Claims (19)
1. a metal-oxide-metal capacitance structure is characterized in that, comprising:
One dielectric layer is arranged in the substrate;
One first net-shaped metal layer is embedded in a ground floor position of this dielectric layer, and has a plurality of first openings that are arranged in an array; And
One second net-shaped metal layer, be embedded in a second layer position of this ground floor position that is higher than this dielectric layer, and have a plurality of second openings that are arranged in an array, wherein a plurality of first net intersection points in this first net-shaped metal layer correspond respectively to described second opening, and a plurality of second net intersection points in this second net-shaped metal layer correspond respectively to described first opening.
2. metal-oxide-metal capacitance structure according to claim 1 is characterized in that, this first net-shaped metal layer is electrically connected to a first node, and this second net-shaped metal layer is electrically connected to a Section Point.
3. metal-oxide-metal capacitance structure according to claim 1 is characterized in that, this first net-shaped metal layer has identical size with this second net-shaped metal layer.
4. metal-oxide-metal capacitance structure according to claim 1 is characterized in that, more comprises:
A plurality of first contact mats, correspondence are embedded in this ground floor position of this dielectric layer in described first opening, make described first contact mat respectively in alignment with the described second net intersection point;
A plurality of first interlayer connectors connect described first contact mat and the corresponding described second net intersection point respectively;
A plurality of second contact mats, correspondence are embedded in this second layer position of this dielectric layer in described second opening, make described second contact mat respectively in alignment with the described first net intersection point; And
A plurality of second interlayer connectors connect described second contact mat and the corresponding described first net intersection point respectively.
5. metal-oxide-metal capacitance structure according to claim 4 is characterized in that, each first contact mat has rectangle, square, polygon or the circular profile of overlooking.
6. metal-oxide-metal capacitance structure according to claim 4 is characterized in that, each first contact mat is positioned at the center of this corresponding first opening.
7. metal-oxide-metal capacitance structure according to claim 4 is characterized in that, each second contact mat has rectangle, square, polygon or the circular profile of overlooking.
8. metal-oxide-metal capacitance structure according to claim 4 is characterized in that, each second contact mat is positioned at the center of this corresponding second opening.
9. metal-oxide-metal capacitance structure according to claim 4 is characterized in that, more comprises:
One the 3rd net-shaped metal layer, be embedded in one the 3rd layer of position of this second layer position that is higher than this dielectric layer, and have a plurality of the 3rd openings that are arranged in an array, wherein the 3rd net-shaped metal layer and this first net-shaped metal layer are of similar shape and size, and the 3rd net-shaped metal layer and the projection of this first net-shaped metal layer on this plane, substrate place are overlapping fully;
A plurality of the 3rd contact mats, correspondence are embedded in the 3rd layer of position of this dielectric layer in described the 3rd opening, make described the 3rd contact mat respectively in alignment with described second net intersection point and described first contact mat; And
A plurality of the 3rd interlayer connectors connect described the 3rd contact mat and the corresponding described second net intersection point respectively.
10. metal-oxide-metal capacitance structure according to claim 9 is characterized in that, each the 3rd contact mat has rectangle, square, polygon or the circular profile of overlooking.
11. metal-oxide-metal capacitance structure according to claim 9 is characterized in that, each the 3rd contact mat is positioned at the center of the 3rd corresponding opening.
12. metal-oxide-metal capacitance structure according to claim 9 is characterized in that, more comprises:
One the 4th net-shaped metal layer, be embedded in one the 4th layer of position of the 3rd layer of position that is higher than this dielectric layer, and have a plurality of the 4th openings that are arranged in an array, wherein the 4th net-shaped metal layer and this second net-shaped metal layer are of similar shape and size, and the 4th net-shaped metal layer and the projection of this second net-shaped metal layer on this plane, substrate place are overlapping fully;
A plurality of the 4th contact mats, correspondence are embedded in the 4th layer of position of this dielectric layer in described the 4th opening, make described the 4th contact mat respectively in alignment with a plurality of the 3rd net intersection points and described second contact mat of the 3rd net-shaped metal layer; And
A plurality of the 4th interlayer connectors connect described the 4th contact mat and corresponding described the 3rd net intersection point respectively.
13. metal-oxide-metal capacitance structure according to claim 12 is characterized in that, each the 4th contact mat has rectangle, square, polygon or the circular profile of overlooking.
14. metal-oxide-metal capacitance structure according to claim 12 is characterized in that, each the 4th contact mat is positioned at the center of the 4th corresponding opening.
15. a metal-oxide-metal capacitance structure is characterized in that, comprising:
One dielectric layer is arranged in the substrate; And
A plurality of net-shaped metal layer, stacked in parallel are in this dielectric layer, and each net-shaped metal layer has a plurality of openings that are arranged in an array;
Wherein a plurality of net intersection points in each odd number net-shaped metal layer correspond respectively to described opening in each even number net-shaped metal layer and a plurality of net intersection points in each even number net-shaped metal layer and correspond respectively to described opening in each odd number net-shaped metal layer;
Wherein said odd number net-shaped metal layer is electrically connected to a first node, and described even number net-shaped metal layer is electrically connected to a Section Point.
16. metal-oxide-metal capacitance structure according to claim 15 is characterized in that, more comprises:
A plurality of contact mats, correspondence is embedded in this interior dielectric layer of described opening of described net-shaped metal layer, the described contact mat that makes the described opening that is positioned at described even number net-shaped metal layer is respectively in alignment with a plurality of net intersection points of described odd number net-shaped metal layer, and the described contact mat that makes the described opening that is positioned at described odd number net-shaped metal layer is respectively in alignment with a plurality of net intersection points of described even number net-shaped metal layer; And
A plurality of interlayer connectors, the described contact mat that will be positioned at the described opening of described even number net-shaped metal layer is connected to a plurality of net intersection points adjacent to described odd number net-shaped metal layer, and the described contact mat that will be positioned at the described opening of described odd number net-shaped metal layer is connected to a plurality of net intersection points adjacent to described even number net-shaped metal layer.
17. metal-oxide-metal capacitance structure according to claim 16 is characterized in that, each contact mat has rectangle, square, polygon or the circular profile of overlooking.
18. metal-oxide-metal capacitance structure according to claim 16 is characterized in that, each contact mat is positioned at the center of this corresponding opening.
19. metal-oxide-metal capacitance structure according to claim 15 is characterized in that described net-shaped metal layer has identical size.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008101864049A CN101419969A (en) | 2008-12-16 | 2008-12-16 | Metal-oxide-metal capacitor construction |
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2008101864049A CN101419969A (en) | 2008-12-16 | 2008-12-16 | Metal-oxide-metal capacitor construction |
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| CNA2008101864049A Pending CN101419969A (en) | 2008-12-16 | 2008-12-16 | Metal-oxide-metal capacitor construction |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102637583A (en) * | 2012-04-20 | 2012-08-15 | 上海华力微电子有限公司 | Preparation method of multilayer metal-monox-metal capacitor |
| CN104576647A (en) * | 2013-10-22 | 2015-04-29 | 旺宏电子股份有限公司 | Integrated circuit, and manufacturing method and operating method thereof |
| CN105097768A (en) * | 2014-05-23 | 2015-11-25 | 力晶科技股份有限公司 | Capacitor structure and manufacturing method thereof |
| CN110323334A (en) * | 2019-07-09 | 2019-10-11 | 四川中微芯成科技有限公司 | A kind of structure and method for making ADC capacitor of parasitic capacitance |
-
2008
- 2008-12-16 CN CNA2008101864049A patent/CN101419969A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102637583A (en) * | 2012-04-20 | 2012-08-15 | 上海华力微电子有限公司 | Preparation method of multilayer metal-monox-metal capacitor |
| CN102637583B (en) * | 2012-04-20 | 2015-05-20 | 上海华力微电子有限公司 | Preparation method of multilayer metal-monox-metal capacitor |
| CN104576647A (en) * | 2013-10-22 | 2015-04-29 | 旺宏电子股份有限公司 | Integrated circuit, and manufacturing method and operating method thereof |
| CN104576647B (en) * | 2013-10-22 | 2017-10-17 | 旺宏电子股份有限公司 | Integrated circuit and its manufacture method and operating method |
| CN105097768A (en) * | 2014-05-23 | 2015-11-25 | 力晶科技股份有限公司 | Capacitor structure and manufacturing method thereof |
| CN110323334A (en) * | 2019-07-09 | 2019-10-11 | 四川中微芯成科技有限公司 | A kind of structure and method for making ADC capacitor of parasitic capacitance |
| CN110323334B (en) * | 2019-07-09 | 2023-03-24 | 四川中微芯成科技有限公司 | Structure and method for using parasitic capacitor as ADC capacitor |
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Open date: 20090429 |