CN104576647A - Integrated circuit, and manufacturing method and operating method thereof - Google Patents
Integrated circuit, and manufacturing method and operating method thereof Download PDFInfo
- Publication number
- CN104576647A CN104576647A CN201310497136.3A CN201310497136A CN104576647A CN 104576647 A CN104576647 A CN 104576647A CN 201310497136 A CN201310497136 A CN 201310497136A CN 104576647 A CN104576647 A CN 104576647A
- Authority
- CN
- China
- Prior art keywords
- conductive structure
- integrated circuit
- conductive
- forked
- shank portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000011017 operating method Methods 0.000 title abstract description 5
- 238000010276 construction Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 description 11
- 238000003860 storage Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000011010 flushing procedure Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an integrated circuit, and a manufacturing method and an operating method thereof. The integrated circuit comprises a forked construction and a first conductive structure. The forked construction comprises a handle part, branch parts extending from the handle part, a laminated structure and a dielectric layer. The dielectric layer is positioned between the first conductive structure and the laminated structure of the handle part.
Description
Technical field
The invention relates to a kind of integrated circuit and manufacture method thereof and method of operation, and relate to a kind of memory and manufacture method thereof and method of operation especially.
Background technology
Storage device is used in many products, such as, in the storage unit of MP3 player, digital camera, computer archives etc.Along with the increase of application, the demand for storage device also tends to less size, larger memory capacity.In response to this demand, it is the storage device needing to manufacture high component density.
Because device critical dimension has been reduced to the limit of technology, therefore designers develop a kind of method improving density of memory devices is use 3-D stacks storage device, uses and reaches higher memory capacity, reduce the cost of each bit simultaneously.But the structure of this kind of storage device complexity also makes manufacture method become complicated.In addition, operability is by the restriction designed.
Summary of the invention
The invention relates to a kind of integrated circuit and manufacture method thereof and method of operation, method for manufacturing integrated circuit is simple and operating efficiency is high.
According to an embodiment, propose a kind of integrated circuit, it comprises a forked structure and one first conductive structure.Forked structure comprises a shank portion and the component extended from shank portion.Forked structure comprises a laminated construction and a dielectric layer.Dielectric layer is between the first conductive structure and the laminated construction of shank portion.
According to another embodiment, propose a kind of manufacture method of integrated circuit, comprise the following steps.A forked structure is formed on a substrate.Forked structure comprises a shank portion and the component extended from shank portion.Forked structure comprises a laminated construction and a dielectric layer is formed on laminated construction.One first conductive structure is formed on dielectric layer.Dielectric layer is between the first conductive structure and the laminated construction of shank portion.
According to another embodiment again, a kind of method of operation of integrated circuit is proposed.Integrated circuit comprises a bit line and one first conductive structure.Bit line has a pronged shape, comprises a shank portion and the component extended from shank portion.First conductive structure is configured on the shank portion of bit line, and is used as a serial selection line.The method of operation of integrated circuit comprises the following steps.There is provided one first voltage to the first conductive structure, to control the shank portion of bit line and component for selection mode or non-selected state.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating institute's accompanying drawings, being described in detail below:
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the integrated circuit according to an embodiment.
Fig. 2 is the top view of the integrated circuit according to an embodiment.
Fig. 3 A to Fig. 3 C illustrates the manufacture method of the integrated circuit according to an embodiment.
Fig. 4 is the top view of the integrated circuit according to an embodiment.
Fig. 5 is the top view of the integrated circuit according to an embodiment.
Fig. 6 is the top view of the integrated circuit according to an embodiment.
Fig. 7 is the top view of the integrated circuit according to an embodiment.
Fig. 8 is the top view of the integrated circuit according to an embodiment.
[symbol description]
102: forked structure
104, the 104A, 104D: first conductive structure
106: laminated construction
108: dielectric layer
110: substrate
112: conductive stripe
114: dielectric striped
116: shank portion
118: component
120: the first current-carrying parts
122: the second current-carrying parts
124: upper surface
126: upper surface
128, the 128A, 128B, 128C: second conductive structure
130: upper surface
132: wordline
134: ground connection selects line
136: source pad
138: stepped portion
140: the first voltages
142A, 142B: the second voltage
144, the 144C: the first current-carrying part
146, the 146C: the second current-carrying part
148,148C: upper surface
150,150C: upper surface
152: part
154: part
156A, 156B: first layer metal wire
158A, 158B, 158C, 158D, 158E, 158F, 158G, 158H, 158I, 158J, 158K, 158L: second layer metal wire
160: the first conductive plungers
162: the second conductive plungers
Embodiment
Please refer to Fig. 1, it is the schematic diagram of the integrated circuit according to an embodiment.Integrated circuit comprises forked structure 102 and one first conductive structure 104.
Forked structure 102 comprises laminated construction 106 and a dielectric layer 108.Separated from each otherly the laminated construction 106 of same page (such as extending toward Z-direction) configures on a substrate 110.Laminated construction 106 is each to be formed with dielectric striped 114 by multiple cross laminates and for the conductive stripe 112 of vertical bar shape.Conductive stripe 112 is not limited to as shown in the figure 4 layers, also can be the number of plies that other are suitable, such as 8 layers.Dielectric layer 108 is configured on laminated construction 106.Forked structure 102 comprises a shank portion 116 and the multiple components 118 extended from shank portion 116.The component 118 extended from single shank portion 116 is not limited to as shown in the figure two, and can be other more numbers.
First conductive structure 104 is configured on the shank portion 116 of dielectric layer 108, and by dielectric layer 108 separately from the conductive stripe 112 of laminated construction 106.In this embodiment, the first conductive structure 104 comprises one first contiguous current-carrying part 120 and one second current-carrying part 122, respectively away from the component 118 with close forked structure 102.One upper surface 124 of the first current-carrying part 120 is higher than forked structure 102.One upper surface 126 of the second current-carrying part 122 is the upper surfaces flushing forked structure 102 (such as dielectric layer 108 or dielectric striped 114).
Integrated circuit more can comprise multiple second conductive structure 128, is configured in respectively on the lateral wall of its component 118 separated from each other of dielectric layer 108, and by dielectric layer 108 separately from the conductive stripe 112 of forked structure 102.In this embodiment, a upper surface 130 of the second conductive structure 128 is the upper surfaces flushing forked structure 102 (such as dielectric layer 108 or dielectric striped 114).
In one embodiment, integrated circuit is a three-dimensional storage lamination, such as three-dimensional perpendicular grid nand flash memory (3D vertical gate NAND flash), can more comprise multiple conductive layer, it comprises wordline (WL) 132 and selects line (GSL) 134 with ground connection, be separated from each other and be configured on the component 118 of forked structure 102 abreast, its bearing of trend (such as X-direction) can perpendicular to the bearing of trend of component 118 (such as Z-direction); Also the source pad (source pad) 136 of extending from the component 118 of conductive stripe 112 can be comprised.The source pad of different layers can be electrically connected to source line (common source line altogether respectively by conductive plunger; CSL).The conductive stripe 112 of laminated construction 106 is used as bit line.First conductive structure 104 and the second conductive structure 128 are used as serial selection line (SSL).Conductive stripe 112 comprises the stepped portion 138 of extending from shank portion 116, and it can be shared with the conductive stripe of another forked structure (not illustrating).
The dielectric striped 114 of laminated construction 106 is similar to conductive stripe 112, for the structure that vertical bar shape extends continuously, and the structure of integrated circuit in order to clear expression embodiment, Fig. 1 does not show the part that dielectric striped 114 is selected between line 134 and source pad 136 between the first conductive structure 104, second conductive structure 128, wordline 132, ground connection.
The method of operation of integrated circuit comprises provides one first voltage 140 to the first conductive structure 104, with the shank portion 116 controlling conductive stripe (bit line) 112 with component 118 for select (unlatching) state or non-selected (closedown) state.In addition, the second voltage 142A, 142B to the second conductive structure 128 is provided respectively, to control the component 118 of contiguous conductive stripe 112 for selection mode or non-selected state.Page selection mode is simple, and the operating efficiency of array is high.
In one embodiment, first conductive structure 104 is normal closed condition (normally OFF), and the general state of the second conductive structure 128 is designed to normal opening (normally ON), and (such as the first voltage 140 is for closing voltage, second voltage 142A, 142B is cut-in voltage or suspension joint (floating)), make whole forked conductive stripe (bit line) 112 in opening by this.In one operating procedure, providing the first voltage 140 with in the process of opening, the component 118 controlling the conductive stripe 112 of adjacent second conductive structure 128 by second voltage 142A, 142B is further the state of non-selected (closedown).In another operating procedure, can pass through the first conductive structure 104, to control corresponding forked conductive stripe 112 whole be unselected state.Page selection mode is simple, and the operating efficiency of array is high.
Please refer to Fig. 2, it is the top view of the integrated circuit according to an embodiment, and it has 8 forked structures 102.Comprise the first current-carrying part 120 to be arranged, respectively on the shank portion 116 of different forked structures 102 from the first conductive structure 104 of the second current-carrying part 122.Single the second conductive structure 128 be abut against two forked structures 102 of difference component 118 between.In one embodiment, for example, the first conductive structure 104 is normal closed condition (normally OFF), and the general state of the second conductive structure 128 is designed to normal opening (normally ON).Further, in an operating procedure, in the process of the first voltage 140 that unlatching is provided, be that the component 118 of the conductive stripe 112 controlling arbitrarily adjacent second conductive structure 128 is for selecting or unselected state.For example, can pass through third left second conductive structure 128, the component 118 controlling fourth left and the 5th conductive stripe 112 is unselected state, and its component 118 in the conductive stripe 112 away from third left second conductive structure 128 then maintains opening.In another embodiment, can pass through any one first conductive structure 104, to control corresponding forked conductive stripe 112 whole be unselected state.Page selection mode is simple, and the operating efficiency of array is high.
Fig. 3 A to Fig. 3 C illustrates the manufacture method of the integrated circuit according to an embodiment.
Please refer to Fig. 3 A, on substrate 110, form laminated construction 106.Forked laminated construction 106 comprises shank portion 116 and the multiple components 118 extended from shank portion 116.The formation method of laminated construction 106 is included in cross laminates conductive film and dielectric film (not shown) on substrate 110, then gold-tinted photoetching process patterned conductive thin film and dielectric film is utilized, to form forked conductive stripe 112 and dielectric striped 114.Then, dielectric layer 108 is formed on laminated construction 106.Laminated construction 106 and dielectric layer 108 form forked structure 102.Conductive stripe 112 can comprise metal, (such as adulterating) polysilicon, metal silicide or other suitable electric conducting materials.Dielectric striped 114 and dielectric layer 108 can comprise silica, silicon nitride, silicon oxynitride or other suitable materials.Dielectric layer 108 is not limited to ONO three-decker, also can be simple layer or other suitable structures.In embodiment, simultaneously source pad 136 and stepped portion 138 formed with laminated construction 106.
Please refer to Fig. 3 B, on dielectric layer 108, form the first conductive structure 104A, the second conductive structure 128A and conductive layer.Conductive layer is configured on the component 118 of forked structure 102 in parallel to each other.Conductive layer comprises wordline 132, ground connection selects line 134.First conductive structure 104, second conductive structure 128 can be included on forked structure 102 with the formation method of conductive layer and form electric conducting material (not shown), patterned photo glue (not shown) is formed on electric conducting material, removing conductive material is not patterned the part that photoresist covers, and then removes patterned photo glue.
Please refer to Fig. 3 C, remove the first conductive structure 104A (Fig. 3 B) of part, to form the first current-carrying part 120 and the second current-carrying part 122.In addition, the second conductive structure 128A (Fig. 3 B) of part is removed, to form the second conductive structure 128.The formation method of the first conductive structure 104 and the second conductive structure 128 can be included in the structure shown in Fig. 3 B and form patterned photo glue (not shown), remove the first conductive structure 104A and the second conductive structure 128A and be not patterned the part that photoresist covers, then remove patterned photo glue.
Fig. 4 illustrates the top view of the integrated circuit according to an embodiment, and the Discrepancy Description of itself and Fig. 2 is as follows.Second conductive structure 128B comprises one first adjacent current-carrying part 144 and one second current-carrying part 146, respectively away from the shank portion 116 with contiguous forked structure 102.First current-carrying part 144 extends on the upper surface of forked structure 102, and its upper surface 148 is the upper surfaces higher than forked structure 102.The upper surface 150 of the second current-carrying part 146 flushes the upper surface in forked structure 102.In one embodiment, this structure caused from the process shifts of the expected structure of Fig. 2, but still possess the operation usefulness of device expection.Therefore, in other words, the structure and method of embodiment can bear process shifts, and maintains product yield.Second current-carrying part 122 of the first conductive structure 104 and second current-carrying part 146 of the second conductive structure 128B can be identical gold-tinted photoetching process formed simultaneously.
Fig. 5 illustrates the top view of the integrated circuit according to an embodiment, and the Discrepancy Description of itself and Fig. 2 is as follows.Second conductive structure 128C be extend in single component 118 madial wall and lateral wall on, the part 152 wherein on lateral wall is wider than the part 154 on madial wall.The part 152 that this structure can pass through on lateral wall increases grid control area.Second conductive structure 128C comprises the first adjacent current-carrying part 144C and the second current-carrying part 146C, respectively away from the shank portion 116 with contiguous forked structure 102.First current-carrying part 144C extends on the upper surface of forked structure 102, and its upper surface 150C is the upper surface higher than forked structure.The upper surface 150C of the second current-carrying part 146C flushes the upper surface in forked structure 102.Second current-carrying part 122 of the first conductive structure 104 and the second current-carrying part 146C of the second conductive structure 128C can be identical gold-tinted photoetching process formed simultaneously.
Fig. 6 illustrates the top view of the integrated circuit according to an embodiment, and the Discrepancy Description of itself and Fig. 2 is as follows.First conductive structure 104D only exceeds the first current-carrying part 120 of forked structure 102, and eliminates the second current-carrying part 122 (Fig. 2).
Fig. 7 is the top view of the integrated circuit according to an embodiment, wherein for the sake of clarity, does not show the wordline 132 shown in Fig. 2 and selects line 134 with ground connection.Two group patterns respectively have 4 forked structures 102, and share second layer metal wire (M2) 158A to 158F being positioned at top.First conductive structure 104 and the second conductive structure 128C are first layer metal wire 156A and the 156B being electrically connected to top by the first conductive plunger 160 respectively, then are electrically connected to the second layer metal wire 158A to 158F of more top through upper point the second conductive plunger 162.In this example, the first conductive structure 104 is alternately electrically connected to second layer metal wire 158A and 158B.Second conductive structure 128C system of each group pattern is electrically connected to second layer metal wire 158C to 158F one by one.
Fig. 8 is the top view of the integrated circuit according to an embodiment, and the Discrepancy Description of itself and Fig. 7 is as follows.Second conductive structure 128C system is alternately electrically connected to second layer metal wire 158G and 158H.First conductive structure 104 of each group pattern is electrically connected to second layer metal wire 158I to 158L one by one.
In sum, although the present invention with embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (10)
1. an integrated circuit, comprising:
One forked structure, comprise a shank portion and the multiple components extended from this shank portion, this forked structure comprises a laminated construction and a dielectric layer; And
One first conductive structure, this dielectric layer is between this first conductive structure and this laminated construction of this shank portion.
2. integrated circuit according to claim 1, more comprise one second conductive structure, wherein this dielectric layer is between this second conductive structure and this laminated construction of these components.
3. integrated circuit according to claim 1, comprises this forked structure multiple and one second conductive structure, wherein single this second conductive structure be configured in different these forked structures these components between.
4. integrated circuit according to claim 1, more comprise multiple conductive layer and multiple source pad, wherein these conductive layers are parallel to each other and are configured on these components of this forked structure, these conductive layers comprise a wordline (WL) and/or a ground connection selects line (GSL), these source pad are extended from these components of this forked structure, and are electrically connected to source line altogether.
5. integrated circuit according to claim 4, more comprise one second conductive structure, be configured on these components, wherein this first conductive structure and this second conductive structure are used as serial selection line (SSL), this second conductive structure is between this first conductive structure and this wordline, and this ground connection selects line between these source pad and this wordline.
6. integrated circuit according to claim 1, wherein this laminated construction is made up of multiple conductive stripe of cross laminates and dielectric striped.
7. a manufacture method for integrated circuit, comprising:
On a substrate, form a forked structure, comprise a shank portion and the multiple components extended from this shank portion, this forked structure comprises a laminated construction and a dielectric layer is formed on this laminated construction; And
On this dielectric layer, form one first conductive structure, wherein this dielectric layer is between this first conductive structure and this laminated construction of this shank portion.
8. the manufacture method of integrated circuit according to claim 7, more comprises and forms multiple second conductive structure, lay respectively on these different components.
9. a method of operation for integrated circuit, wherein this integrated circuit comprises:
One bit line, has a pronged shape, comprises a shank portion and the multiple components extended from this shank portion; And
One first conductive structure, is configured on this shank portion of this bit line, and is used as a serial selection line, and wherein the method for operation of this integrated circuit comprises:
There is provided one first voltage to this first conductive structure, to control this shank portion of this bit line and these components for selection mode or non-selected state.
10. the method for operation of integrated circuit according to claim 9, wherein this integrated circuit more comprises one second conductive structure, and these components being configured in this bit line wherein at least one, and are used as a serial selection line,
The method of operation of this integrated circuit comprises provides one second voltage to this second conductive structure, to control this at least one component of this bit line this second conductive structure contiguous for selection mode or non-selected state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310497136.3A CN104576647B (en) | 2013-10-22 | 2013-10-22 | Integrated circuit and its manufacture method and operating method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310497136.3A CN104576647B (en) | 2013-10-22 | 2013-10-22 | Integrated circuit and its manufacture method and operating method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104576647A true CN104576647A (en) | 2015-04-29 |
| CN104576647B CN104576647B (en) | 2017-10-17 |
Family
ID=53092325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310497136.3A Active CN104576647B (en) | 2013-10-22 | 2013-10-22 | Integrated circuit and its manufacture method and operating method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104576647B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101419969A (en) * | 2008-12-16 | 2009-04-29 | 威盛电子股份有限公司 | Metal-oxide-metal capacitor construction |
| US20100294352A1 (en) * | 2009-05-20 | 2010-11-25 | Uma Srinivasan | Metal patterning for electrically conductive structures based on alloy formation |
| CN102637583A (en) * | 2012-04-20 | 2012-08-15 | 上海华力微电子有限公司 | Preparation method of multilayer metal-monox-metal capacitor |
-
2013
- 2013-10-22 CN CN201310497136.3A patent/CN104576647B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101419969A (en) * | 2008-12-16 | 2009-04-29 | 威盛电子股份有限公司 | Metal-oxide-metal capacitor construction |
| US20100294352A1 (en) * | 2009-05-20 | 2010-11-25 | Uma Srinivasan | Metal patterning for electrically conductive structures based on alloy formation |
| CN102637583A (en) * | 2012-04-20 | 2012-08-15 | 上海华力微电子有限公司 | Preparation method of multilayer metal-monox-metal capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104576647B (en) | 2017-10-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105359270B (en) | 3D nonvolatile memories with wide-bandgap transistors decoder | |
| US9449966B2 (en) | Three-dimensional semiconductor device and method of manufacturing the same | |
| US7948024B2 (en) | Multi-layered, vertically stacked non-volatile memory device and method of fabrication | |
| CN105023926B (en) | A kind of memory component and preparation method thereof | |
| US9076797B2 (en) | 3D memory array | |
| US20120061637A1 (en) | 3-d structured nonvolatile memory array and method for fabricating the same | |
| US9343322B2 (en) | Three dimensional stacking memory film structure | |
| US10283519B2 (en) | Three dimensional NAND string memory device | |
| US9741731B2 (en) | Three dimensional stacked semiconductor structure | |
| CN110364532A (en) | The silicon silicided level line of autoregistration two and source electrode line bumping pad in vertical channel memory | |
| CN109473445A (en) | Memory device, method of manufacturing the same, and electronic apparatus including the same | |
| CN105845681B (en) | Non-volatile memory and manufacturing method thereof | |
| CN103730435B (en) | Semiconductor structure and manufacture method thereof | |
| CN103579253B (en) | Semiconductor storage unit and its manufacturing method | |
| CN105655485A (en) | Resistive random access memory and manufacturing method thereof | |
| TWI521682B (en) | Integrated circuit and method for manufacturing and operating the same | |
| US20150325585A1 (en) | Method for forming three-dimensional memory and product thereof | |
| CN104576647A (en) | Integrated circuit, and manufacturing method and operating method thereof | |
| TWI580086B (en) | Memory device and manufacturing method of the same | |
| TWI462278B (en) | Semiconductor structure and manufacturing method of the same | |
| CN105990392A (en) | Resistive random access memory and manufacturing method thereof | |
| CN105870120B (en) | non-volatile memory | |
| TWI538168B (en) | Three-dimensional semiconductor device and method of manufacturing the same | |
| CN106158871B (en) | Memory device and method of manufacturing the same | |
| CN103824814B (en) | Semiconductor structure and manufacture method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |