CN107591377A - More the DBC encapsulating structures and method for packing of a kind of power device - Google Patents
More the DBC encapsulating structures and method for packing of a kind of power device Download PDFInfo
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- CN107591377A CN107591377A CN201710816578.8A CN201710816578A CN107591377A CN 107591377 A CN107591377 A CN 107591377A CN 201710816578 A CN201710816578 A CN 201710816578A CN 107591377 A CN107591377 A CN 107591377A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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Abstract
The invention discloses more the DBC encapsulating structures and method for packing of a kind of power device, wherein, the encapsulating structure includes power device, directly covers copper ceramic substrate (i.e. DBC plates), lead, heat-radiating substrate, decoupling capacitance, power terminal and drive terminal and shell, and this encapsulating structure forms the half-bridge circuit being made up of power device；This encapsulating structure and method for packing provided by the invention, using DBC+DBC, sandwich construction is formed, while optimize loop of power circuit structure, the stray inductance for reducing commutation circuit is offset using mutual inductance, reduces the overvoltage in switching process and vibration.
Description
Technical field
The invention belongs to the encapsulation technology field of power semiconductor modular, more particularly, to a kind of the more of power device
DBC encapsulating structures and method for packing.
Background technology
In power system, electric power affect, data center, electric automobile, the multiple fields such as new energy application, utilize electric power electricity
Sub- equipment realizes that energy conversion is conventional means, basic composition list of the power semiconductor as converters
Member, vital effect is played wherein.With the raising of converters power grade, single power semiconductor device
The discrete device (such as TO247 encapsulation) of part encapsulation can not meet high-power requirement, and simultaneously joint conference makes multiple discrete devices
Into the problems such as parasitic parameter is big, volume is big, radiating is difficult, therefore in high-power applications occasion, it is packaged into by multiple chip parallel connections
Power semiconductor modular receive and be widely applied.
The performance of traditional silicon device has all approached its theoretical limit at many aspects, so as to cause in actual applications very
Difficulty meets power electronic system to power device in blocking voltage, on state current, switching frequency and high temperature, efficient etc.
New demand.In this case, power device of the third generation based on wide bandgap semiconductor arises at the historic moment.As a kind of broad stopband half
Conductor material, not only breakdown field strength is high, heat endurance is good for carborundum, also with carrier saturation drift velocity height, thermal conductivity
The features such as rate is high, it can be used for manufacturing various resistant to elevated temperatures high frequencies, high-efficiency high-power device, be difficult to win applied to traditional silicon device
The occasion appointed.The switching frequency of silicon carbide device can reach megahertz in theory, but the encapsulation knot of existing commercial devices
Structure greatly limit the frequency applications of silicon carbide device, mainly due in encapsulation process substrate, chip, lead interconnection cause
Stray inductance it is bigger, and in general device package module is also by the sub- extraction electrode of power terminal, and these leads are all
The stray inductance in loop can be increased.These stray inductances can make device bear larger peak voltage in turn off process, seriously
When may damage device, it is therefore necessary to try reduce power device module stray inductance.
Around this problem of the stray inductance how reduced in silicon carbide device encapsulating structure, existing encapsulating structure has bonding
Structure, slab construction, mixed structure encapsulating structure.Wherein, bonding structure technique is simple, reliability is high, but the encapsulation of one side
Size is big, and stray inductance is big；Slab construction parasitic parameter is small, thermal diffusivity is good, but complex process, poor reliability；Hybrid package
Structure is by bonding cable architecture, directly covers the combination of copper ceramic substrate (Direct Bonding Copper, DBC) technology, is had
Preceding 2 the advantages of.But existing hybrid package structure still suffer from stray inductance it is larger and do not obtain effectively optimization, bonding area it is small
The problem of causing reliability to reduce, it is therefore necessary to be packaged the optimization of structure and method for packing.
The content of the invention
For the disadvantages described above or Improvement requirement of prior art, the invention provides a kind of more DBC of power device encapsulation
Structure and method for packing, the technology that stray inductance is larger, bonding area is small is thus solved in existing power device packaging structure
Problem.
To achieve the above object, according to one aspect of the present invention, there is provided a kind of more DBC encapsulation knots of power device
Structure, including：Heat-radiating substrate, bottom DBC substrates, the power device being mounted on the bottom DBC substrates, it is welded on the bottom
Upper strata DBC substrates on DBC substrates；
Mounting position of the power device on the bottom DBC substrates is corresponding with the window of the upper strata DBC substrates；
Realized and be electrically connected by wire bonding between the electrode of the power device and the upper strata DBC substrates；The upper strata DBC bases
The copper foil up and down of plate is realized by through hole and is electrically connected；The bottom DBC substrates are realized with the upper strata DBC substrates by solder
Electrical connection.
Preferably, the bottom DBC substrates are divided into the sub- bottom DBC substrates of three identicals, and the heat-radiating substrate is monoblock
Copper base, enhancing radiating；Each sub- bottom DBC substrates are respectively welded on the correspondence position of heat-radiating substrate, each sub- bottom DBC substrates
It is three-decker, wherein, upper strata is that height leads material with lower floor, and intermediate layer is insulation heat-transfer matcrial；Upper surface is divided into
One solder side and the second solder side, and the spacing between the first solder side and the second solder side is more than the maximum functional of power device
Electric insulation distance corresponding to voltage.
Preferably, the upper strata DBC substrates are divided into the sub- upper strata DBC substrates of three identicals, are respectively welded at corresponding son
On bottom DBC substrates, each sub- upper strata DBC substrates are three-decker, wherein, upper strata and lower floor are that height leads material, intermediate layer
For the heat-transfer matcrial that insulate；The circuit structure that upper surface is needed by lithographic method, and the height of heterogeneous networks lead material it
Between spacing be more than electric insulation distance corresponding to power device maximum working voltage；Underlying surfaces are needed by lithographic method
The circuit structure wanted, and the spacing that the height of heterogeneous networks is led between material is more than corresponding to power device maximum working voltage electrically
Insulation distance, realized and be electrically connected by through hole between upper strata and lower floor.
Preferably, the power device include the first MOSFET chips, the 2nd MOSFET chips, the first SBD chips and
2nd SBD chips；
The first MOSFET chips and the 2nd MSOFE chips are composed in parallel by six MOSFET chips respectively, institute
State the first SBD chips and the 2nd SBD chips are composed in parallel by three SBD chips respectively；
The first MOSFET chips the first SBD chips in parallel, form the upper tube of half-bridge circuit；Described second
MOSFET chips the 2nd SBD chips in parallel, form the down tube of half-bridge circuit；Upper tube and down tube half-bridge circuit knot in series
Structure.
Preferably, negative electrode and the upper strata DBC of the drain electrode of the first MOSFET chips and the first SBD chips
The corresponding copper foil of substrate bottom, it is soldered to the first solder side of the bottom DBC substrates；The source of the first MOSFET chips
The anode of pole and the first SBD chips and the corresponding copper foil of the upper strata DBC substrate top layers, are connected by the first bonding line
Connect；The bottom copper foil with the drain electrode connection of the first MOSFET chips and the upper strata DBC bases on the upper strata DBC substrates
The top layer of plate corresponds to copper foil and connected by through hole；
The drain electrode of the 2nd MOSFET chips and negative electrode and the upper strata DBC substrate bases of the 2nd SBD chips
The corresponding copper foil of layer, it is soldered to the second solder side of the bottom DBC substrates；The source electrode of the 2nd MOSFET chips and
The correspondence position of the anode of the 2nd SBD chips and the upper strata DBC substrate top layers, connected by the second bonding line, in institute
State on the DBC substrates of upper strata with the bottom copper foil of the drain electrode connection of the 2nd MOSFET chips and on the upper strata DBC substrates
The top layer copper foil being connected with the source electrode of the first MOSFET chips is connected by through hole.
Preferably, on the upper strata DBC substrates, three power of the different copper foil in three blocks of upper strata as welding encapsulating structure
The position of terminal, the power terminal provide the interface being connected with outside main circuit；The grid of the first described MOSFET and source
Pole, the upper strata that described upper strata DBC substrates are connected to by the first driving bonding line are corresponded on copper foil, and corresponding upper tube driving connects
Device is connect to be welded on the copper foil；The grid and source electrode of the 2nd described MOSFET, it is connected to by the second driving bonding line described
Upper strata DBC substrates corresponding copper foil on, corresponding down tube drive connection device is welded on the copper foil；Drive connection device provide with
The interface of external drive circuit connection.
Preferably, the connected mode between the electrode of drive connection device and MOSFET chips uses Kelvin connections, to subtract
Small common source inductance；Drive connection device, MOSFET grids and source electrode and connection drive connection device and MOSFET grids and source electrode
Part forms driving circuit, MOSFET hourglass source electrodes and the part composition loop of power circuit for connecting its hourglass source electrode；Driving circuit and power
Loop is orthogonal, the coupling reduced between driving circuit and loop of power circuit is played, to reduce loop of power circuit to driving back
The interference on road, enhance the stability of driving.
Preferably, the window size set on the upper strata DBC substrates matches with the size of power device so that processed
Power device can be placed on the bottom DBC substrates from the window in journey, and window number and the number of power device
It is identical.
Preferably, the bottom DBC substrates and the upper strata DBC substrates use the ceramic substrate of double-sided copper-clad, wherein,
Upper strata uses oxygen-free high conductivity type copper with lower floor, and intermediate layer uses one kind in aluminium nitride, aluminum oxide, silicon nitride or beryllium oxide；Institute
The intermediate layers of bottom DBC substrates is stated by heat transfer caused by power device to the bottom heat radiation face of the bottom DBC substrates, and
Realize that the electric component inside encapsulating structure is dielectrically separated to radiator.
Preferably, the bottom DBC substrates are welded on heat-radiating substrate, and heat-radiating substrate is fixed on a heat sink；Radiate base
The size of plate and radiator is determined, it is necessary to ensure reliably to install according to the size of the bottom DBC substrates.
Preferably, the encapsulating structure also includes shell；
The shell is fixed on the heat-radiating substrate, and upper strata DBC substrates and lower floor's DBC substrates electricity can be surrounded completely by having
The floor space of line structure, outer cover height is higher than lead height；Shell is by upper strata DBC substrates, lower floor's DBC substrates and power device
Cover gets up, and plays a part of protection packaging structure；And shell and upper strata DBC substrates, lower floor's DBC substrates and power device it
Between void space, be perfused with insulation protection glue.
It is another aspect of this invention to provide that provide a kind of power device described in based on above-mentioned first aspect any one
More DBC encapsulating structure method for packing, including：
(1) according to power device to be packaged, the bottom DBC substrates and upper strata DBC substrates of design are prepared；The upper strata
Window is provided with DBC substrates；Window number is identical with the number of power device to be packaged, window size and power to be packaged
Device size matches；
(2) upper strata DBC substrates are welded on bottom DBC substrates, and by power device to be packaged from upper strata DBC substrates
Window be welded on bottom DBC substrates, while decoupling capacitance is welded on the DBC substrates of upper strata；
(3) electrode of power device to be packaged and upper strata DBC substrates are electrically connected using lead key closing process；
(4) power terminal is welded on the DBC bases of upper strata；
(5) bottom DBC substrates are welded on heat-radiating substrate, shell is pasted onto on bottom DBC substrates；
(6) insulating silicone gel is injected in shell；Standing solidifies insulating silicone gel.
Preferably, the upper copper of the preparation-obtained bottom DBC substrates of step (1) is etched to two solders side, this
Insulation spacing between two solders side is 1.5mm；The upper strata of the preparation-obtained upper strata DBC substrates of step (1) is etched to
Three solders side, lower copper foil are etched to two solders side, and the insulation spacing between the solder side of same layer is 1.5mm.
Preferably, step (2) specifically includes following sub-step：
(2.1) high-temperature solder of the melt temperature more than 220 degrees Celsius is coated in bottom DBC substrate upper tables by silk-screen printing
The solder side in face；
(2.2) upper strata DBC substrates are mounted according to the position of solder side, and will waits to seal by the window on the DBC substrates of upper strata
The power device of dress is placed on the solder side of bottom DBC upper surface of base plate；
(2.3) power device to be packaged and upper strata DBC substrates are welded on by bottom DBC using the method for vacuum back-flow weldering
On the solder side of substrate.
Preferably, the high-temperature solder used in step (2.1) for tin, silver, copper mixing material, tin, silver, the ratio of copper are
96.5：3：0.5.
Preferably, for the solder used in step (4) for the mixing material of tin, lead, tin, the ratio of lead are 63:37, step
Suddenly for the solder used in (5) for the mixing material of tin, lead, tin, the ratio of bismuth are 42:58.
In general, by the contemplated above technical scheme of the present invention compared with prior art, it can obtain down and show
Beneficial effect：
(1) encapsulating structure of power device provided by the invention, the half-bridge circuit structure being made up of power device, effectively
Reduce the path of loop of power circuit, so as to reduce the stray inductance of loop of power circuit；
(2) encapsulating structure of power device provided by the invention, due to the input of power device half-bridge circuit structure, output
The layout of terminal make it that the conductor on change of current path is in parallel construction, therefore constitutes current direction in switching tube commutation course
Opposite power conductor, the stray inductance for playing a part of reducing switching tube commutation circuit is offset using mutual inductance, thus plays and subtracts
Overvoltage and vibration in low-power device switching process；
(3) encapsulating structure of power device provided by the invention, because drive signal utilizes Kelvin connected modes, play
Effectively reduce the effect of common source inductance；Drive signal line and the perpendicular structure of power line, can make driving circuit and loop of power circuit
Between coupling further reduce, so as to reduce interference of the loop of power circuit to driving circuit, strengthen the stability of driving；
(4) encapsulating structure of power device provided by the invention, the power terminal being welded on the DBC plates of upper strata are mutually flat
OK, play a part of reducing the inductance that the contact resistance that brings of power terminal and power terminal introduce；
(5) encapsulating structure of power device provided by the invention, described encapsulating structure are symmetrical by multiple chips in parallel
It is distributed in three submodules, the chip layout structure in three submodules is identical, efficiently solves multiple chip parallel connections and draws
The problem of commutation circuit parasitic parameter difference risen is big.Secondly, high-frequency decoupling electric capacity is integrated with each submodule, can be with
Further suppress the due to voltage spikes in switching process；
(6) encapsulating structure and method for packing of power device provided by the invention, bottom DBC substrates and upper strata DBC plates
Between welding using welding comprehensively, greatly enhance the reliability of encapsulating structure.
Brief description of the drawings
Fig. 1 is a kind of overall diagram of more DBC encapsulating structures of power device disclosed in the embodiment of the present invention；
Fig. 2 is the structural representation that a kind of encapsulating structure disclosed in the embodiment of the present invention removes after shell；
Fig. 3 is a kind of schematic side view removed after shell of encapsulating structure disclosed in the embodiment of the present invention；
Fig. 4 is a kind of structure of heat dissipation substrate schematic diagram of encapsulating structure disclosed in the embodiment of the present invention；
Fig. 5 is a kind of shell mechanism schematic diagram of encapsulating structure disclosed in the embodiment of the present invention；
Fig. 6 is a kind of bottom DBC board structure schematic diagrames of encapsulating structure disclosed in the embodiment of the present invention；
Fig. 7 is a kind of upper strata DBC plate positive structure schematics of encapsulating structure disclosed in the embodiment of the present invention；
Fig. 8 is a kind of schematic diagram of the upper strata DBC plates Facad structure with through hole of encapsulating structure disclosed in the embodiment of the present invention；
Fig. 9 is a kind of upper strata DBC back structural representations of encapsulating structure disclosed in the embodiment of the present invention；
Figure 10 is a kind of power terminal structural representation of encapsulating structure disclosed in the embodiment of the present invention；
Figure 11 is a kind of drive terminal face structural representation of encapsulating structure disclosed in the embodiment of the present invention；
Figure 12 is a kind of chip position schematic diagram of encapsulating structure disclosed in the embodiment of the present invention；
Figure 13 is a kind of bonding line position view of encapsulating structure disclosed in the embodiment of the present invention；
Figure 14 is a kind of circuit theory diagrams of half-bridge circuit disclosed in the embodiment of the present invention；
Figure 15 is an exemplary plot of a kind of encapsulating structure disclosed in the embodiment of the present invention and external circuit connected mode；
Figure 16 is that a kind of flow of the method for packing of more DBC encapsulating structures of power device disclosed in the embodiment of the present invention is shown
It is intended to.
Embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, it is right below in conjunction with drawings and Examples
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in each embodiment of invention described below
Conflict can is not formed each other to be mutually combined.
Because hybrid package structure needs to form sandwich construction, it is contemplated that radiating, bottom, which uses, directly covers copper ceramic substrate
(Direct Bonding Copper, DBC), and upper strata typically uses pcb board.But the insulating materials of pcb board uses asphalt mixtures modified by epoxy resin
Fat, its dielectric strength is typically in 30kV/mm, but heat dispersion is bad, thus is not suitable for answering using PCB hybrid package structure
Used in high current, high-power, high temperature occasion, and the insulating materials of DBC substrates is usually aluminum oxide or aluminium nitride, although its is exhausted
Edge intensity is both less than epoxy resin, but heat dispersion is better than epoxy resin.Therefore more DBC hybrid package structure is used, suitably
Applied to high current, powerful occasion.Therefore, the present invention proposes more DBC encapsulating structures and the encapsulation of a kind of power device
Method, so as to obtain the high power device packaging structure of a kind of low stray inductance, reliability.
To achieve these goals, scheme of the present invention is by power device, directly to cover copper ceramic substrate
The encapsulation knot of (i.e. DBC plates), lead, heat-radiating substrate, decoupling capacitance, power terminal and drive terminal and shell composition design
Structure；This encapsulating structure forms a half-bridge circuit, specifically includes：Heat-radiating substrate, bottom DBC substrates, it is mounted on bottom DBC bases
Power device on plate, the upper strata DBC substrates being welded on bottom DBC substrates；
Mounting position of the power device on bottom DBC substrates is corresponding with the window of upper strata DBC substrates；The electricity of power device
Realized and be electrically connected by wire bonding between pole and upper strata DBC substrates；The copper foil up and down of upper strata DBC substrates is realized by through hole
Electrical connection；Bottom DBC substrates are realized by solder with upper strata DBC substrates and are electrically connected.
In an optional embodiment, the encapsulating structure goes for silicon carbide power device, silicon-based power device
Part or gallium nitride power device etc., it will not limit in the present invention.
In an optional embodiment, bottom DBC substrates are divided into the sub- bottom DBC substrates of three identicals, and radiate base
Plate is monoblock copper base, and each sub- bottom DBC substrates are respectively welded on the correspondence position of heat-radiating substrate, each sub- bottom DBC substrates
It is three-decker, wherein, upper strata is that height leads material with lower floor, and intermediate layer is insulation heat-transfer matcrial；Upper surface is divided into
One solder side and the second solder side, and the spacing between the first solder side and the second solder side is more than the maximum functional of power device
Electric insulation distance corresponding to voltage；
Upper strata DBC substrates are divided into the sub- upper strata DBC substrates of three identicals, are respectively welded at corresponding sub- bottom DBC substrates
On, each sub- upper strata DBC substrates are three-decker, wherein, upper strata is that height leads material with lower floor, and intermediate layer is insulation heat transfer material
Material；The circuit structure that upper surface is needed by lithographic method, and the spacing that the height of heterogeneous networks is led between material is more than
Electric insulation distance corresponding to power device maximum working voltage；The circuit knot that underlying surfaces are needed by lithographic method
Structure, and the spacing that the height of heterogeneous networks is led between material is more than electric insulation distance corresponding to power device maximum working voltage,
Realized and be electrically connected by through hole between upper strata and lower floor.
Bottom DBC is mounted on by the upper strata DBC substrates that are fixed on bottom DBC substrates, by upper strata DBC substrate windows
The power device and bottom DBC substrates of electrical connection are realized on substrate and between the DBC substrates of upper strata by lead, together structure
Into half-bridge circuit, the path that the commutation circuit of wherein power device is flowed through shortens significantly, meanwhile, electric current in commutation circuit be present
Opposite conductive layer is flowed to, mutual inductance counteracting can be played a part of, thus reduce loop stray inductance.
In an optional embodiment, power device includes the first MOSFET chips, the 2nd MOSFET chips, first
SBD chips and the 2nd SBD chips；
First MOSFET chips and the 2nd MSOFE chips are composed in parallel by six MOSFET chips respectively, the first SBD chips
Composed in parallel respectively by three SBD chips with the 2nd SBD chips；
First MOSFET chips the first SBD chips of parallel connection, form the upper tube of half-bridge circuit；2nd MOSFET chips parallel connection
Two SBD chips, form the down tube of half-bridge circuit；Upper tube and down tube half-bridge circuit structure in series.
In an optional embodiment, the drain electrode of the first MOSFET chips, the negative electrode of the first SBD chips and upper strata
The corresponding copper foil of DBC substrate bottoms, it is soldered to the first solder side of bottom DBC substrates；The source electrode of first MOSFET chips,
The anode of one SBD chips and the correspondence position of upper strata DBC substrate top layers, are connected by the first bonding line；On the DBC substrates of upper strata
It is connected with the bottom copper foil copper foil corresponding with the top layer of upper strata DBC substrates of the drain electrode connection of the first MOSFET chips by through hole；
The corresponding copper foil of the drain electrode of 2nd MOSFET chips, the negative electrode of the 2nd SBD chips and upper strata DBC substrate bottoms, quilt
It is welded to the second solder side of bottom DBC substrates；The source electrode of 2nd MOSFET chips, the anode and upper strata DBC of the 2nd SBD chips
The correspondence position of substrate top layer, connected by the second bonding line, the drain electrode with the 2nd MOSFET chips on the DBC substrates of upper strata connects
The bottom copper foil connect is connected with the top layer copper foil being connected on the DBC substrates of upper strata with the source electrode of the first MOSFET chips by through hole.
Wherein, the layout of the positive and negative electrode of power device and encapsulating structure make it that the conductor on change of current path is in parallel junction
Structure；By taking down tube commutation course as an example, the wire of the positive electrode of encapsulating structure to the first SBD chip negative electrodes, with the first metal-oxide-semiconductor source electrode
It is opposite to the current direction in the wire of AC electrodes；With the current direction in the wire of the first metal-oxide-semiconductor source electrode to AC electrodes, with
Two metal-oxide-semiconductor source electrodes are to the current direction in the wire of negative electrode on the contrary, playing using mutual inductance counteracting to reduce the work of stray inductance
With so as to effectively reduce overvoltage and vibration of the power device in switching process.
In an optional embodiment, the copper foil that three pieces of upper strata is different on the DBC plates of upper strata is as welding encapsulating structure
Three power terminals position；Power terminal provides the interface being connected with outside main circuit.First MOSFET grid and source
Pole, the upper strata that upper strata DBC substrates are connected to by the first driving bonding line are corresponded on copper foil, corresponding upper tube drive connection device weldering
It is connected on the copper foil；2nd MOSFET grid and source electrode, the correspondence of upper strata DBC substrates is connected to by the second driving bonding line
On copper foil, corresponding down tube drive connection device is welded on the copper foil；Drive connection device provides what is be connected with external drive circuit
Interface.
Wherein, the connected mode between the electrode of drive connection device and MOSFET chips uses Kelvin connections, to reduce
Common source inductance；Drive connection device, MOSFET grids and source electrode and connection drive signal terminal and MOSFET grids and source electrode
Part forms driving circuit, MOSFET hourglass source electrodes and the part composition loop of power circuit for connecting its hourglass source electrode；Driving circuit and power
Loop is orthogonal, plays a part of reducing being coupled between driving circuit and loop of power circuit, to reduce loop of power circuit to driving back
The interference on road, enhance the stability of driving.
In an optional embodiment, the window size set on the DBC plates of upper strata matches with the size of power device,
So that power device can be placed on bottom DBC substrates from the window in process, and electricity when needing to consider work
Gas insulation safety；Window number is identical with the number of power device.
In an optional embodiment, bottom DBC substrates and upper strata DBC substrates are using the ceramic base of double-sided copper-clad
Plate, wherein, upper strata uses oxygen-free high conductivity type copper with lower floor, and intermediate layer is used in aluminium nitride, aluminum oxide, silicon nitride or beryllium oxide
It is a kind of；The intermediate layer of bottom DBC substrates by heat transfer caused by power device to the bottom heat radiation face of bottom DBC substrates, and
Realize that the electric component inside encapsulating structure is dielectrically separated to radiator.
In an optional embodiment, bottom DBC substrates are welded on heat-radiating substrate, and heat-radiating substrate can by screw
Fix on a heat sink；The size of heat-radiating substrate and radiator is determined, it is necessary to ensure reliably to pacify according to the size of bottom DBC substrates
Dress.
In an optional embodiment, the encapsulating structure also includes shell；
Shell is fixed on heat-radiating substrate, and upper strata DBC substrates and lower floor DBC substrate circuit structures can be surrounded completely by having
Floor space, outer cover height is higher than lead height；Shell gets up upper strata DBC substrates, lower floor's DBC substrates and power device cover,
Play a part of protection packaging structure；And the sky between shell and upper strata DBC substrates, lower floor's DBC substrates and power device
Gap space, it is perfused with insulation protection glue.
Wherein, upper surface of outer cover is provided with hole, and for injecting insulating gels, hole diameter is 3mm~5mm.
In conjunction with the drawings and specific embodiments, the present invention is further described.In embodiments of the present invention, identical mark
Number be used for represent identical element.
Below in conjunction with the accompanying drawings and embodiment the present invention is further illustrated.Shown in Fig. 1-3, encapsulation provided by the invention
Structure includes：Heat-radiating substrate 1, shell 2, encapsulation and the circuit structure in housing, circuit structure include power terminal 92, drive end
Son 91, bottom DBC substrates 3, upper strata DBC substrates 4, MOSFET chips 71, diode 72, the bonding line 5 for power connection, use
Bonding line 6, decoupling capacitance 8 in drive connection.Wherein power terminal includes three positive power terminals, 923, three negative power ends
Sub 921, three AC power terminals 922；Drive terminal includes upper tube drive terminal (911,912,913), down tube drive terminal
(914、915、916)；Bottom DBC substrates 3 include (301,302,303), upper strata DBC plates 4 include (401,402,403),
MOSFET chips have upper tube (71-1,71-2,71-3,71-4,71-5,71-6), down tube (71-7,71-8,71-9,71-10,71-
11st, 71-12), SBD chips have upper tube (72-1,72-2,72-3), down tube (72-4,72-5,72-6).Heat-radiating substrate 1 passes through spiral shell
Silk can be fixed on a heat sink；Shell 2 is used for protection packaging structure and filling Silica hydrogel；Bottom DBC substrates (301,302,
303) by being reflow soldered on heat-radiating substrate 1, upper strata DBC plates are welded with bottom DBC substrates (301,302,303)
(401,402,403), MOSFET chips (71-1,71-2,71-3,71-4,71-5,71-6,71-7,71-8,71-9,71-10,
71-11,71-12) and SBD chips (72-1,72-2,72-3,72-4,72-5,72-6), using aluminum steel by MOSFET chips, SBD
Chip (72-1,72-2,72-3,72-4,72-5,72-6) and upper strata DBC plates (401,402,403) connect；Power terminal
With drive terminal by reflow soldering on upper strata DBC surface.
Heat-radiating substrate 1 of the present invention, as shown in figure 4, wherein 101 be screw hole, for connecting radiator；102 are
Surface depth 1mm grain, it is therefore an objective to be used to align when welding bottom DBC.
Shell 2 of the present invention, as shown in figure 5, and bonded together by fluid sealant and heat-radiating substrate 1, the shell
Hole 202 on the front of body, the extraction for power terminal；Hole 201 on the front of the housing, the extraction for drive terminal；
There is a diameter of 4mm hole 203 in the front of the housing, for injecting Silica hydrogel；Embedding has glass transition temperature to surpass in the housing 2
200 degree of Silica hydrogel is crossed, the height of the Silica hydrogel of embedding is so that the leaded submergence of institute to be defined.
Fig. 6 is the hardened compositions of bottom DBC of the encapsulating structure of the present invention.As shown in fig. 6, described DBC substrates are divided into three
Block identical DBC substrates (301,302,303), DBC substrates are three-decker, and levels are oxygen-free high conductivity type copper paper tinsel, intermediate layer
For aluminium nitride or alumina ceramic layer, heat caused by power chip is passed to module bottom heat-radiating substrate by the ceramic layer, and is carried
For the insulation inside package module to heat-radiating substrate；Upper copper 301-1,301-2 of the ceramic substrate 301 is etched to accordingly
Shape, it is possible to provide bonding power chip and the position being connected with upper strata DBC plates 4；Wherein copper foil 301-1 and copper foil 301-2 it
Between clearance distance be 1.5mm, it is possible to provide effective insulation distance；The lower copper foil of described DBC substrates can be used as and radiate
The connected contact surface of substrate.
Fig. 7 is the positive structure schematic of DBC plates in upper strata of the present invention, and Fig. 8 is DBC plates in upper strata of the present invention
Schematic diagram of the Facad structure with through hole, Fig. 9 is the structure schematic diagram of DBC plates in upper strata of the present invention.Described is upper
Lower copper foil 401-6,401-7 of layer DBC plates (401,402,403) has the upper copper with bottom DBC (301,302,303)
301-1,301-2 have same shape, are connected bottom DBC and upper strata DBC by welding；It has hole on DBC plates at the middle and upper levels
401-1, chip can be placed in one, be welded on bottom DBC；There are upper copper 401-2,401-3,401- on the DBC plates of upper strata
4th, 401-5, lower copper foil 401-6,401-7；There are corresponding through hole 401-8,401-9 inside the intermediate layer of upper strata DBC plates, its
Middle 401-8 connects the upper copper 401-3 of upper strata DBC plates and lower copper foil 401-7, forms together in half-bridge circuit
AC, 401-9 connect the upper copper 401-4 of upper strata DBC plates and lower copper foil 401-6, form half-bridge circuit together
In DC+；In addition, upper copper 401-5 provides the DC- of half-bridge circuit, 401-2 is used for drive terminal and drives the company of bonding line
Connect.Upper copper 401-3 can also be used to weld AC terminal, and for connecting the source electrode of upper bridge arm MOSFET in half-bridge structure；On
Layer copper foil 401-4 can also be used to weld DC plus ends；Upper copper 401-5 can also be used to weld DC negative terminals, and for connecting
Lower bridge arm MOSFET source electrode in half-bridge structure.
Figure 10 is power terminal structural representation of the present invention, and Figure 11 is that drive terminal structure of the present invention is shown
It is intended to.Wherein power terminal includes DC+ power terminals 922, DC- power terminals 921, AC power terminals 923, and each terminal has
Hole as shown in 921-1, for being connected with external circuit.Drive terminal is busbar as shown in figure 11, by bottom conductive
911-2, the plastic casing 911-3 of fixation, contact pin 911-2；The upper copper that wherein 911-2 passes through solder and upper strata DBC
401-2 is connected, then is connected by contact pin 911-2 with external drive.
Figure 12 is chip position schematic diagram of the present invention, and Figure 13 is bonding line and decoupling capacitance position of the present invention
Put schematic diagram.Chip of the present invention is individually placed in three little modules, is illustrated exemplified by one of them, chip 71-1,71-
2nd, 72-1 is individually positioned in upper strata DBC similar 401-1 hole, and bottom DBC upper copper 301- is welded to by solder
1；71-7,71-8,72-4 are individually positioned in upper strata DBC similar 401-1 hole, and are welded to the upper of bottom DBC by solder
Layer copper foil 301-2.The position of bonding line is identical inside three little modules, is illustrated exemplified by one of them, bonding line is divided into power
Bonding line (501,502,503,504,505,506) and driving bonding line (601,602,603,604), wherein bonding line 501,
502nd, 505 be the bonding line in upper tube, and the upper copper 401-4 of the source electrode of chip and upper strata DBC is connected；Bonding line
503rd, 504,506 be the bonding line in down tube, and the upper copper 401-5 of the source electrode of chip and upper strata DBC is connected；Bonding
Line 601,602 is the bonding line in upper tube, and the upper copper 401-2 of the grid of chip, source electrode and upper strata DBC is connected.
Half-bridge circuit is formed by these chips, bonding line and DBC copper foil and terminal.In addition, the also integrated decoupling capacitance (51) of the design,
As shown in figure 13, the decoupling capacitance is connected across between upper strata DBC upper copper 401-4,401-5, can reduce mistake during shut-off
Voltage.As shown in figure 12, the drive signal line of MOSFET chips uses Kelvin connected modes, drive signal line 501,502,
503rd, 504 and power line 601,602,603,604 perpendicular structures.The connected mode of signal wire shown in Figure 12 greatly reduces
The stray inductance of driving circuit, avoids common source inductance and is disturbed to caused by driving circuit；Other signal wire and power line
Vertical stratification greatly reduces the coupling of driving circuit and loop of power circuit, further reduces common source inductance.
Figure 14 is half-bridge circuit schematic diagram of the present invention.Described half-bridge circuit structure is by upper and lower bridge arm and each
Antiparallel diode composition.Upper bridge arm is by 6 in parallel group of MOSFET chips (71-1,71-2,71-3,71-4,71-5,71-6)
Into, and 3 SBD chips (72-1,72-2,72-3) in parallel；Lower bridge arm by 6 MOSFET chips (71-7,71-8,71-9,
71-10,71-20,71-30) compose in parallel, and 3 SBD chips (72-4,72-5,72-6) in parallel.
According to the layout type of the encapsulating structure of the present invention, in half-bridge circuit, the conductor length of switching tube commutation circuit
Greatly reduce, while in commutation course, power lead has the opposite structure of current direction, takes full advantage of mutual inductance and offsets skill
Art further reduces stray inductance.
Figure 15 is an exemplary plot of the encapsulating structure with external circuit connected mode of the present invention.Described encapsulating structure
In, D is power model, and D is welded on radiator A, ensures radiating；C is driving plate, and module D drive terminal is connected to driving
On plate C；B is DC bus capacitor plate, and module D is connected by the hole in capacitor board B with the L-type copper foil on electric hot plate B.
Figure 16 is a kind of flow chart of method for packing provided by the invention.
As shown in figure 16, method for packing provided by the invention, specifically includes following steps.
Step S101：According to power device to be packaged, the bottom DBC substrates and upper strata DBC substrates of design are prepared；Upper strata
Window is provided with DBC substrates；Window number is identical with the number of power device to be packaged, window size and power to be packaged
Device size matches；
Wherein, aluminium nitride (AlN) material of insulating barrier selection with high thermal conductivity of upper strata DBC substrates, aluminium nitride
Thermal coefficient of expansion and carborundum it is close, by punching, electroplating, etching the structure formed as Figure 6-9.
Bottom DBC substrates and the particulate matter of upper strata DBC plate surfaces are removed using the method for ultrasonic wave cleaning and Chemical cleaning
Matter and ionic impurity.
Wherein, the upper copper of the preparation-obtained bottom DBC substrates of step S101 is etched to two big solders side,
Insulation spacing between the two solders side is 1.5mm；, the upper strata of the preparation-obtained upper strata DBC substrates of step S101 is carved
Lose for three big solders side, lower copper foil is etched to two big solders side, between the insulation between the solder side of same layer
Away from for 1.5mm.
Step S102：The print solder paste in the front copper foil of bottom DBC substrates, upper strata DBC substrates are welded on bottom DBC
On substrate, and the window of power device to be packaged from upper strata DBC substrates is welded on bottom DBC substrates, while decouples electricity
Appearance is welded on the DBC substrates of upper strata；
Wherein, from the Sn96.5/Ag3.0/Cu0.5 tin creams that fusing point is 220 degrees Celsius, tin cream is printed to by steel mesh silk
Copper foil surface on bottom DBC；Power device and upper strata DBC plates to be packaged is welded on bottom by vacuum high-temperature solder reflow techniques
On layer DBC plates, specifically, step S102 includes following sub-step：
S102.1：High-temperature solder of the melt temperature more than 220 degrees Celsius is coated on bottom DBC substrates by silk-screen printing
The solder side on surface；
S102.2：Upper strata DBC substrates are mounted according to the position of solder side, and will be treated by the window on the DBC substrates of upper strata
The power device of encapsulation is placed on the solder side of bottom DBC upper surface of base plate；
S102.3：Power device to be packaged and upper strata DBC substrates are welded on bottom by the method welded using vacuum back-flow
On the solder side of DBC substrates.
Wherein, the high-temperature solder used in step S102.1 for tin, silver, copper mixing material, tin, silver, the ratio of copper
For 96.5:3:0.5；The operating temperature of encapsulating structure can be improved using high-temperature solder, improves stability；Facilitate the encapsulation simultaneously
Solder of the structure in application is chosen；Melt temperature can be used Celsius less than 200 when being welded in encapsulating structure
The solder of degree.
Step S103：The electrode of power device to be packaged and upper strata DBC substrates are carried out by electricity using lead key closing process
Gas connects；
Wherein, one end of lead is connected to the upper surface electrode of power device to be packaged by bonding technology, will be drawn
The other end of line is connected to by bonding technology on the copper foil of upper strata DBC plates, when it is implemented, the quantity and thickness of lead can be with
According to the area of power device electrode to be packaged and chosen by the size of electric current, be not specifically limited herein.
Step S104：Power terminal and drive connection device are welded to the copper foil of upper strata DBC substrates by the tool of design
On；
Wherein, in step S104, from the Pb37/Sn63 tin creams that fusing point is 183 degrees Celsius, tin is printed on terminal
Cream, terminal is welded on the DBC of upper strata by vacuum high-temperature solder reflow techniques.
Wherein, in step S104, for the solder used for the mixing material of tin, lead, tin, the ratio of lead are 63:37；
The high-temperature solder used in the solder and step S102.1 of use will ensure enough temperature differences.
Step S105：The print solder paste on heat-radiating substrate, bottom DBC substrates are welded on heat-radiating substrate, shell is glued
It is attached on bottom DBC substrates；
Wherein, from the Sn42/Bi58 tin creams that fusing point is 138 degrees Celsius, the surface of steel mesh silk-screen to heat-radiating substrate is passed through；
Bottom DBC substrates are welded on heat-radiating substrate by vacuum high-temperature solder reflow techniques；Then shell is installed, fill Silica hydrogel.Will
In insulating silicone gel injection shell；Standing solidifies insulating silicone gel.Shell is bonded on heat-radiating substrate by sealant, shell
Size be defined so that internal structure can be completely covered；Silica hydrogel is circulated into shell by dotting glue method, and it is small that 24 are stood after embedding
When, wait Silica hydrogel solidification.
Wherein, for the solder used in step S105 for the mixing material of tin, lead, tin, the ratio of bismuth are 42:58；
The high-temperature solder used in the solder and step S102.1 of use will ensure enough temperature differences.
In an optional embodiment, the solder in S102, S104 and S105 ensures that sufficient temp is poor, it is possible to
The encapsulation is completed, while fusion temperature can not exceed the minimum fusion temperature of each material.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, all any modification, equivalent and improvement made within the spirit and principles of the invention etc., all should be included
Within protection scope of the present invention.
Claims (10)
- A kind of 1. more DBC encapsulating structures of power device, it is characterised in that including：Heat-radiating substrate, bottom DBC substrates, it is mounted on Power device on the bottom DBC substrates, the upper strata DBC substrates being welded on the bottom DBC substrates；Mounting position of the power device on the bottom DBC substrates is corresponding with the window of the upper strata DBC substrates；It is described Realized and be electrically connected by wire bonding between the electrode of power device and the upper strata DBC substrates；The upper strata DBC substrates Upper and lower copper foil is realized by through hole to be electrically connected；The bottom DBC substrates are realized electric with the upper strata DBC substrates by solder Connection.
- 2. encapsulating structure according to claim 1, it is characterised in that the bottom DBC substrates are divided into three identical Bottom DBC substrates；The heat-radiating substrate is monoblock copper base, enhancing radiating；Each sub- bottom DBC substrates are respectively welded at radiating base On the correspondence position of plate, each sub- bottom DBC substrates are three-decker, wherein, upper strata and lower floor are that height leads material, intermediate layer For the heat-transfer matcrial that insulate；Upper surface is divided into the first solder side and the second solder side, and the first solder side and the second solder side it Between spacing be more than power device maximum working voltage corresponding to electric insulation distance；The upper strata DBC substrates are divided into the sub- upper strata DBC substrates of three identicals, are respectively welded at corresponding sub- bottom DBC substrates On, each sub- upper strata DBC substrates are three-decker, wherein, upper strata is that height leads material with lower floor, and intermediate layer is insulation heat transfer material Material；The circuit structure that upper surface is needed by lithographic method, and the spacing that the height of heterogeneous networks is led between material is more than Electric insulation distance corresponding to power device maximum working voltage；The circuit knot that underlying surfaces are needed by lithographic method Structure, and the spacing that the height of heterogeneous networks is led between material is more than electric insulation distance corresponding to power device maximum working voltage； Realized and be electrically connected by through hole between upper strata and lower floor.
- 3. encapsulating structure according to claim 1 or 2, it is characterised in that the power device includes the first MOSFET cores Piece, the 2nd MOSFET chips, the first SBD chips and the 2nd SBD chips；The first MOSFET chips and the 2nd MSOFE chips are composed in parallel by six MOSFET chips respectively, and described One SBD chips and the 2nd SBD chips are composed in parallel by three SBD chips respectively；The first MOSFET chips the first SBD chips in parallel, form the upper tube of half-bridge circuit；The 2nd MOSFET cores Piece the 2nd SBD chips in parallel, form the down tube of half-bridge circuit；Upper tube and down tube half-bridge circuit structure in series.
- 4. encapsulating structure according to claim 3, it is characterised in that the drain electrode of the first MOSFET chips and described The corresponding copper foil of the negative electrode of first SBD chips and the upper strata DBC substrate bottoms, it is soldered to the of the bottom DBC substrates One solder side；The source electrode of the first MOSFET chips and the anode of the first SBD chips and the upper strata DBC substrates top The corresponding copper foil of layer, connected by the first bonding line；On the upper strata DBC substrates with the drain electrode of the first MOSFET chips The bottom copper foil of connection copper foil corresponding with the top layer of the upper strata DBC substrates is connected by through hole.The drain electrode of the 2nd MOSFET chips and the negative electrode of the 2nd SBD chips and the upper strata DBC substrate bottoms Corresponding copper foil, it is soldered to the second solder side of the bottom DBC substrates；The source electrode of the 2nd MOSFET chips and described The correspondence position of the anode of 2nd SBD chips and the upper strata DBC substrate top layers, connected by the second bonding line；On described Layer DBC substrates on the 2nd MOSFET chips drain electrode connection bottom copper foil with the upper strata DBC substrates with institute The top layer copper foil for stating the source electrode connection of the first MOSFET chips is connected by through hole.
- 5. encapsulating structure according to claim 4, it is characterised in that on the upper strata DBC substrates, three pieces of upper strata difference Position of the copper foil as welding three power terminals of encapsulating structure, the power terminal provides connecing of being connected with external circuit Mouthful；The grid and source electrode of first MOSFET, the upper strata pair of the upper strata DBC substrates is connected to by the first driving bonding line Answer on copper foil, corresponding upper tube drive connection device is welded on the copper foil；The grid and source electrode of 2nd MOSFET, pass through Two driving bonding lines are connected on the corresponding copper foil of the upper strata DBC substrates, and corresponding down tube drive connection device is welded on the copper On paper tinsel；Drive connection device provides the interface being connected with external drive circuit；Connected mode between drive connection device and MOSFET chips uses Kelvin connections, to reduce common source inductance；Driving connects Connect device, MOSFET grids and source electrode and connect drive connection device and form drive with the bonding line and copper foil of MOSFET grids and source electrode Dynamic loop, MOSFET hourglass source electrodes and the part composition loop of power circuit for connecting its hourglass source electrode；Driving circuit hangs down mutually with loop of power circuit Directly, play a part of reducing the coupling between driving circuit and loop of power circuit, to reduce interference of the loop of power circuit to driving circuit, Enhance the stability of driving.
- 6. encapsulating structure according to claim 3, it is characterised in that the bottom DBC substrates and the upper strata DBC substrates The ceramic substrate of double-sided copper-clad is used, wherein, upper strata uses oxygen-free high conductivity type copper with lower floor, and intermediate layer is using aluminium nitride, oxygen Change one kind in aluminium, silicon nitride or beryllium oxide；Heat transfer caused by power device is arrived in the intermediate layer of the bottom DBC substrates The bottom heat radiation face of the bottom DBC substrates, and realize that the electric component inside encapsulating structure is dielectrically separated to radiator.
- 7. encapsulating structure according to claim 3, it is characterised in that the encapsulating structure also includes shell；The shell is fixed on the heat-radiating substrate, and upper strata DBC substrates and lower floor DBC substrate circuit knots can be surrounded completely by having The floor space of structure, outer cover height is higher than lead height；Shell plays upper strata DBC substrates, lower floor's DBC substrates and power device cover Come, play a part of protection packaging structure；And between shell and upper strata DBC substrates, lower floor's DBC substrates and power device Void space, it is perfused with insulation protection glue.
- A kind of 8. encapsulation side of more DBC encapsulating structures of power device based on described in any one of the claims 1 to 7 Method, it is characterised in that including：(1) according to power device to be packaged, the bottom DBC substrates and upper strata DBC substrates of design are prepared；The upper strata DBC bases Window is provided with plate, window number is identical with the number of power device to be packaged, window size and power device to be packaged Size matches；(2) upper strata DBC substrates are welded on bottom DBC substrates, and the window by power device to be packaged from upper strata DBC substrates Mouth is welded on bottom DBC substrates, while decoupling capacitance is welded on the DBC substrates of upper strata；(3) electrode of power device to be packaged and upper strata DBC substrates are electrically connected using lead key closing process；(4) power terminal and drive connection device are welded on the DBC substrates of upper strata；(5) bottom DBC substrates are welded on heat-radiating substrate, and shell is pasted onto on bottom DBC substrates；(6) insulating silicone gel is injected in shell；Standing solidifies insulating silicone gel.
- 9. method for packing according to claim 8, it is characterised in that the preparation-obtained bottom DBC substrates of step (1) Upper copper is etched to two solders side, and the insulation spacing between the two solders side is 1.5mm；Step (1) is prepared to be obtained To the upper stratas of upper strata DBC substrates be etched to three solders side, lower copper foil is etched to two solders side, the weldering of same layer Insulation spacing between junction is 1.5mm.
- 10. method for packing according to claim 9, it is characterised in that step (2) specifically includes following sub-step：(2.1) high-temperature solder of the melt temperature more than 220 degrees Celsius is coated in bottom DBC upper surface of base plate by silk-screen printing Solder side；(2.2) upper strata DBC substrates are mounted according to the position of solder side, and will be to be packaged by the window on the DBC substrates of upper strata Power device is placed on the solder side of bottom DBC upper surface of base plate；(2.3) power device to be packaged and upper strata DBC substrates are welded on by bottom DBC substrates using the method for vacuum back-flow weldering Solder side on.
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| CN113163578B (en) * | 2021-03-10 | 2023-03-31 | 重庆大学 | Ultra-low parasitic inductance pulse forming single module packaging structure and stacked packaging structure |
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