CN112434400A

CN112434400A - MOSFET grid source voltage interference conduction path model

Info

Publication number: CN112434400A
Application number: CN202011101993.3A
Authority: CN
Inventors: 邵天骢; 郑琼林; 李志君; 李虹; 黄波; 邱志东; 张志朋; 王作兴; 王佳信
Original assignee: Beijing Jiaotong University; Global Power Technology Co Ltd
Current assignee: Beijing Jiaotong University; Global Power Technology Co Ltd
Priority date: 2020-10-15
Filing date: 2020-10-15
Publication date: 2021-03-02
Anticipated expiration: 2040-10-15
Also published as: CN112434400B

Abstract

The invention provides a MOSFET grid-source voltage interference conduction path model which comprises a double-loop transfer function for describing an interference conduction process of pulse voltage and pulse current and a characteristic equation for describing a standard second-order system of the interference conduction path. The interference conduction path model can comprehensively consider the influence of pulse voltage and pulse current on the gate-source voltage interference of the MOSFET and is used for visually and rapidly judging the driving parameters of the MOSFET, the packaging structure of the MOSFET and the rationality of PCB layout design in a power conversion system.

Description

MOSFET grid source voltage interference conduction path model

Technical Field

The invention relates to a MOSFET grid-source voltage interference conduction path model.

Background

Generally, the operating voltage (about kV level) of the SiC MOSFET is much higher than the operating current (about a level), so the impulse voltage is the main interference source of the gate-source voltage interference, and although numerically, the mathematical analysis considering the impulse voltage interference has better accuracy within the error tolerance range, the interference of the impulse current will not be negligible under the premise of studying the package difference and the interference of the driving resistance to the gate-source voltage. The interference of the pulse current to the gate-source voltage can be roughly classified into two types: the first type is that distributed voltage interference is induced in a driving loop through the change of a space electromagnetic field, and the distributed voltage interference belongs to radiation interference; and in the second category, the stray inductance of the device is coupled to a grid source electrode to form interference, and the interference belongs to conducted interference. To suppress the first type of radiated interference, power engineers typically design PCBs for suppression, and common techniques include: the area of a driving loop is minimized, and the superposition of a driving part and a power part rich in interference sources is avoided; at present, the method has more perfect theoretical basis and engineering experience. However, the second category of conducted interference lacks theoretical guidance and engineering design schemes of the system in the field of power electronics.

In the second type of conduction interference, the drastic changes of drain-source voltage and current are conducted through the Miller capacitor, so that the gate-source voltage is subjected to spike and oscillation, the stability of the gate-source voltage is influenced, the loss of a converter can be increased, even the direct connection of a bridge arm and the breakdown of a gate electrolyte are caused, and the performance improvement and the safe and reliable application of the MOSFET are seriously threatened. With the progress of material technology, power MOSFETs generated by using wide bandgap semiconductor materials such as SiC and GaN have the advantages of high withstand voltage and high switching speed, however, the change rate of drain-source voltage and current is also increased by the advantage, so that the problem of conduction interference is prominent, and the problem of MOSFET gate-source voltage interference suppression is receiving wide attention.

To suppress gate-source voltage interference, the mechanism of generation should be understood first. Therefore, scholars at home and abroad adopt the idea of mathematical modeling to deeply discuss the gate-source voltage interference mechanism. In the aspect of simple mechanism model analysis, the key limiting factors for determining the switching speed are focused on by the model analysis, and the result shows that for a wide-bandgap device, two main factors for limiting the switching speed of the wide-bandgap device in a bridge arm structure are the problems of grid driving capability and grid-source voltage interference, and then the maximum change value of the grid-source voltage caused by the interference is estimated according to the voltage change rate, the driving resistance and a junction capacitance equivalent circuit; for example, references [1], [2] and [3 ].

The characterization of a 10kV SiC MOSFET in switching transients is detailed in reference [4], indicating that in a conduction transient, a forward spike of gate-source voltage interference will likely generate a breakdown current, and due to the presence of this breakdown current, the conduction current and conduction losses are increased; in the off-transient, the negative spike of gate-source voltage disturbance will cause device performance degradation when the allowable range is exceeded. On this basis, the disturbance of the gate-source voltage and the limitation of the switching speed are discussed, and in the extreme case, i.e. assuming that all the current through the miller capacitance of the device charges its gate-source capacitance, the maximum gate-source voltage variation amplitude is estimated by the junction capacitance equivalent circuit. The simple mechanism models explain the essential reason of the gate-source voltage interference, and provide conceptual basis for improving a gate driver, eliminating the interference and improving the switching speed; however, key stray parameters affecting the dynamic characteristics of the SiC MOSFET, such as gate internal resistance, drive loop inductance, power loop inductance, etc., have not been considered, and the gate-source voltage interference mechanism is not complete.

In the aspect of complex mechanism model analysis:

reference [5] proposes to establish a circuit analysis model of a continuous device, and studies the phenomenon of misconduction caused by gate-source voltage interference of a high-voltage enhanced GaN transistor under a bridge arm structure: firstly, establishing a nonlinear I-V and C-V characteristic device model considering a high-voltage enhancement type GaN transistor; then, combining the device characteristics with various circuit parameters to establish a circuit level model; finally, comparing the segmental switching process model with the PSpice simulation, proving that the model obtains a more accurate analysis result;

reference [6] is a bridge arm circuit based on a GaN device, considers all circuit parasitic parameters, analyzes and establishes a mathematical model, comprehensively and quantitatively analyzes the misconduction phenomenon caused by gate-source voltage interference, provides accurate reference for device selection, PCB design and debugging of the GaN-based converter in engineering practice, and can be used for evaluating and judging the occurrence of the misconduction problem;

reference [7] is directed to stray parameters of a common bridge arm structure circuit in engineering practice, and a gate-source voltage interference analysis model is researched and provided based on an MOSFET equivalent junction capacitance model, Thevenin theorem and a superposition principle and considering the influences of reverse recovery of a MOSFET body diode, nonlinearity of drain-source voltage change and inductance of a driving loop, and is explicitly and correspondingly expressed by the stray parameters of a converter;

in reference [8], a junction capacitance equivalent circuit of a wide bandgap device is introduced, the influence of a driving loop inductance and a power loop inductance is considered, and a six-order model for gate-source voltage interference mechanism analysis is established;

in summary, the complex mechanism models consider various circuit spurious parameters, and can calculate and obtain voltage spike values caused by crosstalk. However, these complex mechanism models only consider voltage spikes caused by interference, and lack explanation of interference oscillation; moreover, in the modeling process, too many non-dominant spurious parameters are introduced. Therefore, by utilizing the complex mechanism models, the design guiding principle of considering the grid pressure stress is difficult to be given by directly facing the engineering application; the method for reducing the gate voltage stress of the SiC MOSFET is not completely integrated into the design of a high-power current conversion system. Therefore, it is a challenging task to maximize the performance advantages of the SiC MOSFET device while ensuring the safety and stability of the power conversion system using the SiC MOSFET device.

Therefore, the invention provides a MOSFET grid-source voltage interference conduction path model mainly aiming at conduction interference caused by pulse voltage and pulse current in a bridge arm circuit, which is used for predicting and judging the influence of the pulse voltage and the pulse current on the MOSFET grid-source voltage interference and disclosing an interference conduction mechanism.

The references are as follows:

[1]ZHANG Z,ZHANG W,WANG F,et al.Analysis of the Switching Speed Limitation of Wide Band-Gap Devices in a Phase-Leg Configuration:2012 IEEE Energy Conversion Congress and Exposition(ECCE)[C].Raleigh,USA:15-20 Sep.2012.

[2]CHEN Z.Characterization and Modeling of High-Switching-Speed Behavior of SiC Active Devices[D].Virginia Polytechnic Institute,2009.

[3]NGUYEN B,ZHANG X,FERENCZ A,et al.Analytic model for power MOSFET turn-off switching loss under the effect of significant current diversion at fast switching events:2018 IEEE Applied Power Electronics Conference and Exposition(APEC)[C].

[4]JI S,ZHENG S,WANG F,et al.Temperature-Dependent Characterization,Modeling,and Switching Speed-Limitation Analysis of Third-Generation 10-kV SiC MOSFET[J].IEEE Transactions on Power Electronics,2018,33(5):4317-4327.

[5]XIE R,WANG H,TANG G,et al.An Analytical Model for False Turn-On Evaluation of High-Voltage Enhancement-Mode GaN Transistor in Bridge-Leg Configuration[J].IEEE Transactions on Power Electronics,2017,32(8):6416-6433.

[6]ZHU T,ZHUO F,ZHAO F,et al.Quantitative Model-Based False Turn-on Evaluation and Suppression for Cascode GaN Devices in Half-Bridge Applications[J].IEEE Transactions on Power Electronics,2019,34(10):10166-10179.

[7]LI R,ZHU Q,XIE M.A New Analytical Model for Predicting dv/dt-Induced Low-Side MOSFET False Turn-ON in Synchronous Buck Converters[J].IEEE Transactions on Power Electronics,2019,34(6):5500-5512.

[8]CHEN J,LUO Q,HUANG J,et al.Analysis and Design of an RC Snubber Circuit to Suppress False Triggering Oscillation for GaN Devices in Half-Bridge Circuits[J].IEEE Transactions on Power Electronics,2020,35(3):2690-2704.

disclosure of Invention

The invention aims to solve the technical problem of providing a MOSFET grid-source voltage interference conduction path model for revealing a grid-source voltage interference mechanism which occurs when a MOSFET is switched on and off at a high speed in a high-frequency high-power converter.

The implementation mode of the invention is as follows: a MOSFET gate-source voltage disturb conduction path model, the disturb conduction path comprising: a pulse voltage interference conduction path and a pulse current interference conduction path; the model specifically comprises: the pulsed voltage and the pulsed current interfere with the double loop transfer function of the conduction process.

Further, the dual loop transfer function includes a drive loop transfer function and a power loop transfer function.

Further, the interference conduction path model is in a matrix form:

in the formula, v_GS(s) represents the combined interference voltage conducted to the MOSFET gate-source voltage, G_o(s) represents the impulse voltage interference power loop transfer function, H_o(s) represents the transfer function of the impulse current disturbance power loop, G_i(s) represents the impulse voltage disturbance drive loop transfer function, H_i(s) represents the transfer function of the impulse current disturbance drive loop, v_dis(s) represents a pulse voltage disturbance, i_dis(s) represents the pulse current disturbance, said s being a complex parameter.

Further, it is characterized byThe transfer function H of the pulse current interference power loop_o(s), the expression of which is as follows:

H_o(s)＝L_css

in the formula, L_csIs the common source inductance of the MOSFET.

Further, the pulse current interferes with the transfer function H of the driving loop_i(s), the expression of which is as follows:

wherein R represents an external driving resistor, R_gRepresenting the internal resistance of the MOSFET gate, C_issRepresenting the MOSFET input capacitance, C_aShowing an external gate-source parallel auxiliary capacitor, L_iDenotes the sum of the inductances of the drive circuits, D(s) ═ s³RC_aL_iC_iss+s²(RR_gC_aC_iss+L_iC_iss)+s(R_gC_iss+RC_iss+RC_a)+1。

Further, the impulse voltage disturbs the power loop transfer function G_o(s), the expression of which is as follows:

in the formula: l is_oRepresents the sum of stray inductances, R, of the power loop_oRepresenting the sum of the distributed resistances, C, of the power circuit_ossIs the MOSFET output capacitance.

Further, the pulse voltage disturbs the transfer function G of the driving loop_i(s), the expression of which is as follows:

wherein R represents an external driving resistor, R_gRepresenting the internal resistance of the MOSFET gate, C_issRepresenting MOSFET inputsCapacitance, C_aShowing an external gate-source parallel auxiliary capacitor, L_iDenotes the sum of the inductances of the drive circuits, D(s) ═ s³RC_aL_iC_iss+s²(RR_gC_aC_iss+L_iC_iss)+s(R_gC_iss+RC_iss+RC_a)+1。

Further, the characteristic equation of the standard second-order system of the interference conduction path is as follows:

s²(RR_gC_aC_iss+L_iC_iss)+s(R_gC_iss+RC_iss+RC_a)+1＝0

wherein R represents an external driving resistor, R_gRepresenting the internal resistance of the MOSFET gate, C_issRepresenting the MOSFET input capacitance, C_aShowing an external gate-source parallel auxiliary capacitor, L_iRepresenting the drive loop inductance sum.

The invention has the following advantages: the mathematical model can reveal a loop coupling mechanism of pulse voltage and pulse current which cause SiC MOSFET grid-source voltage interference through packaging stray parameters, is convenient for intuitively and quickly judging the rationality of system element parameters, greatly simplifies calculation, and can be used for predicting a dynamic process and an oscillation condition after the grid-source voltage is interfered. Meanwhile, the model has concise mathematical characteristics and visual physical significance.

Drawings

The invention will be further described with reference to the following examples with reference to the accompanying drawings.

FIG. 1 is a block diagram of a MOSFET gate-source voltage interference conduction path model transfer function of the present invention;

FIG. 2 is a schematic diagram of a bridge arm circuit structure considering impulse current interference in the present invention;

FIG. 3 is a waveform timing diagram of the present invention considering that a pulsed current interference source causes MOSFET gate-source voltage interference;

FIG. 4 is a simplified diagram of the bridge arm circuit of the present invention;

FIG. 5 is an equivalent circuit diagram of gate-source voltage disturber of the present invention;

FIG. 6 is a schematic diagram of a model prediction result of a gate-source voltage interference negative spike varying with MOSFET packaging obtained by using the model of the present invention;

FIG. 7 is a schematic diagram of the results of an actual measurement experiment using the model of the present invention to obtain negative peak of gate-source voltage interference as a function of MOSFET package.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

The contents of the present invention are described below with reference to the accompanying drawings.

Fig. 1 is a transfer function block diagram of a MOSFET gate-source voltage interference conduction path model according to the present invention. As shown in fig. 1, the model includes the following:

(1) both pulsed voltage and pulsed current interference conduction paths are described.

(2) The model includes a dual loop transfer function that describes the impulse voltage and impulse current interference conduction process.

(3) The dual loop transfer function includes a drive loop transfer function and a power loop transfer function.

(4) The interference conduction path model is in a matrix form:

in the formula, v_GS(s) represents the combined interference voltage, i, conducted to the MOSFET gate-source voltage_dis(s) represents a pulsed current disturbance, H_o(s) represents the transfer function of the impulse current interference power loop, H_i(s) represents a pulsed current disturbance drive loop transfer function; v. of_dis(s) represents a pulse voltage disturbance, G_o(s) represents the impulse voltage interference power loopRoad transfer function, G_i(s) represents a pulse voltage disturbance drive loop transfer function, wherein s is a complex parameter variable; v. of_GSDenotes the drive signal.

(5) The characteristic equation of the interference conduction path standard second-order system is as follows:

s²(RR_gC_aC_iss+L_iC_iss)+s(R_gC_iss+RC_iss+RC_a)+1＝0

(6) The transfer function H of the pulse current interference power loop_o(s), the expression of which is as follows:

H_o(s)＝L_css

in the formula, L_csIs the common source inductance of the MOSFET.

(7) The pulse current interference drive loop transfer function H_i(s), the expression of which is as follows:

(8) The transfer function G of the impulse voltage interference power loop_o(s), the expression of which is as follows:

(9) The pulse voltage interference drive loop transfer function G_i(s), the expression of which is as follows:

FIG. 2 is a bridge arm circuit structure considering impulse current interference according to an embodiment of the present invention, as shown in FIG. 2, the bridge arm structure loads current I_LThe positive direction flows out from the middle point of the bridge arm and returns to the middle point of the direct current bus. Because the upper tube Q of the bridge arm_HAnd a lower tube Q_LIn the present embodiment, only the lower tube Q is referred to_LSo that the lower tube Q_LShown in the form of a transient equivalent circuit. The junction capacitances are respectively C_gs、C_gd、C_ds(ii) a Gate internal resistance of R_gRepresents; the package lead inductors are respectively provided with L_g、L_d、L_sAnd (4) showing. i.e. i_dFor the current flowing through the channel (or anti-parallel diode) of the SiCMOSFET, the difference between the channel and the anti-parallel diode is ignored for ease of analysis in the embodiments of the present invention. Q_HAnd Q_LThe upper and lower switch tubes are respectively in complementary conduction and leave dead time to prevent the bridge arms from being directly connected. In order to prevent gate-source voltage interference, an auxiliary capacitor C is connected in parallel between the gate and the source_a. Conduction of driving signalBias voltage of V_CCOff bias voltage of V_EE. PWM signal S of upper and lower tubes_HAnd S_LA drive signal v input from and output from the drive chip via the drive chip (including an isolation circuit)_GSAnd charging and discharging a gate-source input capacitor of the SiMOSFET through a driving resistor R.

Fig. 3 shows a waveform diagram of a pulsed current disturb gate-source voltage. To highlight the main contradiction, the interference cause of the grid source voltage of the passive tube is analyzed emphatically, and the analysis process is approximately considered as C_gs、C_dsInvariable, C_gdIs piecewise linearized, ignoring the parasitic body diode D_dsThe reverse recovery effect of (a), as shown in fig. 3:

from t₀At the beginning of the moment, the tube Q is put on_HStarts to rise, resulting in v_DSStart to fall, Q_HInterference Q_LGate source voltage v_GSThe procedure of (2) is as follows.

Mode 1[ t ]₀,t₁]：t₀At the beginning of the time, lower tube Q_LOf the drain-source voltage v_DSFrom V_DCIs reduced to 0. At this stage, Q_LOf the gate-source voltage v_GSDisturbance by drain-source voltage v_DSReduced off-bias voltage V_EEA further decrease is started. v. of_DSDown to a certain extent when Q_LThe mode ends when the parasitic body diode of (1) satisfies the conduction condition.

Mode 2[ t ]₁,t₂]：t₁Time, Q_LThe parasitic body diode of (1) conducts current, drain current i_DRises to I in the reverse direction_LThe top tube current gradually commutates to the bottom tube. At this stage, v_DSWill excite Q_LGate source voltage v_GSGenerating high frequency oscillation, the oscillation lasting for t₂Time, Q_LGate source voltage v_GSReturn to off bias voltage V_EE. At this stage, the gate-source voltage v caused by the disturbance of the current_GSSuperimposed on v caused by voltage disturbances_GSAbove the interference oscillations, negative interference spikes are generated together.

Mode 3[ t ]₂,t₃]: q is thus still within the dead time of the upper and lower tubes_LGate source voltage v_GSIs kept at a negative turn-off bias voltage V_EEUnchanged until lower tube Q_LPWM signal S of_LChanging from low to high. Drain-source voltage v_DSKept near 0V (conduction voltage drop) and reverse drain current i_DConstant is I_L。

Mode 4[ t ]₃,t₄]：t₃At time, lower tube Q_LPWM signal S of_LChanging from low to high. The driving voltage is lower tube Q through a driving resistor_LInput capacitance C_issCharging, gate source voltage v_GSSwitching off the bias voltage V from the negative direction_EEUp to a forward on bias voltage V_CCAbove threshold voltage, Q_LHas a low impedance and the load current flows through the channel of the MOSFET.

Mode 5[ t ]₄,t₅]: lower tube Q_LOf the gate-source voltage v_GSIs maintained at a forward conduction bias voltage V_CC，Q_LWill continue to flow load current.

Mode 6[ t ]₅,t₆]：t₅At time, lower tube Q_LPWM signal S of_LChanging from high to low. The driving voltage is lower tube Q through a driving resistor_LInput capacitance C_issDischarge, gate-source voltage v_GSBias voltage V from forward conduction_CCBegins to fall below the threshold voltage, Q_LHas a high resistance to current flow through Q_LParasitic body diode of (1), drain-source voltage v_DSKept near 0V (conduction voltage drop) and reverse drain current i_DConstant is I_L. When v is_GSReducing to a negative turn-off bias voltage V_EE. Thereafter, the upper tube Q_HPWM signal S of_HChange from low to high, Q_HWhen the gate-source voltage rises to the threshold value, Q_HBegins to rise in channel current, reverse drain current i_DThe fall is started and the modality ends.

Mode 7[ t ]₆,t₇]: reverse drain current i_DFrom I_LDown to 0 and load current from Q_LThe parasitic diode gradually commutates to Q_H，v_DSKept around 0V (conduction voltage drop). At this stage, Q_LOf the gate-source voltage v_GSDisturbance by drain current i_DIs caused by a reverse drop from the off-bias voltage V_EEFurther increase was started. Reverse drain current i_DAt the moment of falling to 0, the modality ends.

Mode 8[ t ]₇,t₈]：t₇Time, Q_LOf the drain-source voltage v_DSIncrease from 0 to V_DC. At this stage, the drain-source voltage v_DSV due to the rise of_GSDisturbance superimposed on the drain current i_DV caused by a reverse descent of_GSOn disturbance, v_GSContinues to move away from the turn-off bias voltage V_EEFurther increase was started. v. of_DSIncrease to V_DCThe modality ends.

Mode 9[ t ]₈,t₉]：t₈Time, Q_LDrain-source voltage v_DSIs raised to V_DC. At this stage, v_DSWill excite Q_LGate source voltage v_GSGenerating high frequency oscillation, the oscillation lasting for t₉Time, Q_LGate source voltage v_GSReturn to negative turn-off bias voltage V_EE. A new steady state process is entered until the next cycle begins.

Fig. 4 is a simplified diagram of a bridge arm circuit according to an embodiment of the present invention, and as shown in fig. 4, a high-frequency impulse interference source of a power circuit is caused by the switching action of the switch SW, and is approximately considered as the superposition of impulse current interference and impulse voltage interference according to the superposition principle. As shown in FIG. 4, in a typical 3-pin packaged SiC MOSFET, the source stray inductance L_sThe inductor is not only the inductor of the power source, but also a part of the inductor of the power loop; the stray inductance of the driving source is part of the inductance of the driving loop. Thus, in a 3-pin packaged SiC MOSFET, the common source inductance L_csIs equal in value to the source inductance L_s. As can be seen from fig. 4, of the power circuitThe high-frequency pulse interference source passes through a common source inductor L_csA drive loop coupled to the gate-source electrode for generating a gate-source voltage v_GSAnd (4) interference.

FIG. 5 is an equivalent circuit of gate-source voltage disturbance according to an embodiment of the present invention, as shown in FIG. 5, for the input junction capacitance C of the SiC MOSFET_iss＝C_gs+C_gdPower loop inductance L_oComprises MOS pin and lead inductor (L)_d、L_s) And stray inductance L_σ(the circuit consisting of the DC decoupling capacitor and the bridge arm), therefore, L_o＝L_σ+L_d+L_s。R_oIncluding all equivalent resistances of the power loop, including PCB lead resistance, MOSFET on-resistance. Drive loop inductance L_iIncluding parasitic inductance L of gate pin_gAnd a drive loop inductance L on the source pin_s，L_i＝L_g+L_s，v_csIs the voltage drop over the common source inductance. According to the equivalent circuit of the gate-source voltage interference of the embodiment of the invention, the following can be obtained by derivation: transfer function H of pulse current interference power loop_o(s) pulse current disturbance drive loop transfer function H_i(s) pulse voltage interference power loop transfer function G_o(s) pulse voltage disturbance drive loop transfer function G_i(s)。

FIG. 6 is a schematic diagram of a model prediction result of the variation of the gate-source voltage interference negative spike with the main parameters of the MOSFET package, obtained by using the model of the present invention. In this embodiment, a typical voltage current value V is taken in consideration of the case where the gate-source voltage and the pulse current disturbance are commonly applied to the gate-source voltage to generate the disturbance_DC＝800V、I_L3A and for simplicity the ramping time of the pulsed voltage and pulsed current disturbances are both taken to be 40nS, ignoring the dc bias component V_EEThe change component of the negative spike is analyzed with emphasis. According to the model of the gate-source voltage interference provided by the invention, the parameter R is measured in a typical SiC MOSFET_g＝5.7Ω、C_iss＝1816pF、C_rss＝24pF、L_i＝30nH、C_aSubstituting the above model transfer function expression under the condition of 2nF and 10 ΩCalculating v under interference excitation_GSRamp signal response c (t), as shown in FIG. 6, at time 0, the pulse voltage begins to fall and the pulse current begins to rise in the negative direction, corresponding to t of mode 1 in FIG. 3₀The time of day. The gate-source voltage is increased along with the negative direction, and when the time reaches 40nS, the slope interference voltage current reaches a steady-state value, the gate-source voltage has a negative peak, which corresponds to t of the mode 1 in the figure 3₂The time of day. As can be seen from the waveforms shown in fig. 6, as the common source inductance Lcs decreases, the loop coupling strength decreases, and the negative spike occurring in the gate-source voltage also decreases. The model calculation result of the gate-source voltage interference shows that by reducing the loop coupling strength, the gate-source voltage can be interfered by the pulse interference source through the common source inductor Lcs. By improving the SiC MOSFET packaging structure, the coupling strength of the driving circuit and the power circuit is reduced, so that the gate-source voltage interference component introduced by high-frequency pulse current can be reduced, and the gate-source voltage interference peak is relieved to a certain extent. Therefore, for a specific SiC MOSFET, the time domain response of the grid-source voltage response to the high-frequency switching interference can be predicted by substituting the transient characteristic parameters provided by a data manual and the specific values of the parameters corresponding to the parameters in practical application into the model of the invention.

As shown in fig. 7, the gate-source voltage disturbs the measured experimental results of the negative spike as a function of MOSFET package. Setting the DC bus voltage V_DCThe gate-source voltages of SiC MOSFETs of different coupling strengths were experimentally compared under the same test conditions, 800V. The grid source voltage of the SiC MOSFET with the strong coupling loop and the weak coupling loop is subjected to a negative interference peak value, the strong coupling loop is larger than the weak coupling loop by a certain amount, and the difference is obvious. Under the condition of strong coupling of a loop, the Lcs value is larger, and the grid-source voltage waveform is superposed with more obvious pulse current interference, so that the interference intensity is larger, and the peak of the negative increase of the grid-source voltage of the 3 pins is about 3V higher than that of the 4 pins; under the condition of weak loop coupling, the gate of the SiC MOSFET is decoupled from the power loop, so that the Lcs value is small and the interference of pulse current is small, and the negative peak value of the gate-source voltage interference is small. By improving the packaging structure, the power loop and the driving loop are decoupled, and the pulse current interference can be reduced through the common source inductance interference gridThe source voltage reduces the negative interference voltage peak to a certain extent, and relieves the grid voltage stress.

Comparing the results of fig. 6 and 7, it can be found that the model prediction result of fig. 6 and the experimental test result of fig. 7 are within the error tolerance. Therefore, the influence of pulse voltage interference and pulse current interference on the grid-source voltage can be effectively predicted by adopting the model disclosed by the invention. The model comprehensively considers the influence of pulse voltage and pulse current on MOSFET grid-source voltage interference, and is used for intuitively and quickly judging the MOSFET driving parameters, the MOSFET packaging structure and the rationality of PCB layout design in a power conversion system.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although specific embodiments of the invention have been described above, it will be understood by those skilled in the art that the specific embodiments described are illustrative only and are not limiting upon the scope of the invention, and that equivalent modifications and variations can be made by those skilled in the art without departing from the spirit of the invention, which is to be limited only by the appended claims.

Claims

1. A MOSFET gate-source voltage disturb conduction path model, comprising: the interfering conductive path comprises: a pulse voltage interference conduction path and a pulse current interference conduction path; the model specifically comprises: the pulsed voltage and the pulsed current interfere with the double loop transfer function of the conduction process.

2. The MOSFET gate-source voltage disturb conduction path model of claim 1, wherein: the dual loop transfer function includes a drive loop transfer function and a power loop transfer function.

3. The MOSFET gate-source voltage disturb conduction path model of claim 1, wherein: the interference conduction path model is in a matrix form:

4. A MOSFET gate-source voltage disturb conduction path model according to claim 3, wherein: the transfer function H of the pulse current interference power loop_o(s), the expression of which is as follows:

H_o(s)＝L_css

in the formula, L_csIs the common source inductance of the MOSFET.

5. A MOSFET gate-source voltage disturb conduction path model according to claim 3, wherein: the pulse current interference drive loop transfer function H_i(s), the expression of which is as follows:

6. A MOSFET gate-source voltage disturb conduction path model according to claim 3, wherein: the transfer function G of the impulse voltage interference power loop_o(s), the expression of which is as follows:

7. A MOSFET gate-source voltage disturb conduction path model according to claim 3, wherein: the pulse voltage interference drive loop transfer function G_i(s), the expression of which is as follows:

wherein R represents an external driving resistor, R_gRepresenting the internal resistance of the MOSFET gate, C_issRepresenting the MOSFET input capacitance, C_aShowing an external gate-source parallel auxiliary capacitor, L_iRepresents the sum of the inductances of the drive loops, D: (s)＝s³RC_aL_iC_iss+s²(RR_gC_aC_iss+L_iC_iss)+s(R_gC_iss+RC_iss+RC_a)+1。

8. The MOSFET gate-source voltage disturb conduction path model of claim 1, wherein: the characteristic equation of the standard second-order system of the interference conduction path is as follows:

s²(RR_gC_aC_iss+L_iC_iss)+s(R_gC_iss+RC_iss+RC_a)+1＝0