CN113163578B - Ultra-low parasitic inductance pulse forming single module packaging structure and stacked packaging structure - Google Patents
Ultra-low parasitic inductance pulse forming single module packaging structure and stacked packaging structure Download PDFInfo
- Publication number
- CN113163578B CN113163578B CN202110262198.0A CN202110262198A CN113163578B CN 113163578 B CN113163578 B CN 113163578B CN 202110262198 A CN202110262198 A CN 202110262198A CN 113163578 B CN113163578 B CN 113163578B
- Authority
- CN
- China
- Prior art keywords
- pcb
- parasitic inductance
- low parasitic
- single module
- packaging structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a single module packaging structure and a stacked packaging structure formed by extremely low parasitic inductance pulse. The extremely low parasitic inductance pulse forming single module packaging structure comprises an upper PCB and a lower PCB. The stacked packaging structure of the single module packaging structure formed by the extremely low parasitic inductance pulse comprises n single module packaging structures formed by the extremely low parasitic inductance pulse; the invention provides a single-module 3D bus structure for a Marx generator and a 3D bus stacking structure based on a 3D bus and mutual inductance cancellation principle, and the parasitic inductance of a power loop of the Marx generator can be further reduced.
Description
Technical Field
The invention relates to the field of pulse, in particular to a single module packaging structure and a stacked packaging structure formed by extremely low parasitic inductance pulse.
Background
SiC MOSFETs have been widely used in pulse generator development due to their excellent dynamic characteristics, and Marx generators using SiC MOSFETs have the advantages of modularity, flexible regulation, and economical reliability.
In the Marx generator based on the SiC MOSFET, the high switching speed of the SiC MOSFET directly promotes the dynamic level of the Marx generator, but the advantages of the Marx generator are limited by a current loop and parasitic inductance, so that not only can switch misoperation be caused, but also electromagnetic interference on a driving circuit can be caused, but also the overshoot voltage in the switching-off transition process can be directly caused, and further the service life of the SiC MOSFET is shortened, so that the switch is failed. Therefore, controlling the SiC MOSFET power current loop and parasitic inductance is of great importance to Marx pulse generators using SiC MOSFETs.
In the application of a high-power integrated converter, the power module-3D laminated bus of a hybrid packaging structure is realized by changing the layout and the stacking sequence of semiconductor devices. The structure enables the module to have the advantages of low parasitic inductance, voltage overshoot suppression, electromagnetic interference suppression and switching loss reduction through a mutual inductance cancellation principle, and achieves that the parasitic inductance of a single module is less than 1.7nH and the voltage overshoot is reduced by about 55% in a 5.5kW single-phase inverter. The prior art proposes to use low inductance PCB packaging to meet the requirements of nanosecond pulsers for fast voltage rise and fall times. However, the bare chip is directly welded with the PCB, so that the process difficulty and the production cost are increased, and a module superposition solution is not provided.
Disclosure of Invention
The invention aims to provide a pulse forming single module packaging structure with extremely low parasitic inductance, which comprises an upper PCB and a lower PCB.
The top layer of the upper PCB is a grid drive circuit arrangement layer;
the bottom layer of the upper PCB, the top layer of the lower PCB and the bottom layer of the lower PCB are power loop arrangement layers;
the upper PCB and the lower PCB are connected through a MOSFET (metal oxide semiconductor field effect transistor) M1;
the upper PCB top layer and the upper PCB bottom layer are not directly electrically connected, and the lower PCB top layer and the lower PCB bottom layer are connected through a via hole.
Recording one end of the top layer of the PCB as an A end and the other end as a B end; one end of the top layer of the lower PCB board is an A 'end, and the other end of the top layer of the lower PCB board is a B' end;
a' of the bottom layer of the lower PCB is connected with the anode of the diode D, and the end A of the top layer of the lower PCB is connected with the cathode of the diode D.
The end B of the top layer of the lower PCB is connected with the end B' of the bottom layer of the lower PCB through a via hole.
The bottom layer of the upper PCB is connected with the top layer of the lower PCB in a direct welding mode;
and the top layer of the upper PCB is provided with a gate drive circuit, a switch gate and a switch Kelvin source electrode.
The top layer of the lower PCB is provided with a switch drain electrode circuit, a switch source electrode circuit and a grounding pin;
and the bottom layer of the lower PCB is connected with two ends of the energy storage capacitor.
The current forms mutual inductance counteracting loops with opposite directions between the upper PCB and the lower PCB.
A gap between the bottom layer of the upper PCB and the top layer of the lower PCB is filled with a conductive medium; the bottom layer of the upper PCB is electrically connected with the top layer of the lower PCB.
And forming a stacked packaging structure of the single module packaging structure based on the extremely low parasitic inductance pulse, wherein the stacked packaging structure comprises n extremely low parasitic inductance pulses to form the single module packaging structure. n is more than or equal to 2.n is a positive integer.
The ith-1 st extremely low parasitic inductance pulse forms a single module packaging structure, and the ith extremely low parasitic inductance pulse forms a single module packaging structure which is connected through a connecting column. i =1,2, \8230;, n.
The lower PCB of the 1 st extremely low parasitic inductance pulse forming single module packaging structure is sequentially connected with a load R and the upper PCB of the nth extremely low parasitic inductance pulse forming single module packaging structure.
The 1 st extremely low parasitic inductance pulse forms the lower PCB board of the single module packaging structure to receive the external direct current and form a charging current loop.
After the 1 st extremely low parasitic inductance pulse forms the single module packaging structure and is charged, the charging diode D is used for charging d1 Discharging to the 2 nd extremely low parasitic inductance pulse forming single module package structure.
After the jth ultra-low parasitic inductance pulse forms the single module packaging structure, the charging is finished through a charging diode D dj And discharging to the jth extremely low parasitic inductance pulse to form a single module packaging structure. j =2,3, \8230;, n.
The nth very low parasitic inductance pulse forms the upper PCB ground of the single module package structure.
The number of charging diodes is n-1.
The technical effects of the invention are undoubted, the driving circuit and the power circuit are isolated in an economic, simple and effective mode through the 3D bus structure design, the parasitic inductance of the pulse power circuit is smaller than 4nH through the mutual inductance cancellation principle, the front edge of the output pulse voltage is further reduced, the current front edge is accelerated by about 2.3 times, the overshoot of the switching voltage is reduced by 80%, the driving voltage is effectively restrained, the pulse characteristic of the Marx generator is improved, and the stability and the reliability of the system are improved.
The invention relates to an economic and effective Marx single module and stacking structure design scheme based on a three-dimensional laminated bus structure. Firstly, a single-module 3D bus structure design is provided by discussing a Marx single-module parasitic inductance influence rule, and then a module stacking structure design scheme is provided and experimental verification is carried out.
The 3D bus structure provided by the invention can improve the rising and falling speed of the output voltage, and simultaneously improve the pulse current response rate, and the speed can be improved by nearly 2.3 times.
The invention can reduce the overshoot of the switch voltage by 4.77 times (80%), reduce the risk of switch misconduction and improve the dynamic characteristic and stability of the generator.
The invention provides a single-module 3D bus structure for a Marx generator and a 3D bus stacking structure based on a 3D bus and mutual inductance cancellation principle, and the parasitic inductance of a power loop of the Marx generator can be further reduced.
Drawings
FIG. 1 is a very low parasitic inductance pulse forming single module package structure;
FIG. 2 is a stacked package structure forming a single module package structure based on the very low parasitic inductance pulse;
FIG. 3 is a circuit diagram of a single very low parasitic inductance pulse applied in a stacked package configuration;
fig. 4 is a comparison of the overshoot of the switching voltage turn-off process.
FIG. 5 is a stacked package structure circuit topology for forming a single module package structure based on the very low parasitic inductance pulse;
FIG. 6 shows the current flow and intensity for a multi-module stack;
FIG. 7 (a) is a 3D bus Marx single-module object diagram; fig. 7 (b) is a physical diagram of a 3D bus 4-level Marx stacking module (gate driving part); fig. 7 (c) is a real object diagram of a 3D bus 4-level Marx stacking module (power bus part);
FIG. 8 is a load voltage comparison; FIG. 8 (a) is an expanded view of the pulse voltage rising process; FIG. 8 (b) is a development view of a pulse voltage drop process;
FIG. 9 is a comparison of load current waveforms;
FIG. 10 is a comparison of drain-source voltages of high-potential output stage switches; fig. 10 (a) shows the drain-source voltage during the turn-on process of the switch of a certain stage after the modules are stacked; after the modules in fig. 10 (b) are stacked, the drain-source voltage is in the process of switching off the switch of a certain stage;
fig. 11 shows a comparison of the driving signals of the high-potential output stage.
In the figure: the circuit comprises a gate drive circuit 2, a through hole 3, a switch drain circuit 4, a switch source circuit 5, an energy storage capacitor 6, a switch Kelvin source 7 and a switch gate 8.
Detailed Description
The present invention is further illustrated by the following examples, but it should not be construed that the scope of the above-described subject matter is limited to the following examples. Various substitutions and alterations can be made without departing from the technical idea of the invention and the scope of the invention is covered by the present invention according to the common technical knowledge and the conventional means in the field.
Example 1:
referring to fig. 1 and 3, the very low parasitic inductance pulse forms a single module package structure including an upper PCB and a lower PCB.
The top layer of the upper PCB is a grid drive circuit arrangement layer;
the bottom layer of the upper PCB, the top layer of the lower PCB and the bottom layer of the lower PCB are power loop arrangement layers;
the upper PCB and the lower PCB are connected through a MOSFET (metal oxide semiconductor field effect transistor) M1; the MOSFET tube is a SiC tube.
The top layer of the upper PCB is not directly electrically connected with the bottom layer of the upper PCB, and the designated areas of the top layer of the lower PCB and the bottom layer of the lower PCB are connected through the via hole 3. The designated area is the B end of the top layer of the lower PCB and the B' end of the bottom layer of the lower PCB.
The bottom layer of the upper PCB is connected with the top layer of the lower PCB in a direct welding mode;
the top layer of the upper PCB is arranged with a gate drive circuit 2, a switching gate 8 and a switching kelvin source 7.
The top layer of the lower PCB is provided with a switch drain electrode circuit 4, a switch source electrode circuit 5 and a grounding pin;
the bottom layer of the lower PCB is connected with two ends of the energy storage capacitor 6.
The current forms mutual inductance counteracting loops with opposite directions between the upper PCB and the lower PCB.
And a gap between the bottom layer of the upper PCB and the top layer of the lower PCB is filled with a conductive medium (soldering tin and the like) and has reliable electrical connection.
Recording one end of the top layer of the PCB as an A end and the other end as a B end; one end of the top layer of the lower PCB board is an A 'end, and the other end of the top layer of the lower PCB board is a B' end;
the A' of the bottom layer of the lower PCB is connected with the anode of the diode D, and the A end of the top layer of the lower PCB is connected with the cathode of the diode D.
Example 2:
the ultra-low parasitic inductance pulse forms a single module packaging structure, the structure is formed by combining an upper PCB and a lower PCB with double thicknesses, and a Top layer of the upper PCB is a power loop arrangement layer. The Bottom layer of the upper PCB and the Top layer of the lower PCB are directly connected and are divided into two parts through the SiCSMOSFET, the two parts are respectively connected with a drain stage and a source stage, and the Bottom layer of the lower PCB is respectively connected with two poles of an energy storage capacitor.
Due to the fact that the multi-layer structure is used, discharging current is connected to the switch drain electrode from the energy storage capacitor through the hole, and after the switch is conducted, the discharging current is applied to two ends of a load through the switch source electrode. The green arrows in fig. 2 point to the direction of the discharge current of the power loop, and due to the 3D multi-layer layout, the current forms mutual inductance cancellation loops with opposite directions between the upper layer and the lower layer of the PCB, and the PCB is an FR4 substrate with a thickness of 1.6mm, compared with the conventional space stacking, due to the proximity of the loop distance, the mutual inductance cancellation effect is further enhanced, and finally the parasitic inductance of the main loop is greatly reduced.
Table 13 d structure parasitic parameter extraction data nH
And (4) carrying out PCB drawing by combining the design scheme, extracting parasitic parameters of the drawn PCB by using AnsysQ3D, wherein the extraction rule is the same as the requirement of the second section, and obtaining the parameters shown in the table 4. It can be found that due to the design of the mutual inductance cancellation loop, large negative mutual inductances exist in L2 and L4, L3 and L4 which are adjacent to each other and have opposite current directions, so that the loop equivalent inductance of the power bus circuit adopting the 3D multilayer structure is only 3.9nH. Therefore, the proposed structure has excellent pulse output characteristics. Especially in the aspect of the switching overshoot, the switching drain-source voltage turn-off overshoot of a 3D bus shown in FIG. 4 is smaller than that of the A plate and the B plate, and the overshoot peak value is reduced to 100V from 340V, and the overshoot peak value is reduced by 70%.
Example 3:
referring to fig. 2 and 5, a stacked package structure of a single module package structure is formed based on the extremely low parasitic inductance pulse, and includes n extremely low parasitic inductance pulses to form the single module package structure. n is more than or equal to 2.n is a positive integer.
The ith-1 st extremely low parasitic inductance pulse forms a single module packaging structure, and the ith extremely low parasitic inductance pulse forms a single module packaging structure which is connected through a connecting column. i =1,2, \8230;, n.
The lower PCB of the single module packaging structure formed by the 1 st extremely low parasitic inductance pulse is sequentially connected with a load R and the upper PCB of the single module packaging structure formed by the nth extremely low parasitic inductance pulse.
The 1 st extremely low parasitic inductance pulse forms a lower PCB of the single module packaging structure to receive external direct current and form a charging current loop.
After the 1 st extremely low parasitic inductance pulse forms the single module packaging structure and is charged, the charging diode D is used for charging d1 Discharging to the 2 nd extremely low parasitic inductance pulse forming single module package structure.
After the jth ultra-low parasitic inductance pulse forms the single module packaging structure, the charging is finished through a charging diode D dj And discharging to the jth extremely low parasitic inductance pulse to form a single module packaging structure. j =2,3, \8230;, n.
The nth very low parasitic inductance pulse forms the upper PCB ground of the single module package structure.
The number of charging diodes is n-1.
The circuit structure of the single module packaging structure formed by single extremely low parasitic inductance pulse is shown in fig. 3, wherein L1-L4 are inductances generated by the arrangement of a PCB board, and a capacitor C is an energy storage capacitor 6.
The module superposition is a direct mode for realizing high-voltage output of the pulse generator, and the core of the Marx topology is parallel charging and serial discharging of capacitors, so that the design of a multi-module laminated structure is the premise of ensuring that the 3D structure provided by the text has practicability. Fig. 7 shows that the 4-level Marx3D single modules are stacked and connected up and down through connecting columns. Unlike the conventional Marx stacking, only the power circuit is stacked, and the board layer where the driving circuit of each module is located is an independent PCB layer (as shown in fig. 1), so that the bus circuit and the driving circuit of the structure provided herein are arranged in upper and lower layers 3D, and the influence of the strong pulse transient strong field on the driving circuit can be avoided to the greatest extent in physical space.
The structure provided by the embodiment can not only improve the stability of the driving circuit, but also improve the laminated structure of the power circuit. Fig. 5 is a multi-module stacked circuit topology with the green arrows showing the current direction when the generators are discharged in series. In the foregoing, due to the design of the single-module upper and lower PCB laminated 3D structure, not only the mutual inductance cancellation loop is formed in the discharging process due to the opposite current directions, but also the mutual inductance cancellation loop can be formed between the single modules in the laminated structure, so that the parasitic inductance of the line can be further reduced in the overall structure, and the quality of the output pulse can be improved.
Example 4:
the experiments for forming single module package structures and stacked package structures based on the extremely low parasitic inductance pulse were verified as follows:
fig. 6 is the result of Maxwell simulation of surface current density vectors and surface current density intensities performed on the proposed structure. Fig. 6 shows the counter current flow for a single module bus current in the direction of mutual inductance cancellation, and the counter current flow for a stacked module power loop current in a stacked configuration also in the direction of mutual inductance cancellation. And the driving loop and the power loop are arranged in a vertically-stacked 3D structure, the current density intensity in FIG. 6 also shows that when the current density of the power loop reaches 560A/m, the current density of the driving loop is only 100A/m. Therefore, the provided laminated structure can effectively reduce the mutual inductance between layers, and can further reduce the space interference of the transient large current mutation magnetic field of the power loop on the drive loop through the space layout, thereby further improving the stability of the generator.
It should be noted that fig. 6 shows that the connecting column is an output portion for realizing multi-module pulse superposition, and therefore, the connecting column is a place where pulse power is converged and directly acts near the main loop. The current density intensity profile results of fig. 6 also indicate that the connecting column region is an intensity concentrated region where transient magnetic fields are radiated to the accessory drive loop region due to power superposition, so care should be taken away from the connecting column region in the drive loop arrangement to further reduce the impact of transient high-voltage fields on the drive loop.
The embodiment establishes a 4-level (900 Veach) 3D structure Marx superposition experimental platform. The CREEC3M0065100J SiC MOSFET was used and the voltage measurement probe was PPE5kV (LeCry 400 MHz), the current probe was 6600 (Pearson 120 MHz), and the voltage probe measured in a group spring to further reduce the measurement loop inductance. The test conditions were a DC charging voltage of 950V, a 50 Ω load, and a pulse current of 90A (a limit pulse current condition of C3M 0065100J).
Fig. 7 is a design circuit, and (a) of fig. 7 is the proposed 3D bus bar single module, in which a MOSFET driving part and a power part are stacked up and down by a kelvin connection manner. And a Marx pulse forming loop is arranged on a power part to form a mutual inductance cancellation power current loop shown in figure 1, so that the parasitic inductance of the power loop is further reduced. Fig. 7 (b) and 7 (c) are stacked structures of the proposed 4-stage 3D bus module, where fig. 10 (b) is embodied as an independent driving loop unit, and driving loop interlayer independence is achieved through signal optical isolation and power supply isolation. Fig. 7 (c) is a power loop 3D arrangement and pulse superposition is achieved directly on the power side. The physical distance of the power loop is reduced, the line inductance is reduced, and the 3D stacking design realizes the mutual inductance cancellation reduction of the parasitic inductance further when the directions of power current layers are opposite.
Fig. 8 and 9 show the waveforms of the load voltage and current, respectively, and it can be firstly found intuitively that the 3D board has better dynamic characteristics than the conventional AB board (both gate drivers adopt kelvin connection), and has faster edge time on the waveforms of the voltage and the current. Fig. 11 is an expanded view of the front and back edges of the load voltage, when the output voltage amplitude reaches 3.6kV, it is seen that the rise and fall times of the AB plate are 7.8ns and 7.3ns, respectively, and the rise and fall times of the 3D plate are 5.3ns and 5.9ns, respectively, both reduced by about 2ns.
While in the load current of fig. 9, the 3D advantage is more evident. The current rise time is reduced from the original 22.6ns for the AB plate to 9.6ns for the 3D plate, and the fall time is reduced from the original 24.0ns for the AB plate to 10.3ns for the 3D plate. It can be found that the rising speed of the current of the original pulse generator can be improved by 2.35 times and the falling speed can be improved by 2.33 times through the design of the 3D bus single module and the superposition structure.
From the foregoing analysis, it is known that the Marx stack structure has a more severe transient strong field distribution near the power bus, and the driving circuit and the switch in the high-voltage output stage (far from the ground point) are subjected to stronger electromagnetic interference. Therefore, the switching drain-source voltage and the driving signal of the high-voltage output stage in the 4-stage AB plate Marx structure and the 3D bus Marx structure are compared. Fig. 10 is a switch drain-source voltage spread, which first of all exhibits more severe oscillations in the switch dynamics due to the larger parasitic inductance of the AB-plate structure compared to the 3D structure, which directly results in faster turn-on and turn-off times of the switch drain-source voltage. It must be noted that the AB board has a more severe voltage overshoot. As can be seen from FIG. 10, the voltage overshoot Peak-Peak of the AB plate reaches 620V, while the voltage overshoot Peak-Peak of the 3D plate is only 130V, and the overshoot reduction amplitude reaches 4.77 times. This also demonstrates the higher stability of the 3D busbar Marx generator.
Further attention is paid to the drive voltage, also the gate voltage at the high voltage output stage. Because the negative pressure is used for switching off to reduce the risk of switch misconduction, the experiment process does not generate direct switch misconduction. As shown in fig. 10, under the 90A and 950V limit conditions, it can be clearly seen that the AB plate has a positive driving voltage due to the voltage oscillation of the parasitic inductance caused by the driving loop layout under the high di/dt condition. The 3D plates not only have a stable gate voltage waveform, but also produce an oscillation amplitude that is smaller than the AB plates. Therefore, the driving circuit of the 3D board has stronger anti-interference capability, and the stability and the reliability of the pulse generator can be further improved.
Claims (5)
1. The ultra-low parasitic inductance pulse forms a single module packaging structure, which is characterized by comprising an upper PCB and a lower PCB;
the top layer of the upper PCB is a grid drive circuit arrangement layer;
the bottom layer of the upper PCB, the top layer of the lower PCB and the bottom layer of the lower PCB are power loop arrangement layers;
the upper PCB and the lower PCB are connected through a MOSFET (metal oxide semiconductor field effect transistor) M1;
the upper PCB top layer and the upper PCB bottom layer are not directly electrically connected, and the lower PCB top layer and the lower PCB bottom layer are connected through a through hole (3);
the bottom layer of the upper PCB is connected with the top layer of the lower PCB in a direct welding mode;
the top layer of the upper PCB is provided with a gate drive circuit (2), a switch gate (8) and a switch Kelvin source (7);
the top layer of the lower PCB is provided with a switch drain electrode circuit (4), a switch source electrode circuit (5) and a grounding pin;
the bottom layer of the lower PCB is connected with two ends of an energy storage capacitor (6);
the current forms mutual inductance counteracting loops with opposite directions between the upper PCB and the lower PCB;
recording one end of the top layer of the PCB as an A end and the other end as a B end; one end of the bottom layer of the lower PCB is an A 'end, and the other end of the bottom layer of the lower PCB is a B' end;
a' of the bottom layer of the lower PCB is connected with the anode of the diode D, and the end A of the top layer of the lower PCB is connected with the cathode of the diode D.
2. The very low parasitic inductance pulse forming single module package structure of claim 1, wherein: a conductive medium is filled in a gap between the bottom layer of the upper PCB and the top layer of the lower PCB; the bottom layer of the upper PCB is electrically connected with the top layer of the lower PCB.
3. The very low parasitic inductance pulse forming single module package structure of claim 1, wherein the end B of the top layer of the lower PCB and the end B' of the bottom layer of the lower PCB are connected by a via (3).
4. The stacked package structure of the very low parasitic inductance pulse forming single module package structure according to any one of claims 1 to 3, comprising n very low parasitic inductance pulses forming a single module package structure; n is more than or equal to 2; n is a positive integer;
the ith-1 extremely low parasitic inductance pulse forming single module packaging structure is connected with the ith extremely low parasitic inductance pulse forming single module packaging structure through a connecting column; i =1,2, \8230;, n;
the lower PCB of the single-module packaging structure formed by the 1 st extremely-low parasitic inductance pulse is sequentially connected with a load R and the upper PCB of the single-module packaging structure formed by the nth extremely-low parasitic inductance pulse;
the 1 st extremely low parasitic inductance pulse forms a lower PCB of the single module packaging structure to receive external direct current and form a charging current loop;
after the 1 st ultra-low parasitic inductance pulse forms the single module packaging structure, the charging is finished through the charging diode D d1 Discharging to the 2 nd extremely low parasitic inductance pulse to form a single module packaging structure;
after the jth ultra-low parasitic inductance pulse forms the single module packaging structure, the charging is finished through a charging diode D dj Discharging to the jth extremely low parasitic inductance pulse to form a single module packaging structure; j =2,3, \8230;, n;
the nth extremely low parasitic inductance pulse forms the upper PCB ground of the single module package structure.
5. The very low parasitic inductance pulse forming single module package structure of claim 4, wherein the number of charging diodes is n-1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110262198.0A CN113163578B (en) | 2021-03-10 | 2021-03-10 | Ultra-low parasitic inductance pulse forming single module packaging structure and stacked packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110262198.0A CN113163578B (en) | 2021-03-10 | 2021-03-10 | Ultra-low parasitic inductance pulse forming single module packaging structure and stacked packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113163578A CN113163578A (en) | 2021-07-23 |
| CN113163578B true CN113163578B (en) | 2023-03-31 |
Family
ID=76886730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110262198.0A Active CN113163578B (en) | 2021-03-10 | 2021-03-10 | Ultra-low parasitic inductance pulse forming single module packaging structure and stacked packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113163578B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009045888A2 (en) * | 2007-09-28 | 2009-04-09 | Access Business Group International Llc | Printed circuit board coil |
| CN104112718A (en) * | 2014-07-25 | 2014-10-22 | 西安交通大学 | Double-surface low-parasitic inductance GaN power integrated module |
| CN107591377A (en) * | 2017-09-12 | 2018-01-16 | 华中科技大学 | More the DBC encapsulating structures and method for packing of a kind of power device |
| CN109427707A (en) * | 2017-08-31 | 2019-03-05 | 华中科技大学 | A kind of the three-dimension packaging structure and packaging method of power device |
| CN110838480A (en) * | 2019-11-09 | 2020-02-25 | 北京工业大学 | Packaging structure and manufacturing method of silicon carbide MOSFET module |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7838977B2 (en) * | 2005-09-07 | 2010-11-23 | Alpha & Omega Semiconductor, Ltd. | Packages for electronic devices implemented with laminated board with a top and a bottom patterned metal layers |
| CN202340177U (en) * | 2011-11-17 | 2012-07-18 | 广东明阳龙源电力电子有限公司 | Power module design for wind power converter |
| WO2014105887A1 (en) * | 2012-12-31 | 2014-07-03 | Efficient Power Conversion Corporation | Parasitic inductance reduction circuit board layout designs for multilayered semiconductor devices |
| CN103825479A (en) * | 2014-02-20 | 2014-05-28 | 华为技术有限公司 | Power converter |
| CN105914185B (en) * | 2016-06-21 | 2018-07-31 | 华中科技大学 | A kind of encapsulating structure and packaging method of silicon carbide power device |
| CN107170714B (en) * | 2017-06-14 | 2020-01-14 | 扬州国扬电子有限公司 | Low parasitic inductance power module and double-sided heat dissipation low parasitic inductance power module |
| US11183440B2 (en) * | 2018-12-10 | 2021-11-23 | Gan Systems Inc. | Power modules for ultra-fast wide-bandgap power switching devices |
| US11019718B2 (en) * | 2019-05-15 | 2021-05-25 | Efficient Power Conversion Corporation | Low parasitic inductance structure for power switched circuits |
-
2021
- 2021-03-10 CN CN202110262198.0A patent/CN113163578B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009045888A2 (en) * | 2007-09-28 | 2009-04-09 | Access Business Group International Llc | Printed circuit board coil |
| CN104112718A (en) * | 2014-07-25 | 2014-10-22 | 西安交通大学 | Double-surface low-parasitic inductance GaN power integrated module |
| CN109427707A (en) * | 2017-08-31 | 2019-03-05 | 华中科技大学 | A kind of the three-dimension packaging structure and packaging method of power device |
| CN107591377A (en) * | 2017-09-12 | 2018-01-16 | 华中科技大学 | More the DBC encapsulating structures and method for packing of a kind of power device |
| CN110838480A (en) * | 2019-11-09 | 2020-02-25 | 北京工业大学 | Packaging structure and manufacturing method of silicon carbide MOSFET module |
Non-Patent Citations (1)
| Title |
|---|
| 黄志召 ; 李宇雄 ; 陈材 ; 康勇 ; .基于新型混合封装的高速低感SiC半桥模块.电力电子技术.2017,第51卷(第12期),第20-22页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113163578A (en) | 2021-07-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230093824A1 (en) | Transformer resonant converter | |
| CN102856308B (en) | Power semiconductor modular | |
| US6337801B2 (en) | Three-phase zero-current-transition (ZCT) inverters and rectifiers with three auxiliary switches | |
| US20040160996A1 (en) | Apparatus and method for driving a pulsed laser diode | |
| Zhong et al. | Review on solid-state-based Marx generators | |
| JP2004214452A (en) | Semiconductor module for power and method for connecting to external electrode | |
| US11424690B2 (en) | Semiconductor switching arrangement | |
| CN104283448B (en) | Power-converting device | |
| Biebach et al. | Compact modular power supplies for superconducting inductive storage and for capacitor charging | |
| CN211826484U (en) | Multi-line laser module, laser radar and movable platform | |
| Modeer et al. | High-voltage tapped-inductor buck converter auxiliary power supply for cascaded converter submodules | |
| Ma et al. | Investigation and evaluation of solid-state Marx pulse generator based on 3-D busbar | |
| CN113163578B (en) | Ultra-low parasitic inductance pulse forming single module packaging structure and stacked packaging structure | |
| CN115955127A (en) | Three-level rectifier power module | |
| Jagannathan et al. | Impacts of package, layout and freewheeling diode on switching characteristics of Super Junction MOSFET in automotive DC-DC applications | |
| JP2005020868A (en) | Power converting circuit | |
| Giesselmann et al. | Rapid capacitor charger | |
| Yin et al. | Switching characterization of SiC half bridge module for high power density converter | |
| CN110429850B (en) | High-efficiency GaN three-phase inverter module for new energy power generation system | |
| Thekkeppat et al. | A solid-state converter topology,− 100 kV, 20 A, 1.6 ms, modulator for high average power klystron amplifier | |
| Giesselmann et al. | High voltage impulse generator using HV-IGBTs | |
| CN110912423A (en) | Three-layer laminated busbar structure with three-level bridge structure | |
| Zarghani et al. | An Energy Recovery Scheme for RCD Snubber in the Series Configuration of IGBTs | |
| Ajaykumar et al. | Series switched quasi impedance-source inverters with improved boosting ability | |
| Ramesh et al. | A Comparative Investigation of Clamping techniques for Bi-directional Energy Harvester Interface (BEHI) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |