CN107579058A - A kind of polymorphic type Stacked die package structure and preparation method thereof - Google Patents
A kind of polymorphic type Stacked die package structure and preparation method thereof Download PDFInfo
- Publication number
- CN107579058A CN107579058A CN201710781775.0A CN201710781775A CN107579058A CN 107579058 A CN107579058 A CN 107579058A CN 201710781775 A CN201710781775 A CN 201710781775A CN 107579058 A CN107579058 A CN 107579058A
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- Prior art keywords
- chip
- plastic
- wiring layer
- bonding
- array
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
The invention discloses a kind of polymorphic type Stacked die package structure and preparation method thereof, the encapsulating structure includes at least two chip packing-bodies stacked gradually from the bottom to top, chip packing-body includes functional chip, passivation layer, wiring layer and array welding column again, functional chip is molded to form a plastic-sealed body, the lower surface of plastic-sealed body is provided with passivation layer, wiring layer again is provided between the lower surface of plastic-sealed body and passivation layer, array welding column is arranged at the pad that in plastic-sealed body and is electrically connected on plastic-sealed body upper surface and again between wiring layer, functional chip is lead-bonding chip, large scale upside-down mounting welding core, it is combined between one kind in the small size upside-down mounting welding core that at least two same levels are placed and the functional chip in the chip package body of stacking.The present invention can complete the stacked package of multiclass cake core, reduce the cumulative volume of polymorphic type chip package, and vertical interconnection is completed by array welding column, and manufacture work flow is simple, and cost is low.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to a kind of polymorphic type Stacked die package structure and its making
Method.
Background technology
With the fast development of semiconductor integrated circuit, it is following hair of integrated circuit to meet that user customizes functional requirement
Exhibition trend, in order to reach multi-functional output, being integrally interconnected for multiclass cake core need to be carried out, simultaneously integrated circuit volume
Hard requirement small, in light weight is also gradually rising, and for above-mentioned application demand, the encapsulation of multiclass cake core 3-D stacks is gradual
Grow up.But integrated multi items, more scale chips have no very fixed universal architecture in a three-dimensional structure at present, typically all
Special design customization is needed, expends a large amount of designs and simulation cost, while production technology varies, yield rate can not ensure.Separately
Outer one side 3-D stacks encapsulation is usually to use silicon hole（TSV）Three-dimensional vertical interconnection is realized, although being sealed using the technology
It is minimum to fill volume, but process costs are higher.
The content of the invention
In order to solve the above-mentioned technical problem, the invention provides a kind of polymorphic type Stacked die package structure and its making side
Method.
In order to achieve the above object, technical scheme is as follows：
The present invention provides a kind of polymorphic type Stacked die package structure, including at least two chip envelopes stacked gradually from the bottom to top
Body is filled, chip packing-body includes functional chip, again passivation layer, wiring layer and array welding column, and functional chip is molded to form a plastic packaging
Body, the lower surface of plastic-sealed body are provided with passivation layer, are provided with wiring layer again between the lower surface of plastic-sealed body and passivation layer, plastic-sealed body it is upper
Pad is additionally provided with wiring layer on surface and again, array salient point, array are additionally provided with the pad on plastic-sealed body upper surface
Welding column is arranged at the pad that in plastic-sealed body and is electrically connected on plastic-sealed body upper surface and again between wiring layer, and functional chip is
One kind in lead-bonding chip, large scale upside-down mounting welding core, the small size upside-down mounting welding core that at least two same levels are placed
And it is combined between the functional chip in the chip package body stacked.
Preferably, lead-bonding chip is arranged on passivation layer and it is electrically connected with wiring layer again by bonding wire.
Preferably, the height of array welding column is higher than bonding wire camber line highest point level height, and array welding column material is copper cash.
Preferably, welding bulge loop is formed on the bottom of array welding column, and the diameter dimension for welding bulge loop is more than the straight of array welding column
Footpath size.
Preferably, large scale upside-down mounting welding core is electrically connected with wiring layer again by pedestal, small size upside-down mounting welding core
Electrically connected with wiring layer again by pedestal.
Preferably, array salient point is spherical or cylindricality.
The present invention also provides a kind of preparation method of polymorphic type Stacked die package structure, comprises the following steps：
S1, from a carrier disk, made in the upper surface of carrier disk or one layer of interim bonding film of attachment；
S2, make wiring layer and passivation layer again；
S3, by the attachment of the back side of lead-bonding chip over the passivation layer, and carry out wire bonding with bonding wire；
S4, the plant post formation array welding column of array is being carried out on wiring layer again；
S5, the leaded fixation of lead-bonding chip and institute formed by plastic-sealed body by injection using Shooting Technique；
S6, Redundant arrays welding column outside plastic-sealed body polished flat, make in the upper surface of plastic-sealed body and on wiring layer pad again,
Array salient point is made on pad on plastic-sealed body upper surface；
S7, using solution bonding method lead-bonding chip packaging body and interim bonding film are peeled off, then pass through the cutting-up of disk
Form multiple the first independent chip packing-bodies；
S8, the process using above-mentioned steps S1- steps S7, large scale upside-down mounting welding core is selected to replace lead-bonding chip,
Make the second independent chip packing-body；
S9, the process using above-mentioned steps 1- steps S7, selection at least two small size upside-down mounting welding cores replace lead key
Chip is closed, while flip chip bonding on wiring layer, is making the 3rd independent chip packing-body again；
S10, using Flip Chip Bond Technique, by the first independent chip packing-body, the second chip packing-body and the 3rd chip packing-body
Any combination is stacked, and completes polymorphic type Stacked die package structure.
Preferably, connect up manufacture craft in step S2 again by wafer scale and make wiring layer again, pass through spin coating or spraying side
Legal system makees passivation layer.
Preferably, pad and array salient point are made by wafer scale technique in step S6.
The invention has the advantages that：
1st, the external structure of each chip packing-body is identical, and the design of encapsulating structure can carry out generalization customization, effectively reduces
Design cost is encapsulated, and production process is identical, and yield rate is easily controlled during production；
2nd, any type of chip, such as lead-bonding chip, large scale flip chip bonding can be encapsulated inside each chip packing-body
Chip or the upside-down mounting welding core of multiple small sizes etc., go for various types of chip portfolio encapsulation, it is versatile；
3rd, each chip packing-body upper and lower surface completes electricity interconnection by array welding column, and compare silicon hole（TSV）Process costs
It is relatively low；
4th, the pad reserved again on wiring layer, the array salient point made with array welding column upper end, it is possible to achieve multiple same structures
Packaging body it is three-dimensional stacked；
5th, each chip packing-body makes the wiring layer again of tow sides by wafer scale technique, and whole disk is processed simultaneously, raw
Efficiency high is produced, effectively reduces packaging cost.
Brief description of the drawings
Fig. 1 is a kind of structure of the polymorphic type Stacked die package structure of the present invention on carrier disk after interim bonding film
Schematic diagram.
Fig. 2 is that a kind of polymorphic type Stacked die package structure of the present invention makes wiring layer again and blunt on interim bonding film
Change the schematic diagram after layer.
Fig. 3 is showing after a kind of polymorphic type Stacked die package structure of present invention attachment lead-bonding chip and bonding wire
It is intended to.
Fig. 4 is that a kind of polymorphic type Stacked die package structure of the present invention makes the schematic diagram after array welding column.
Fig. 5 is that a kind of polymorphic type Stacked die package structure of the present invention is molded into the schematic diagram after plastic-sealed body.
Fig. 6 is that a kind of polymorphic type Stacked die package structure of the present invention makes the schematic diagram after pad and array salient point.
Fig. 7 is that the completion of disk cutting-up is single after a kind of polymorphic type Stacked die package structure of the present invention peels off interim bonding film
The schematic diagram of lead-bonding chip packaging body.
Fig. 8 is a kind of large scale upside-down mounting welding core package body structure of polymorphic type Stacked die package structure of the present invention
Structural representation.
Fig. 9 is a kind of double small size upside-down mounting welding core package body structure of polymorphic type Stacked die package structure of the present invention
Structural representation.
Figure 10 is a kind of three kinds of different type chip packing-body lamination knots of polymorphic type Stacked die package structure of the present invention
Structure schematic diagram.
Wherein, 1, wiring layer again, 2, passivation layer, 3, lead-bonding chip, 4, bonding wire, 5, array welding column, 6, plastic-sealed body,
7th, pad, 8, array salient point, 9, large scale upside-down mounting welding core, the 10, first small size upside-down mounting welding core 1,11, the second small size are fallen
Welding equipment chip, the 100, first chip packing-body, the 200, second chip packing-body, the 300, the 3rd chip packing-body.
Embodiment
The preferred embodiment that the invention will now be described in detail with reference to the accompanying drawings.
In order to reach the purpose of the present invention, as shown in Figure 10, provided in the one of which embodiment of the present invention a kind of
Polymorphic type Stacked die package structure, including the 3rd chip packing-body 300, the second chip packing-body stacked gradually from the bottom to top
200 and first chip packing-body 100, each chip packing-body include functional chip, again passivation layer 2, wiring layer 1 and array welding column
5, functional chip forms a plastic-sealed body 6 by being molded, and the lower surface of plastic-sealed body 6 is provided with passivation layer 2, the lower surface of plastic-sealed body 6 with
It is provided with wiring layer 1 again between passivation layer 2, pad 7 is additionally provided with the upper surface of plastic-sealed body 6 and on wiring layer 1 again, positioned at modeling
Array salient point 8 is additionally provided with pad 7 on envelope body 6 upper surface, array welding column 5, which is arranged in plastic-sealed body 6 and is electrically connected to, to be located at
Pad 7 on the upper surface of plastic-sealed body 6 and again between wiring layer 1, the functional chip of the first chip packing-body 100 is wire bonding core
Piece, the functional chip of the second chip packing-body 200 are large scale upside-down mounting welding core 9, the functional chip of the 3rd chip packing-body 300
The the first small size upside-down mounting welding core 10 and the second small size upside-down mounting welding core 11 placed for same level.
Wherein, lead-bonding chip 3 is arranged on passivation layer 2 and it is electrically connected with wiring layer 1 again by bonding wire 4；Battle array
The height of row welding column 5 is higher than the camber line highest point level height of bonding wire 4, and the material of array welding column 5 is copper cash；The bottom of array welding column 5
Portion forms welding bulge loop, and the diameter dimension for welding bulge loop is more than the diameter dimension of array welding column；Large scale upside-down mounting welding core 9 with again
Wiring layer is electrically connected by pedestal, the first small size upside-down mounting welding core 10 and the second small size upside-down mounting welding core 11 respectively with
Wiring layer is electrically connected by pedestal again；Array salient point is spherical or cylindricality.
In order to further optimize the implementation result of the present invention, in another embodiment of the invention, foregoing interior
On the basis of appearance, present embodiment also provides a kind of preparation method of polymorphic type Stacked die package structure, such as Fig. 1 to Figure 10 institutes
Show, comprise the following steps：
S1, from a carrier disk 13, made in the upper surface of carrier disk 13 or one layer of interim bonding film 12 of attachment；
S2, connect up manufacture craft making wiring layer 1 again again by wafer scale, pass through spin coating or spraying method makes passivation layer 2；
S3, the back side of lead-bonding chip 3 is mounted on passivation layer 1, and wire bonding is carried out with bonding wire 4；
S4, the plant post formation array welding column 5 of array is being carried out on wiring layer 1 again；
S5, the leaded fixation of lead-bonding chip 3 and institute formed by plastic-sealed body 6 by injection using Shooting Technique；
S6, the outer Redundant arrays welding column of plastic-sealed body 6 polished flat, make in the upper surface of plastic-sealed body 6 and on wiring layer pad again
7, array salient point 8 is made on the pad 7 on the upper surface of plastic-sealed body 6；Wherein, pad 7 and array are made by wafer scale technique
Salient point 8；
S7, using solution bonding method lead-bonding chip packaging body and interim bonding film are peeled off, then pass through the cutting-up of disk
Form multiple the first independent chip packing-bodies 100；
S8, the process using above-mentioned steps S1- steps S7, large scale upside-down mounting welding core is selected to replace lead-bonding chip,
Make the second independent chip packing-body 200；
S9, the process using above-mentioned steps 1- steps S7, the first small size upside-down mounting welding core and the second small size is selected to fall
Welding equipment chip replaces lead-bonding chip, while flip chip bonding on wiring layer, is making the 3rd independent chip packing-body 300 again；
S10, using Flip Chip Bond Technique, by the 3rd independent chip packing-body 300, the second chip packing-body 200 and the first chip
Packaging body 100 stacks gradually together from the bottom to top, completes polymorphic type Stacked die package structure.
Above-described is only the preferred embodiment of the present invention, it is noted that for one of ordinary skill in the art
For, without departing from the concept of the premise of the invention, various modifications and improvements can be made, these belong to the present invention
Protection domain.
Claims (10)
1. a kind of polymorphic type Stacked die package structure, it is characterised in that including at least two cores stacked gradually from the bottom to top
Piece packaging body, chip packing-body includes functional chip, passivation layer, again wiring layer and array welding column, functional chip are molded to form one
Plastic-sealed body, the lower surface of plastic-sealed body are provided with passivation layer, and wiring layer again, plastic-sealed body are provided between the lower surface of plastic-sealed body and passivation layer
Upper surface on and pad is additionally provided with wiring layer again, be additionally provided with array salient point on the pad on plastic-sealed body upper surface,
Array welding column is arranged at the pad that in plastic-sealed body and is electrically connected on plastic-sealed body upper surface and again between wiring layer, function core
Piece is in lead-bonding chip, large scale upside-down mounting welding core, the small size upside-down mounting welding core that at least two same levels are placed
It is combined between functional chip in a kind of and stacking chip package body.
2. polymorphic type Stacked die package structure according to claim 1, it is characterised in that lead-bonding chip is arranged at
On passivation layer and it is electrically connected with wiring layer again by bonding wire.
3. polymorphic type Stacked die package structure according to claim 2, it is characterised in that the height of array welding column is higher than
Bonding wire camber line highest point level height.
4. polymorphic type Stacked die package structure according to claim 1, it is characterised in that array welding column material is copper
Line.
5. polymorphic type Stacked die package structure according to claim 1, it is characterised in that the bottom of array welding column is formed
Bulge loop is welded, the diameter dimension for welding bulge loop is more than the diameter dimension of array welding column.
6. polymorphic type Stacked die package structure according to claim 1, it is characterised in that large scale upside-down mounting welding core with
Wiring layer is electrically connected by pedestal again, and small size upside-down mounting welding core is electrically connected with wiring layer again by pedestal.
7. polymorphic type Stacked die package structure according to claim 1, it is characterised in that array salient point is spherical or post
Shape.
A kind of 8. preparation method of polymorphic type Stacked die package structure as described in claim 1-7 is any, it is characterised in that
Comprise the following steps：
S1, from a carrier disk, made in the upper surface of carrier disk or one layer of interim bonding film of attachment；
S2, make wiring layer and passivation layer again；
S3, by the attachment of the back side of lead-bonding chip over the passivation layer, and carry out wire bonding with bonding wire；
S4, the plant post formation array welding column of array is being carried out on wiring layer again；
S5, the leaded fixation of lead-bonding chip and institute formed by plastic-sealed body by injection using Shooting Technique；
S6, Redundant arrays welding column outside plastic-sealed body polished flat, make in the upper surface of plastic-sealed body and on wiring layer pad again,
Array salient point is made on pad on plastic-sealed body upper surface；
S7, using solution bonding method lead-bonding chip packaging body and interim bonding film are peeled off, then pass through the cutting-up of disk
Form multiple the first independent chip packing-bodies；
S8, the process using above-mentioned steps S1- steps S7, large scale upside-down mounting welding core is selected to replace lead-bonding chip,
Make the second independent chip packing-body；
S9, the process using above-mentioned steps 1- steps S7, selection at least two small size upside-down mounting welding cores replace lead key
Chip is closed, while flip chip bonding on wiring layer, is making the 3rd independent chip packing-body again；
S10, using Flip Chip Bond Technique, by the first independent chip packing-body, the second chip packing-body and the 3rd chip packing-body
Any combination is stacked, and completes polymorphic type Stacked die package structure.
9. the preparation method of polymorphic type Stacked die package structure according to claim 1, it is characterised in that in step S2
Connect up manufacture craft again by wafer scale and make wiring layer again, passivation layer is made by spin coating or spraying method.
10. the preparation method of polymorphic type Stacked die package structure according to claim 1, it is characterised in that step S6
In pass through wafer scale technique and make pad and array salient point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710781775.0A CN107579058A (en) | 2017-09-02 | 2017-09-02 | A kind of polymorphic type Stacked die package structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710781775.0A CN107579058A (en) | 2017-09-02 | 2017-09-02 | A kind of polymorphic type Stacked die package structure and preparation method thereof |
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| Publication Number | Publication Date |
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| CN107579058A true CN107579058A (en) | 2018-01-12 |
Family
ID=61031141
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| CN201710781775.0A Pending CN107579058A (en) | 2017-09-02 | 2017-09-02 | A kind of polymorphic type Stacked die package structure and preparation method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060255458A1 (en) * | 2003-10-15 | 2006-11-16 | Jochen Dangelmaier | Semiconductor module provided with contacts extending through the package |
| CN1921108A (en) * | 2005-08-23 | 2007-02-28 | 新光电气工业株式会社 | Semiconductor package and manufacturing method thereof |
| US20090008762A1 (en) * | 2007-07-02 | 2009-01-08 | Nepes Corporation | Ultra slim semiconductor package and method of fabricating the same |
| CN103582946A (en) * | 2011-05-03 | 2014-02-12 | 泰塞拉公司 | Package-on-package assembly with wire bond to encapsulation surface |
-
2017
- 2017-09-02 CN CN201710781775.0A patent/CN107579058A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060255458A1 (en) * | 2003-10-15 | 2006-11-16 | Jochen Dangelmaier | Semiconductor module provided with contacts extending through the package |
| CN1921108A (en) * | 2005-08-23 | 2007-02-28 | 新光电气工业株式会社 | Semiconductor package and manufacturing method thereof |
| US20090008762A1 (en) * | 2007-07-02 | 2009-01-08 | Nepes Corporation | Ultra slim semiconductor package and method of fabricating the same |
| CN103582946A (en) * | 2011-05-03 | 2014-02-12 | 泰塞拉公司 | Package-on-package assembly with wire bond to encapsulation surface |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180112 |
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| RJ01 | Rejection of invention patent application after publication |