CN105957842A - High efficiency reconfigurable three-dimensional packaging structure - Google Patents
High efficiency reconfigurable three-dimensional packaging structure Download PDFInfo
- Publication number
- CN105957842A CN105957842A CN201610403014.7A CN201610403014A CN105957842A CN 105957842 A CN105957842 A CN 105957842A CN 201610403014 A CN201610403014 A CN 201610403014A CN 105957842 A CN105957842 A CN 105957842A
- Authority
- CN
- China
- Prior art keywords
- dimension packaging
- packaging structure
- tsv
- restructural
- tsv keyset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
Abstract
The invention relates to a high efficiency reconfigurable three-dimensional packaging structure which is formed by the up and down interconnection of a plurality of two-dimensional element structures through a metal solder. Each of the two-dimensional element structures comprises a function chip, a TSV adaption plate, a filling material, and a rewiring layer. The function chip and the TSV adaption plate are placed in the same horizontal and form an integrated structure through the filling material. The surface of the obtained structure is provided with the rewiring layer, and the signal interconnection between the function chip and the TSV adaption plate is realized through the rewiring layer. According to the invention, the TSV adaption plate capable of improving production efficiency and a side TSV adaption method are employed, the three-dimensional packaging structure is formed by stacking the two-dimensional element structures, and the diversity and reconstruction of overall package are realized.
Description
Technical field
The invention belongs to integrated antenna package technical field, especially a kind of efficiently restructural three-dimension packaging structure.
Background technology
Function along with electronic system constantly strengthens, and wiring and packing density are more and more higher, send out to the direction of high-speed high frequency in addition
Exhibition, range of application is increasingly wider, and chip, on the basis of multi-chip package, is stacked by people further in the vertical, i.e.
So-called 3D encapsulation.The concrete structure of 3D encapsulation at present, there are different designs, technical process in each company according to the demand of self
Multifarious, complexity is had nothing in common with each other, and production efficiency is relatively low.Complexity improves then brings product yields to decline, and one
In individual overall three-dimension packaging structure, some micro structure goes wrong, and can cause the destruction of overall structure function, and reconfigurability is poor,
Recycling rate of waterused is low, causes the waste of resource.
In three-dimension packaging structure, chip is to interconnect up and down with TSV keyset major part, and this kind of mode is in IC chip features
Size reduction and collection expansion on a large scale, Wire Bonding Technology produces under conditions of being no longer suitable for, and the advantage of which is to make
I/O can be distributed in and no longer be limited only to narrow IC chip perimeter region on the whole surface of IC chip, thus solves
High density, the electrical connection problem of thin space I/O chip, but it is disadvantageous in that z fixes to structure distribution, causes knot
Structure is single, is unfavorable for the multiformity of encapsulating structure, part microstructure breakage, it is impossible to maintenance, causes allomeric function to destroy.Simultaneously
In traditional handicraft, carrying out matching design according to every kind of chip and manufacture corresponding TSV keyset, technical process is complicated, and efficiency is relatively low.
Summary of the invention
The technical problem to be solved in the present invention is to overcome existing defect, it is provided that a kind of efficiently restructural three-dimension packaging structure, uses
The TSV keyset of production efficiency can be improved and use side TSV forwarding method, secondary structure build stack forming three-dimensional envelope
Assembling structure, it is achieved the variation of overall package and reconfigurability.
In order to solve above-mentioned technical problem, the invention provides following technical scheme:
A kind of efficiently restructural three-dimension packaging structure of the present invention, this three-dimension packaging structure is passed through metal by several secondary structure structures
Solder interconnects composition up and down；Secondary structure structure includes functional chip, TSV keyset, packing material and wiring layer, function again
Chip, TSV keyset same level are placed and are encapsulated as an overall structure by packing material, are provided with on resulting structures surface
Wiring layer and realize functional chip, TSV keyset signal interconnection between the two by wiring layer more again.
Further, TSV keyset is design requirement to be electrically interconnected according to functional chip, intercepts between the prefabricated through hole of corresponding size
Away from fixing TSV keyset disk gained.
Further, three-dimension packaging structure is realized Z-direction interconnection by several secondary structure structures by TSV keyset back side soldered ball
Composition.
Further, out of order secondary structure structure in three-dimension packaging structure is by disassembling three-dimension packaging structure after heating up, right
After patting at intact secondary structure body structure surface, the mode re-assemblied with new secondary structure structure realizes restructural.
Beneficial effects of the present invention:
1, use the TSV keyset disk that prefabricated through hole pitch is fixing, design requirement be electrically interconnected according to according to functional chip,
Intercepting obtains corresponding TSV keyset, simplifies and secures technical process, improve packaging efficiency.
2, use the method for side TSV keyset to realize 3D interconnection, simplify interconnection mode, provide premise for reconfigurability.
3, the reconfigurability of three-dimension packaging is achieved: have cured the encapsulation mode of secondary structure structure, thus reach two purposes,
One is three-dimensional stacked front and back if any the defective or secondary structure structure of afunction, can replace easily；Two is can be flexible
Combined two-dimension primitive structure, it is achieved the variation of three-dimension packaging.
Accompanying drawing explanation
Fig. 1 is the TSV keyset disk that the prefabricated through-hole spacing of a kind of efficient restructural three-dimension packaging structure of the present invention is fixing；
Fig. 2 is the secondary structure structural representation of a kind of efficient restructural three-dimension packaging structure of the present invention；
Fig. 3 is a kind of efficiently restructural three-dimension packaging structural representation of the present invention.
Wherein, 1-functional chip, 2-TSV keyset, 3-packing material, 4-wiring layer again, 5-soldered ball, 6-slide glass.
Detailed description of the invention
Embodiment cited by the present invention, is only intended to help and understands the present invention, should not be construed as the limit to scope
Fixed, for those skilled in the art, without departing from the inventive concept of the premise, it is also possible to the present invention
Making improvements and modifications, these improve and modification also falls in the range of the claims in the present invention protection.
As it is shown on figure 3, a kind of efficiently restructural three-dimension packaging structure of the present invention, by several secondary structure structures by soldered ball 5
Realize Z-direction interconnection composition three-dimension packaging structure；Secondary structure structure includes functional chip 1, TSV keyset 2, packing material 3
Wiring layer 4 again, functional chip 1, TSV keyset 2 same level are placed and are encapsulated as an entirety by packing material 3 and tie
Structure, is provided with wiring layer 4 again and realizes functional chip 1, both TSV keysets 2 by wiring layer 4 again on resulting structures surface
Between signal interconnection.
The preparation method of this three-dimension packaging structure, comprises the following steps:
(1) use a kind of efficient technological design, i.e. use between the through hole of prefabricated (prepared by common processes) as shown in Figure 1
Away from fixing TSV keyset disk, require and the signal exit of functional chip 1 according to the design that is electrically interconnected of functional chip 1
The specific requirement of quantity, intercepts the TSV keyset 2 obtaining corresponding size by scribing；
(2) by functional chip 1 and TSV keyset 2 first interim attachment a to slide glass 6, functional chip 1 front towards
Slide glass 6；
(3) the two kinds of devices (functional chip 1 and TSV keyset 2) on slide glass 6 are packaged, TSV keyset 2
It is packaged in functional chip 1 side (using side TSV keyset method), then slide glass 6 is taken off；
(4) make on above-mentioned resulting structures surface by photoetching but by the way of being not limited to and connect up (RDL) layer 4 again, it is achieved function
Signal exit (I/O) transfer of chip 1, thus prepare secondary structure structure, as shown in Figure 2.
(5) (Z in upper and lower vertical direction is realized by TSV keyset 2 back side soldered ball 5 between the secondary structure structure of gained
To) interconnection, thus prepare three-dimension packaging structure, as shown in Figure 3.When the gained a certain secondary structure of three-dimension packaging structure is tied
Structure breaks down, and three-dimension packaging structure is disassembled, intact secondary structure structure is carried out table after being suitably warming up to soldered ball 5 fusing
After patting (chemical machinery polishes) at face, re-assembly with new secondary structure structure, it is achieved restructural.
Claims (4)
1. an efficient restructural three-dimension packaging structure, it is characterised in that: described three-dimension packaging structure is tied by several secondary structure
Structure interconnects composition up and down by brazing metal；Described secondary structure structure includes functional chip (1), TSV keyset (2), fills out
Filling material (3) and wiring layer (4) again, functional chip (1), TSV keyset (2) same level are placed and by filling material
Material (3) is encapsulated as an overall structure, is provided with wiring layer (4) on resulting structures surface again and is realized by wiring layer (4) again
Functional chip (1), TSV keyset (2) signal interconnection between the two.
Efficient restructural three-dimension packaging structure the most according to claim 1, it is characterised in that: described TSV keyset (2)
It is design requirement to be electrically interconnected according to functional chip (1), intercepts the TSV keyset that the prefabricated through-hole spacing of corresponding size is fixing
Disk gained.
Efficient restructural three-dimension packaging structure the most according to claim 1, it is characterised in that: described three-dimension packaging structure by
Several secondary structure structures realize Z-direction interconnection composition by TSV keyset (2) back side soldered ball (5).
Efficient restructural three-dimension packaging structure the most according to claim 1, it is characterised in that: in described three-dimension packaging structure
Out of order secondary structure structure, by disassembling three-dimension packaging structure after heating up, pats at intact secondary structure body structure surface
After, the mode re-assemblied with new secondary structure structure realizes restructural.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610403014.7A CN105957842A (en) | 2016-06-08 | 2016-06-08 | High efficiency reconfigurable three-dimensional packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610403014.7A CN105957842A (en) | 2016-06-08 | 2016-06-08 | High efficiency reconfigurable three-dimensional packaging structure |
Publications (1)
| Publication Number | Publication Date |
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| CN105957842A true CN105957842A (en) | 2016-09-21 |
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ID=56908190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
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| CN201610403014.7A Pending CN105957842A (en) | 2016-06-08 | 2016-06-08 | High efficiency reconfigurable three-dimensional packaging structure |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107507816A (en) * | 2017-08-08 | 2017-12-22 | 中国电子科技集团公司第五十八研究所 | Fan-out-type wafer scale multilayer wiring encapsulating structure |
| CN107634049A (en) * | 2017-09-15 | 2018-01-26 | 中国电子科技集团公司第五十八研究所 | FC chip systems stack fan-out packaging structure and preparation method thereof |
| CN107706172A (en) * | 2017-08-22 | 2018-02-16 | 中国电子科技集团公司第五十八研究所 | The wafer scale three-dimension packaging structure of multilayer wiring |
| CN110060993A (en) * | 2019-04-26 | 2019-07-26 | 胡志刚 | Multilayer chiop framework and connection method |
| CN110544673A (en) * | 2019-09-12 | 2019-12-06 | 西安电子科技大学 | Multilayer fused three-dimensional system integrated structure |
| CN110581124A (en) * | 2019-09-12 | 2019-12-17 | 西安电子科技大学 | preparation method of multi-level fused three-dimensional system integrated structure |
| CN112234026A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 3D chip package |
-
2016
- 2016-06-08 CN CN201610403014.7A patent/CN105957842A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107507816A (en) * | 2017-08-08 | 2017-12-22 | 中国电子科技集团公司第五十八研究所 | Fan-out-type wafer scale multilayer wiring encapsulating structure |
| CN107706172A (en) * | 2017-08-22 | 2018-02-16 | 中国电子科技集团公司第五十八研究所 | The wafer scale three-dimension packaging structure of multilayer wiring |
| CN107634049A (en) * | 2017-09-15 | 2018-01-26 | 中国电子科技集团公司第五十八研究所 | FC chip systems stack fan-out packaging structure and preparation method thereof |
| CN110060993A (en) * | 2019-04-26 | 2019-07-26 | 胡志刚 | Multilayer chiop framework and connection method |
| CN110544673A (en) * | 2019-09-12 | 2019-12-06 | 西安电子科技大学 | Multilayer fused three-dimensional system integrated structure |
| CN110581124A (en) * | 2019-09-12 | 2019-12-17 | 西安电子科技大学 | preparation method of multi-level fused three-dimensional system integrated structure |
| CN110581124B (en) * | 2019-09-12 | 2021-03-19 | 西安电子科技大学 | Preparation method of multi-level fused three-dimensional system integrated structure |
| CN110544673B (en) * | 2019-09-12 | 2021-03-19 | 西安电子科技大学 | Multilayer fused three-dimensional system integrated structure |
| CN112234026A (en) * | 2020-10-14 | 2021-01-15 | 天津津航计算技术研究所 | 3D chip package |
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Application publication date: 20160921 |