CN107546273A - A kind of VDMOS device with anti-SEB abilities - Google Patents
A kind of VDMOS device with anti-SEB abilities Download PDFInfo
- Publication number
- CN107546273A CN107546273A CN201710726322.8A CN201710726322A CN107546273A CN 107546273 A CN107546273 A CN 107546273A CN 201710726322 A CN201710726322 A CN 201710726322A CN 107546273 A CN107546273 A CN 107546273A
- Authority
- CN
- China
- Prior art keywords
- type semiconductor
- conductive type
- conductive
- semiconductor body
- body area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of VDMOS device with anti-SEB abilities, stacks gradually metalized drain, the first conductive type semiconductor substrate, the first conductive type semiconductor epitaxial layer, metallizing source from top to bottom；Also include the second conductive type semiconductor body area, the first conductive type semiconductor source region, the second conductive type semiconductor body contact zone, there is grid structure between the second conductive type semiconductor body area of both sides；The present invention in the bottom in the second conductive type semiconductor body area by introducing carrier boot section, the Impurity Distribution of boot section can produce built-in field, the built-in field can guide carrier to avoid flowing through the part that the second conductive type semiconductor body area is located at immediately below the first conductive type semiconductor source region, so as to prevent the unlatching of parasitic triode, the anti-SEB abilities of VDMOS when single-particle radiates are improved.
Description
Technical field
The present invention relates to technical field of semiconductor device, and in particular to a kind of VDMOS device with anti-SEB abilities.
Background technology
With fast development of the Power Electronic Technique to high-frequency high-power application field, VDMOS turns into field of power electronics
In one of irreplaceable important devices, it is increasing using VDMOS Power Electronic Circuit.The structure devices generally use
Secondary diffusion or ion implantation technique are formed, and are multi cell devices, are easily integrated, and power density is big, and more subconductivity, and frequency is special
Property is good.VDMOS is one of power MOS main flow device at present.As power switch, VDMOS has high pressure, switching speed
It hurry up, low on-resistance, low driving power, good thermal stability, low noise and widely use the advantages that simple manufacturing process
In the various fields such as Switching Power Supply, AC Drive, variable-frequency power sources, computer equipment, and obtain ideal effect.
The problem of irradiation effect of semiconductor devices is a complexity, because different types of irradiation, to semiconductor devices
Influence be different.The irradiation for mainly having four types can produce irradiation effect to semiconductor devices, and they are matter respectively
Son, electronics, neutron and gamma-rays.The factor for producing material impact and most study to microelectronic component mainly has γ accumulated dose spokes
Penetrate, gamma dose rate radiation, neutron irradiation and single particle effect.
VDMOS single particle effect is broadly divided into single event burnout (SEB) and single event gate rupture (SEGR), wherein single-particle
Burn larger with device inside structural parameters correlation, its principle is as described below：VDMOS N+ source regions, Pbody and N- drift regions
Between, there is a parasitic transistor structure, they respectively constitute the launch site, base and collecting zone of parasitic transistor, and one
As in the case of, the emitter stage of parasitic transistor and base stage realize short circuit by source electrode, so as to not produced to the external behavior of device
Influence.Under radiation environment, injection particle produces a large amount of electron hole pairs in VDMOS device, in drift field and spreads dual
Under effect, through spreading and drifting about, the stream that generates electricity in wink is formed.The horizontal proliferation flowed that generates electricity in wink produces pressure drop on the resistance of base, when
When pressure drop increases to certain value, parasitic transistor conducting.When the drain-source voltage of MOS transistor is more than breakdown voltage, crystalline substance is flowed through
The electric current of body pipe can further be fed back so that the current density of depletion region is gradually increasing, and causes second breakdown between drain-source, such as
Fruit junction temperature exceedes permissible value, then causes burning for source-drain junction.Thus reduce the resistance below VDMOS device N+ source regions, that is, increase
Pbody areas concentration is to improve the effective ways that device anti-single particle burns.Consider the influence to device threshold, Pbody areas concentration
Can not be too big, thus by increase Pbody concentration reduce the method for the resistance below VDMOS device N+ source regions act on it is limited.
The content of the invention
The purpose of the present invention proposes a kind of with anti-aiming at problem present in above-mentioned conventional power VDMOS device
The VDMOS device of SEB abilities.
To achieve the above object, the present invention adopts the following technical scheme that：
A kind of VDMOS device with anti-SEB abilities, stacks gradually metalized drain, the first conduction type from top to bottom
Semiconductor substrate, the first conductive type semiconductor epitaxial layer, metallizing source；In the first conductive type semiconductor epitaxial layer
There is the second conductive type semiconductor body area respectively at left and right sides of portion upper surface；Inside each second conductive type semiconductor body area
Upper surface has the first conductive type semiconductor source region and the second conductive type semiconductor body contact zone；First conduction type
Semiconductor source region and the second conductive type semiconductor body contact zone are connected with metallizing source；Second conduction type of both sides half
There is grid structure between conductor body area；The polygate electrodes of the grid structure and the first conductive type semiconductor extension
Across gate oxide between floor, the second conductive type semiconductor body area and the first conductive type semiconductor source region three；It is described more
Insulating medium layer is filled between crystal silicon gate electrode and metallizing source, the bottom in the second conductive type semiconductor body area has
The carrier boot section of first conductive type semiconductor；The impurity concentration of the carrier boot section of first conductive type semiconductor is non-
It is uniformly distributed, the distribution mode of its impurity concentration is：On the horizontal direction of device, pointed to from close to grid structure away from grid
Direction on, impurity concentration gradually reduces.
It is preferred that the carrier of the first conductive type semiconductor below the second conductive type semiconductor body area draws
Area is led, in the horizontal including the n subregions with different levels of doping, n is more than or equal to 3, and the doping concentration of subregion expires
Foot：As the distance with polygate electrodes gradually increases, the doping concentration of subregion is gradually reduced.
It is preferred that the material of first conductive type semiconductor or second conductive type semiconductor is
Body silicon, carborundum, GaAs, indium phosphide or germanium silicon composite one kind therein.
It is preferred that the first conduction type is p-type, the second conduction type is N-type；Or first conduction type be N
Type, the second conduction type are p-type.
Beneficial effects of the present invention are：Guided by introducing carrier in the bottom in the second conductive type semiconductor body area
Area, the Impurity Distribution of boot section can produce built-in field, and the built-in field can guide carrier to avoid flowing through the second conduction
Type semiconductor body area is located at the part immediately below the first conductive type semiconductor source region, so as to prevent opening for parasitic triode
Open, improve the anti-SEB abilities of VDMOS when single-particle radiates.
Brief description of the drawings
Fig. 1 is a kind of structural representation of VDMOS device with anti-SEB abilities of the present invention；
Fig. 2 is electronics and hole flow graph of the ordinary power VDMOS device when single-particle radiation occurs；
Fig. 3 is the built-in field direction and hair that a kind of N-type VDMOS device with anti-SEB abilities of the present invention is formed
Electronics and hole flow graph during raw single-particle radiation；
Fig. 4 is the structural representation of the embodiment of the present invention 2；
Wherein, 101 be metalized drain, and 102 be the first conductive type semiconductor substrate, and 103 be the first conduction type half
Conductor epitaxial layer, 104 be polygate electrodes, and 105 be gate oxide, and 106 be the first conductive type semiconductor source region, and 107 are
Second conductive type semiconductor body contact zone, 108 be the second conductive type semiconductor body area, and 109 be insulating medium layer, and 110 are
Metallizing source, 11 be the carrier boot section of the first conductive type semiconductor, and 111,112 ... 11n are subregion, and n is more than
Equal to 3.
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Embodiment 1
As shown in figure 1, a kind of VDMOS device with anti-SEB abilities, stack gradually from top to bottom metalized drain 101,
First conductive type semiconductor substrate 102, the first conductive type semiconductor epitaxial layer 103, metallizing source 110；Described first
There is the second conductive type semiconductor body area 108 respectively at left and right sides of the inside upper surface of conductive type semiconductor epitaxial layer 103；Often
The individual inside upper surface of second conductive type semiconductor body area 108 has the first conductive type semiconductor source region 106 and second conductive
Type semiconductor body contact zone 107；The first conductive type semiconductor source region 106 and the contact of the second conductive type semiconductor body
Area 107 is connected with metallizing source 110；There is grid structure between second conductive type semiconductor body area 108 of both sides；Institute
State the conductive type semiconductor epitaxial layer 103 of polygate electrodes 104 and first, the second conductive type semiconductor body of grid structure
Across gate oxide 105 between the three of 108 and first conductive type semiconductor source region of area 106；The polygate electrodes 104 with
Fill insulating medium layer 109 between metallizing source 110, the bottom in the second conductive type semiconductor body area 108 has the
The carrier boot section 11 of one conductive type semiconductor；The impurity concentration of the carrier boot section 11 of first conductive type semiconductor
Non-uniform Distribution, the distribution mode of its impurity concentration are：On the horizontal direction of device, pointed to from close to grid structure away from grid
On the direction of pole, impurity concentration gradually reduces.
The material of first conductive type semiconductor or second conductive type semiconductor be body silicon, carborundum,
GaAs, indium phosphide or germanium silicon composite one kind therein.
It is assumed that the first conductive type semiconductor is N-type semiconductor, the second conduction type is p-type.By taking N-channel device as an example,
Illustrate the operation principle of the present embodiment：
As shown in Fig. 2 when single-particle is incident on ordinary power VDMOS, electron hole pair is inspired along particle track,
Wherein hole will flow to source electrode by the Pbody areas below N+ source regions, therefore easily cause the unlatching of parasitic triode, and simple grain occurs
Son burns.
As shown in figure 3, in a kind of N-channel VDMOS device with anti-SEB abilities proposed by the present invention, N-type carrier
Concentration gradient of the impurity concentration of boot section 11 from close to grid structure to away from grid structure direction, it will be formed from close to grid
Built-in field of the structure to remote grid structure direction.When single-particle is incident produces electron hole pair, due to built-in field
In the presence of hole will move in the presence of built-in field along power line, close to the position of grid to away from grid from N-type region
Position transverse movement, then longitudinally through Pbody areas 108, finally flowed out by P+ contact zones 107.Avoid by N+ source regions 106
The Pbody areas of lower section, so as to effectively prevent the unlatching of parasitic triode, improve the ability that anti-single particle burns.
Embodiment 2
As shown in figure 4, the structure of this example is on the basis of embodiment 1, the lower section of the second conductive type semiconductor body area 108
The carrier boot section 11 of first conductive type semiconductor, in the horizontal including the n subregions with different levels of doping
111st, 112 ... 11n, n are more than or equal to 3, and the doping concentration of subregion meets：With the distance with polygate electrodes 104
Gradually increase, the doping concentration of subregion are gradually reduced.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, all those of ordinary skill in the art without departing from disclosed spirit with being completed under technological thought
All equivalent modifications or change, should by the present invention claim be covered.
Claims (4)
1. a kind of VDMOS device with anti-SEB abilities, stacks gradually metalized drain (101), the first conductive-type from top to bottom
Type Semiconductor substrate (102), the first conductive type semiconductor epitaxial layer (103), metallizing source (110)；Described first is conductive
There is the second conductive type semiconductor body area (108) respectively at left and right sides of type semiconductor epitaxial layer (103) inside upper surface；Often
Individual second conductive type semiconductor body area (108) inside upper surface has the first conductive type semiconductor source region (106) and second
Conductive type semiconductor body contact zone (107)；The first conductive type semiconductor source region (106) and the second conduction type are partly led
Body body contact zone (107) is connected with metallizing source (110)；Between second conductive type semiconductor body area (108) of both sides
With grid structure；The polygate electrodes (104) of the grid structure and the first conductive type semiconductor epitaxial layer (103),
Across gate oxide between second conductive type semiconductor body area (108) and the first conductive type semiconductor source region (106) three
(105)；Insulating medium layer (109) is filled between the polygate electrodes (104) and metallizing source (110), its feature exists
In：The bottom of the second conductive type semiconductor body area (108) has the carrier boot section of the first conductive type semiconductor
(11)；The impurity concentration non-uniform Distribution of the carrier boot section (11) of first conductive type semiconductor, point of its impurity concentration
Mode for cloth is：On the horizontal direction of device, pointed to from close to grid structure on the direction away from grid, impurity concentration gradually drops
It is low.
A kind of 2. VDMOS device with anti-SEB abilities according to claim 1, it is characterised in that：Second conduction type
The carrier boot section (11) of the first conductive type semiconductor below semiconductor body (108), have in the horizontal including n
The subregion (111,112 ... 11n) of different levels of doping, n is more than or equal to 3, and the doping concentration of subregion meets：With with
The distance of polygate electrodes (104) gradually increases, and the doping concentration of subregion is gradually reduced.
A kind of 3. VDMOS device with anti-SEB abilities according to claim 1, it is characterised in that：Described first is conductive
The material of type semiconductor either second conductive type semiconductor is body silicon, carborundum, GaAs, indium phosphide or germanium silicon
Composite one kind therein.
A kind of 4. VDMOS device with anti-SEB abilities according to claim 1, it is characterised in that：First conduction type
For p-type, the second conduction type is N-type；Or first conduction type be N-type, the second conduction type is p-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710726322.8A CN107546273B (en) | 2017-08-22 | 2017-08-22 | VDMOS device with SEB resistance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710726322.8A CN107546273B (en) | 2017-08-22 | 2017-08-22 | VDMOS device with SEB resistance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107546273A true CN107546273A (en) | 2018-01-05 |
| CN107546273B CN107546273B (en) | 2020-07-31 |
Family
ID=60957813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710726322.8A Active CN107546273B (en) | 2017-08-22 | 2017-08-22 | VDMOS device with SEB resistance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107546273B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103258A (en) * | 2018-08-21 | 2018-12-28 | 电子科技大学 | A kind of slot grid DMOS device |
| CN110854179A (en) * | 2019-11-14 | 2020-02-28 | 西安微电子技术研究所 | Radiation-reinforced silicon-based bipolar transistor structure based on self-built electric field and preparation method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515444A (en) * | 2013-09-24 | 2014-01-15 | 哈尔滨工程大学 | Groove gate power MOS device |
| CN104465778A (en) * | 2014-12-29 | 2015-03-25 | 电子科技大学 | Trench type MOS power device |
| CN104795328A (en) * | 2014-01-16 | 2015-07-22 | 北大方正集团有限公司 | Trench-type VDMOS manufacturing method and trench-type VDMOS |
-
2017
- 2017-08-22 CN CN201710726322.8A patent/CN107546273B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515444A (en) * | 2013-09-24 | 2014-01-15 | 哈尔滨工程大学 | Groove gate power MOS device |
| CN104795328A (en) * | 2014-01-16 | 2015-07-22 | 北大方正集团有限公司 | Trench-type VDMOS manufacturing method and trench-type VDMOS |
| CN104465778A (en) * | 2014-12-29 | 2015-03-25 | 电子科技大学 | Trench type MOS power device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103258A (en) * | 2018-08-21 | 2018-12-28 | 电子科技大学 | A kind of slot grid DMOS device |
| CN110854179A (en) * | 2019-11-14 | 2020-02-28 | 西安微电子技术研究所 | Radiation-reinforced silicon-based bipolar transistor structure based on self-built electric field and preparation method |
| CN110854179B (en) * | 2019-11-14 | 2023-04-25 | 西安微电子技术研究所 | Radiation-reinforced silicon-based bipolar transistor structure based on self-built electric field and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107546273B (en) | 2020-07-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107302025B (en) | A kind of VDMOS device with anti-single particle effect | |
| CN105118862B (en) | A kind of VDMOS device with anti-single particle effect | |
| CN103413824B (en) | A kind of RC-LIGBT device and preparation method thereof | |
| US7602045B2 (en) | Semiconductor device and inverter device using the same | |
| CN108183130B (en) | Double-gate carrier storage IGBT device with P-type buried layer | |
| CN102201406B (en) | Bipolar CMOS DMOS (BCD) integrated device based on N type extension layer and manufacture method thereof | |
| CN102194818B (en) | P-type epitaxial layer-based binary coded decimal (BCD) integrated device and manufacturing method thereof | |
| CN103337498B (en) | BCD semiconductor device and manufacturing method thereof | |
| CN105185826B (en) | A kind of transverse direction RC-IGBT device | |
| CN107331707A (en) | VDMOS device with anti-single particle effect | |
| CN110310983A (en) | A kind of hyperconjugation VDMOS device | |
| CN110416285A (en) | A kind of superjunction power DMOS device | |
| CN110504310A (en) | A kind of RET IGBT and preparation method thereof with automatic biasing PMOS | |
| CN110473917B (en) | Transverse IGBT and manufacturing method thereof | |
| CN107546273A (en) | A kind of VDMOS device with anti-SEB abilities | |
| CN104078509A (en) | Power MOS device with single-particle burnout resistance | |
| CN107516679A (en) | A kind of deep trouth superjunction DMOS devices | |
| CN114725206B (en) | SiVDMOSFET device based on low dielectric constant medium | |
| CN109920840A (en) | One kind having L-type SiO2The compound RC-LIGBT device of separation layer | |
| US10546951B2 (en) | Trench MOS device with improved single event burn-out endurance | |
| CN103531586B (en) | A kind of power semiconductor and manufacture method thereof | |
| Yang et al. | Investigation on current crowding effect in IGBTs | |
| CN111244157B (en) | Lateral semiconductor device and manufacturing method thereof | |
| TWI503972B (en) | Lateral insulated gate bipolar transistor and manufacturing method thereof | |
| CN107425071B (en) | A kind of VDMOS device with anti-single particle radiation ability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |