CN109103258A - A kind of slot grid DMOS device - Google Patents
A kind of slot grid DMOS device Download PDFInfo
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- CN109103258A CN109103258A CN201810954071.3A CN201810954071A CN109103258A CN 109103258 A CN109103258 A CN 109103258A CN 201810954071 A CN201810954071 A CN 201810954071A CN 109103258 A CN109103258 A CN 109103258A
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- type semiconductor
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- doping
- contact zone
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- 239000004065 semiconductor Substances 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 13
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 230000024241 parasitism Effects 0.000 abstract description 4
- 230000005684 electric field Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 230000001939 inductive effect Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
Abstract
A kind of slot grid DMOS device, belongs to power semiconductor technologies field.Device of the present invention introduces the electric current guide layer of heavy doping on the basis of traditional slot grid DMOS device architecture, at the top of drift region；And the both ends of metallizing source are further extended down into the second conductive type semiconductor body area and form groove structure；So that contact zone is located at the channel bottom at metallizing source both ends and close to electric current guide layer.It is higher that the doping concentration of one side electric current guide layer compares contact zone, to will form the lower current path of conducting resistance, the electric field strength of another aspect body area and electric current guide layer intersection contact interface is bigger and is easier to puncture, to which the avalanche breakdown point of slot grid DMOS device be fixed in device reversed avalanche breakdown, form the avalanche current path far from the parasitism base area BJT, and then the unlatching of parasitic BJT is effectively avoided, and then improve the anti-UIS failure ability of slot grid DMOS device.
Description
Technical field
The invention belongs to power semiconductor technologies fields, are related to a kind of slot grid DMOS device.
Background technique
Power semiconductor is to realize electric energy conversion and control essential core devices.Power MOSFET is opened because of it
The advantages that speed is fast, loss is small, input impedance is high, driving power is small, frequency characteristic is good is closed, becomes and is most widely used at present
Power device.The system application requirement of power MOSFET its with lower power be lost while, also answered under high electric stress
When with higher reliability.Therefore reliability is for the system of power MOSFET using most important.Studies have shown that device exists
It is failure in dynamic process, compared with its failure in static process, crash rate is high, and failure mechanism is also more complicated.
Rather than the switching process (Unclamped Inductive Switching, UIS) clamped under inductive load is typically considered function
The most extreme electric stress situation that rate DMOS can face in the application.Because there are non-clamp inductive loads in system circuit
When, the energy being stored in inductance under on state can all be discharged by DMOS when off, and high voltage and high current will simultaneously
It is applied on power DMOS, easily causes component failure.Therefore, therefore the anti-UIS failure ability of device is commonly used for evaluating function
The reliability of rate DMOS, and UIS tolerance is to measure the important parameter of the anti-UIS failure ability of power DMOS.
Generally believing the unlatching of parasitic BJT (Bipolar Junction Transistor, bipolar junction transistor) in the industry is
Cause the one of the major reasons of power MOSFET failure during UIS.The failure of UIS is typically considered device " active " mould
Formula, this is because the parasitic BJT between source and drain can be connected when UIS snowslide occurs, intracorporal high current will be flowed through after conducting to be made
Device is brought rapidly up, and finally makes device failure.For thinking N-channel power DMOS device, as shown in Figure 1, its N+ source region conduct
The emitter region of parasitic BJT, the drift region N- constitutes the collector area of parasitism BJT, and the area P-body is as base area.When above-mentioned power
When avalanche breakdown occurs for DMOS device, avalanche current reaches the contact zone P+ via the area P-body below N+ source region, and snowslide is electric
When stream flows through the base area of parasitic BJT, since there are resistance will necessarily generate forward voltage drop in area P-body itself, posted when pressure drop is greater than
When the forward conduction voltage drop of raw BJT, the emitter positively biased of parasitic BJT amplifies workspace into forward direction, amplifies avalanche current, make
It is burnt at the heat of device.
Currently, the method for the anti-UIS failure ability to improve DMOS device is mainly to pass through to reduce parasitism BJT's in the industry
Base resistance inhibits its unlatching.However, this method can not prevent the unlatching of parasitic BJT, it just not can avoid snowslide yet and hit
Wear caused device UIS active failure mode；In addition, by the injection of the boron of high-energy or deep diffusion come can only be certain
Reduce base resistance in limit, can not infinitely reduce the base resistance of parasitic BJT, otherwise will increase the threshold voltage of device.
Summary of the invention
In view of described above, the present invention is provided for existing to improve defect present in the anti-UIS failure ability of device
A kind of slot grid DMOS device and effectivelying prevent parasitic BJT to open with high UIS tolerance.
Technical solution of the present invention is as follows:
A kind of slot grid DMOS device, including metalized drain 1, the first conductive type semiconductor doped substrate 2, first are conductive
Type semiconductor doped drift region 3, slot grid structure, the second conductive type semiconductor body area 6, the doping of the first conductive type semiconductor
Source region 7, the second conductive type semiconductor doping contact zone 8 and metallizing source 10；
Metalized drain 1 is located at the back side of the first conductive type semiconductor doped substrate 2；First conductive type semiconductor is mixed
Miscellaneous drift region 3 is located at the front of the first conductive type semiconductor doped substrate 2；Second conductive type semiconductor body area 6 is located at the
The top layer two sides of one conductive type semiconductor doped drift region 3；Slot grid structure is located at the doping drift of the first conductive type semiconductor
It 3 top layer of area and is clipped between the second conductive type semiconductor body area 6 of two sides；In the second conductive type semiconductor body area 6
Contact zone 8 is adulterated with mutually independent first conductive type semiconductor doping source region 7 and the second conductive type semiconductor, and
First conductive type semiconductor doping source region 7 is located at close to the side of slot grid structure；The slot grid structure and the first conduction type
Semiconductor doping source region 7 and the contact of the second conductive type semiconductor body area 6；Metallizing source 10 is located at device surface, and gold
Categoryization source electrode 10 is covered on the first conductive type semiconductor doping source region 7, the second conductive type semiconductor doping contact zone 8 and slot
The surface of grid structure；It is characterized by:
Also there is the first conductive type semiconductor to adulterate electric current guide layer 9 in the slot grid DMOS device；First conductive-type
Type semiconductor doping electric current guide layer 9 is located at the underface of the second conductive type semiconductor doping contact zone 8 and leads close to second
Electric type semiconductor doping contact zone 8 is arranged；The doping concentration that first conductive type semiconductor adulterates electric current guide layer 9 is greater than the
The doping concentration of two conductive type semiconductors doping contact zone 8；First conductive type semiconductor adulterates electric current guide layer 9 along device
It is laterally extended depth and is laterally extended depth along device less than the second conductive type semiconductor doping contact zone 8.
The present invention is to introduce the electric current of heavy doping at the top of drift region on the basis of traditional slot grid DMOS device architecture
Guide layer, on the one hand since to compare contact zone higher for the doping concentration of electric current guide layer, so that heavy doping electric current guide layer
The lower current path of conducting resistance is formed, on the other hand due to body area and heavy doping electric current guide layer intersection contact interface
Electric field strength is bigger, it is easier to punctures, factors above can guide avalanche current to flow through heavy doping electric current guide layer, thus
The avalanche breakdown point of slot grid DMOS device is fixed in device reversed avalanche breakdown, forms the separate parasitism base area BJT
Avalanche current path, and then the unlatching of parasitic BJT is effectively avoided, and then it is negative in non-clamp inductance to reach raising slot grid DMOS device
Carry reliability, that is, anti-UIS failure ability in application.
Further, the both ends of the metallizing source 10 extend down into 6 shape of the second conductive type semiconductor body area
At groove structure；Second conductive type semiconductor doping contact zone 8 is located at the channel bottom at 10 both ends of metallizing source.This
The path of avalanche breakdown electric current is shortened in invention by using undercut groove profile metallizing source, reduces the base area electricity of parasitic BJT
Resistance.
Further, the present invention in slot grid structure include: groove profile gate electrode 4 and be located at 4 surrounding of groove profile gate electrode and bottom surface
Gate dielectric layer 5, the upper surface of the groove profile gate electrode 4 and the upper surface of gate dielectric layer 5 are contacted with metallizing source 10.
Further, the first conductive type semiconductor is doped to N-type semiconductor, second conduction type half in the present invention
When conductor is doped to P-type semiconductor, the slot grid DMOS device is N-channel slot grid DMOS device.
Further, the first conductive type semiconductor is doped to P-type semiconductor, second conduction type half in the present invention
When conductor is doped to N-type semiconductor, the slot grid DMOS device is P-channel slot grid DMOS device.
Further, the material of slot grid DMOS device of the present invention can be silicon, silicon carbide, GaAs, indium phosphide or germanium silicon
Semiconductor material.
Compared with prior art, the beneficial effects of the present invention are: slot grid DMOS device provided by the invention can be effectively prevent
The unlatching of parasitic BJT improves the UIS tolerance of slot grid DMOS device, so that slot grid DMOS device is in non-clamp inductive load
Reliability in improves.
Detailed description of the invention
Fig. 1 is the schematic diagram of regular troughs grid DMOS device architecture and its avalanche breakdown current path.
Fig. 2 is a kind of structural schematic diagram for slot grid DMOS device that the embodiment of the present invention 1 provides.
Fig. 3 is a kind of schematic diagram of the avalanche breakdown current path for slot grid DMOS device that the embodiment of the present invention 1 provides.
Fig. 4 is a kind of structural schematic diagram for slot grid DMOS device that the embodiment of the present invention 2 provides.
In figure, 1 is metalized drain, and 2 be N+ substrate, and 3 be the drift region N-, and 4 gate electrodes, 5 be gate dielectric layer, and 6 be p-type body
Area, 7 be N+ source region, and 8 be the contact zone P+, and 9 be N+ electric current guide layer, and 10 be metallizing source.
Specific embodiment
Illustrate implementation of the invention below by way of specific embodiment, those skilled in the art can be by this disclosure
Content understand other advantages and effect of the invention.The present invention can also be embodied or practiced by other different modes,
Without departing from the spirit of the present invention the various details in this specification can also be carried out various based on different viewpoints and application
Modifications and changes should belong in the protection scope that the present invention covers.
Embodiment 1:
The present embodiment provides a kind of slot grid DMOS devices, as shown in Fig. 2, including metalized drain 1, N+ substrate 2, N- drift
Area 3, slot grid structure, the second conductive type semiconductor body area 6, N+ source region 7, the contact zone P+ 8 and metallizing source 10；
Metalized drain 1 is located at the back side of N+ substrate 2；The drift region N- 3 is located at the front of N+ substrate 2；Second conduction type
Semiconductor body 6 is located at the top layer two sides of the drift region N- 3；Slot grid structure is located at 3 top layer of the drift region N- and is clipped in the second of two sides
Between conductive type semiconductor body area 6, the slot grid structure include groove profile gate electrode 4 and be located at 4 surrounding of groove profile gate electrode
With the gate dielectric layer of bottom surface；There is mutually independent N+ source region 7 and the contact zone P+ in the second conductive type semiconductor body area 6
8, and N+ source region 7 is located at close to the side of slot grid structure；The slot grid structure and N+ source region 7 and the second conductive type semiconductor
Body area 6 contacts；Metallizing source 10 is located at device surface, and metallizing source 10 is covered on N+ source region 7,8 and of the contact zone P+
The surface of slot grid structure；It is characterized by:
The both ends of the metallizing source 10 extend down into the second conductive type semiconductor body area 6 and form groove knot
Structure, the contact zone P+ 8 are located at the channel bottom setting at 10 both ends of metallizing source；Also there is N+ electric current guide layer in the drift region N- 3
9；N+ electric current guide layer 9 is located at the underface of the contact zone P+ 8, the following table of upper surface and the second conductive type semiconductor body area 6
Face contact；The doping concentration of N+ electric current guide layer 9 is greater than the doping concentration of the contact zone P+ 8；N+ electric current guide layer 9 is along device transverse direction
Extend depth and is laterally extended depth along device less than the contact zone P+ 8.
Below with reference to by taking N-channel slot grid DMOS device as an example, in conjunction with Fig. 3 working principle that the present invention will be described in detail, ability
Field technique personnel on this basis can apparent P-channel slot grid DMOS device working principle, therefore details are not described herein.This
Details are as follows for invention working principle:
Under forward conduction mode, the electrode connection mode of the present embodiment device are as follows: metallizing source 10 connects low potential, metal
Change drain electrode 1 and connect high potential, groove profile gate electrode 4 connects high potential.When the positive bias-voltage for being applied to groove profile gate electrode 4 reaches threshold voltage
When, inversion channel is formed close to the side wall of groove profile gate electrode 4 in the area PXing Ti 6, and how sub- electronics is from N+ source region 7 via the area PXing Ti 6
In inversion channel injection the drift region N- 3 in, formed forward conduction electric current；
Under reverse blocking mode, the electrode connection mode of the present embodiment device are as follows: metallizing source 10 connects low potential, metal
Change drain electrode 1 and connect high potential, groove profile gate electrode 4 connects low potential, and the current potential in the area PXing Ti 6 is identical as the current potential of metallizing source 10.When
When device is in blocking state, the PN junction that the drift region the area PXing Ti 6 and N- 3 is formed exhausts, and is mainly undertaken reversely by the drift region N- 3
Pressure resistance.
The slot grid DMOS device that the present embodiment 1 provides, during UIS, if avalanche breakdown occurs for device, due to N+ electricity
Flowing guide layer 9 has lower conducting resistance, and carrier always selects the smallest path of resistance, while doping concentration is higher
N+ electric current guide layer 9 is bigger with the electric field strength at the area PXing Ti 6, thus is easier to puncture, therefore, avalanche breakdown point energy
It is enough fixed at N+ electric current guide layer 9 and the contact interface of the boundary of the area PXing Ti 6, while being contracted using groove profile metallizing source
The path of short avalanche breakdown electric current, guidance avalanche current is via the area PXing Ti 6 of the lower section of heavily doped P-type contact zone 8 from heavy doping P
Type contact zone 8 flows away, without by the area PXing Ti 6 below N+ source region, guided rear avalanche current path such as Fig. 3 formed
It is shown.It will thus be seen that the present invention, which provides slot grid DMOS device, can prevent the unlatching of parasitic BJT, to improve the anti-of device
UIS failure ability.
Embodiment 2:
The present embodiment provides a kind of slot grid DMOS devices, as shown in figure 4, the present embodiment is compared to the difference of embodiment 1,
The N+ electric current guide layer 9 is located in the second conductive type semiconductor body area 6, and the upper surface of lower surface and the drift region N- 3 connects
Touching.
It needs to specialize, the material of slot grid DMOS device provided by the invention can be silicon, silicon carbide, arsenic
Gallium, indium phosphide or germanium silicon semiconductor material.
Specific implementation of the invention is elaborated in conjunction with attached drawing above, above embodiment is only schematic
, and not restrictive, the invention is not limited to above-mentioned specific embodiments.Those of ordinary skill in the art are of the invention
Under enlightenment, makes and do not depart from all shape changeables of present inventive concept and claimed range and should all belong to guarantor of the invention
Shield.
Claims (6)
1. a kind of slot grid DMOS device, including metalized drain (1), the first conductive type semiconductor doped substrate (2), first lead
Electric type semiconductor doped drift region (3), slot grid structure, the second conductive type semiconductor body area (6), the first conduction type are partly led
Body doping source region (7), the second conductive type semiconductor doping contact zone (8) and metallizing source (10)；
Metalized drain (1) is located at the back side of the first conductive type semiconductor doped substrate (2)；First conductive type semiconductor is mixed
Miscellaneous drift region (3) is located at the front of the first conductive type semiconductor doped substrate (2)；Second conductive type semiconductor body area (6)
Positioned at the top layer two sides of the first conductive type semiconductor doped drift region (3)；Slot grid structure is located at the first conductive type semiconductor
It doped drift region (3) top layer and is clipped between the second conductive type semiconductor body area (6) of two sides；Second conduction type half
There is mutually independent first conductive type semiconductor doping source region (7) and the second conductive type semiconductor in conductor body area (6)
It adulterates contact zone (8), and the first conductive type semiconductor doping source region (7) is located at close to the side of slot grid structure；The slot
Grid structure is contacted with the first conductive type semiconductor doping source region (7) and the second conductive type semiconductor body area (6)；Metallization source
Pole (10) is located at device surface, and metallizing source (10) is covered on the first conductive type semiconductor doping source region (7), second
The surface of conductive type semiconductor doping contact zone (8) and slot grid structure；It is characterized by:
Also there is the first conductive type semiconductor doping electric current guide layer (9) in the slot grid DMOS device；First conduction type
Semiconductor doping electric current guide layer (9) is located at the underface of the second conductive type semiconductor doping contact zone (8) and close to second
Conductive type semiconductor adulterates contact zone (8) setting；First conductive type semiconductor adulterates the doping concentration of electric current guide layer (9)
Greater than the doping concentration of the second conductive type semiconductor doping contact zone (8)；First conductive type semiconductor adulterates electric current guidance
Layer (9) is laterally extended depth along device and is laterally extended depth along device less than the second conductive type semiconductor doping contact zone (8).
2. a kind of slot grid DMOS device according to claim 1, it is characterised in that: first conductive type semiconductor is mixed
Miscellaneous is N-type semiconductor, and second conductive type semiconductor is doped to P-type semiconductor.
3. a kind of slot grid DMOS device according to claim 1, it is characterised in that: first conductive type semiconductor is mixed
Miscellaneous is P-type semiconductor, and second conductive type semiconductor is doped to N-type semiconductor.
4. a kind of slot grid DMOS device according to claim 2 or 3, it is characterised in that: the metallizing source (10)
Both ends extend down into the second conductive type semiconductor body area (6) and form groove structure；Second conductive type semiconductor
Doping contact zone (8) is located at the channel bottom at metallizing source (10) both ends.
5. a kind of slot grid DMOS device according to claim 2 or 3, it is characterised in that: the slot grid structure includes: grid electricity
Pole (4) and the gate dielectric layer (5) for being located at gate electrode (4) surrounding and bottom surface.
6. a kind of slot grid DMOS device according to claim 2 or 3, it is characterised in that: the material of the slot grid DMOS device
Material is silicon, silicon carbide, GaAs, indium phosphide or germanium silicon semiconductor material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810954071.3A CN109103258A (en) | 2018-08-21 | 2018-08-21 | A kind of slot grid DMOS device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810954071.3A CN109103258A (en) | 2018-08-21 | 2018-08-21 | A kind of slot grid DMOS device |
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| CN109103258A true CN109103258A (en) | 2018-12-28 |
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| CN201810954071.3A Pending CN109103258A (en) | 2018-08-21 | 2018-08-21 | A kind of slot grid DMOS device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4931846A (en) * | 1987-05-29 | 1990-06-05 | Nissan Motor Company, Limited | Vertical MOSFET having voltage regulator diode at shallower subsurface position |
| CN105679819A (en) * | 2016-03-18 | 2016-06-15 | 电子科技大学 | Reverse conducting MOS gate-controlled thyristor and fabrication method thereof |
| CN107546273A (en) * | 2017-08-22 | 2018-01-05 | 电子科技大学 | A kind of VDMOS device with anti-SEB abilities |
-
2018
- 2018-08-21 CN CN201810954071.3A patent/CN109103258A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4931846A (en) * | 1987-05-29 | 1990-06-05 | Nissan Motor Company, Limited | Vertical MOSFET having voltage regulator diode at shallower subsurface position |
| CN105679819A (en) * | 2016-03-18 | 2016-06-15 | 电子科技大学 | Reverse conducting MOS gate-controlled thyristor and fabrication method thereof |
| CN107546273A (en) * | 2017-08-22 | 2018-01-05 | 电子科技大学 | A kind of VDMOS device with anti-SEB abilities |
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Application publication date: 20181228 |