CN107534055A - 功率晶体管的具有可变条带宽度的稀释漂移层 - Google Patents

功率晶体管的具有可变条带宽度的稀释漂移层 Download PDF

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CN107534055A
CN107534055A CN201680008805.8A CN201680008805A CN107534055A CN 107534055 A CN107534055 A CN 107534055A CN 201680008805 A CN201680008805 A CN 201680008805A CN 107534055 A CN107534055 A CN 107534055A
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张永熙
萨米尔·P·佩恩达尔卡尔
斯科特·G·巴尔斯特
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Abstract

在所描述实例中，一种多指横向高电压晶体管MFLHVT(100)包含：衬底(105)，其被掺杂成第一掺杂剂类型；井(102)，其被掺杂成第二掺杂剂类型；及埋入漂移层BDL(132)，其被掺杂成第一类型、具有包含稀释条带的稀释BDL部分DBDL(132a)。被掺杂成第二类型的半导体表面(138)在BDL上。电介质隔离区(162)具有界定在第一间隙区(第一深沟)中的第一作用区域及在第二间隙区(第二深沟)中的第二作用区域的间隙。漏极包含与在第一深沟中的源极指互相交叉的在第二深沟中的漏极指，所述源极指及所述漏极指各自被掺杂成第二掺杂剂类型。DBDL位于在第一深沟与第二深沟之间与漏极指尖及/或源极指尖相关联的指尖漂移区内。栅极堆叠在半导体表面上位于源极与漏极之间。稀释条带具有在其相应位置处随漂移长度单调地增加的条带宽度。

Description

功率晶体管的具有可变条带宽度的稀释漂移层
技术领域
本发明涉及具有稀释漂移层的横向高电压金属氧化物半导体(MOS)功率晶体管，包含LDMOS及DEMOS晶体管。
背景技术
现代数字超大规模集成(VLSI)电路通常以大约2.5伏特或低于2.5伏特的供应电压操作。然而，特定集成电路(IC)需要以更高电压操作的额外芯片上电路。实例性电路是具有各种芯片外系统组件的输入/输出(IO)接口电路，例如功率管理开关、调节传感器信号的模拟输入电路或者用于扬声器或其它致动器的输出模拟驱动功能。
此问题的一种解决方案是使用多个不同栅极氧化物厚度且在同一IC芯片上构建低电压晶体管及高电压晶体管两者。此方法增加过程复杂度及成本。替代解决方案是使用在(n型装置的)漏极与栅极之间具有轻掺杂n型间隙以使得能够使用更高漏极到源极电压的横向不对称源极及漏极MOS晶体管，例如横向扩散金属氧化物半导体(LDMOS)或漏极延伸MOS(DEMOS)，其具有能够以更高电压(与常规对称MOS晶体管相比较)操作的漏极结构。
在LDMOS晶体管中，轻掺杂横向扩散漏极区构造于重掺杂漏极触点与晶体管沟道区之间。如LDMOS名称所暗示，横向电流形成于漏极与源极之间。耗尽区在此轻掺杂横向扩散区中形成，从而产生漏极触点与晶体管栅极之间的电压降。在进行恰当设计的情况下，在漏极触点与栅极电介质之间可具有足以允许针对高电压使用低栅极电压晶体管作为开关的电压降。
一些横向功率晶体管包含为经减小表面电场区的“RESURF”区。出于此专利申请案的目的，术语“RESURF”是指减小邻近表面半导体区中的电场的材料。举例来说，RESURF区可为具有与邻近半导体区(或层)相反的导电类型的埋入半导体区(或层)。在阿佩尔(Appels)等人的“薄层高电压装置(Thin Layer High Voltage Devices)”(飞利浦杂志，Res.35，1-13，1980年)中描述RESURF结构。横向功率晶体管的RESURF区一般称为埋入漂移区。
为提高横向功率晶体管的击穿电压，可在晶体管的一端处的漂移区处使用稀释埋入漂移层，所述稀释埋入漂移层可通过掩蔽植入(其达成植入由掩蔽(非所植入)条带分开的稀释条带)形成。接下来为一或多个高温退火过程，此导致掺杂剂从所植入条带扩散到非所植入条带中从而形成与较不重掺杂条带交替的较重掺杂条带。
DEMOS或LDMOS晶体管可具有：多指布局，其具有一般彼此互相交叉的多个源极及漏极指；或跑道布局，其为(本质上)具有封闭源极或封闭漏极的单指设计。稀释埋入漂移层设计的稀释埋入漂移层一般设定横向功率晶体管的漏极到源极击穿电压(BVDSS)，其中跑道布局一般由于较小结曲率而提供接近理想(平面)结击穿电压的较高击穿电压(与在指尖区处具有较高曲率的多指布局的较低BVDSS相比较)。指尖区对应于从指尖的线性(非弯曲)区延伸的指状件的弯曲远端。多指横向功率晶体管(例如，DEMOS或LDMOS晶体管)的优点包含经减少寄生效应以及改变宽度(W)、长度(L)、指状件数目及触点数目(此帮助加快晶体管布局过程的速度)的能力。
发明内容
在所描述实例中，一种多指横向高电压晶体管(MFLHVT)包含：衬底，其被掺杂成第一掺杂剂类型；井，其被掺杂成第二掺杂剂类型；及埋入漂移层(BDL)，其被掺杂成第一类型、具有包含稀释条带的稀释BDL部分(DBDL)。被掺杂成所述第二类型的半导体表面在所述BDL上。电介质隔离区具有界定在第一间隙区(第一深沟)中的第一作用区域及在第二间隙区(第二深沟)中的第二作用区域的间隙。漏极包含与在所述第一深沟中的源极指互相交叉的在所述第二深沟中的漏极指，所述源极指及所述漏极指各自被掺杂成所述第二掺杂剂类型。所述DBDL位于在所述第一深沟与所述第二深沟之间与漏极指尖及/或源极指尖相关联的指尖漂移区内。栅极堆叠位于所述半导体表面上在源极与漏极之间。所述稀释条带具有在其相应位置处随漂移长度单调地增加的条带宽度。
附图说明
图1A是根据实例性实施例的具有n沟道MFLHVT的实例性IC的横截面图，所述n沟道MFLHVT具有实例性DBDL部分及多个水平电流沟道。
图1B是图1A的IC的俯视图。
图2A描绘根据实例性实施例的所揭示MFLHVT的一部分，其展示在分别具有漏极指尖的第一漏极指与第二漏极指之间的具有源极指尖的源极指。
图2B是根据实例性实施例的MFLHVT的DBDL在具有MIOD稀释条带宽度设计的BDL植入之后的俯视图描绘，其中稀释条带对应于具有基于FDR中的所揭示比例缩放而设计的十五个(15)实例性稀释条带的所植入区。
图3A及3B分别展示根据实例性实施例的包含指尖及指尖部分的1/2的指状件，其用于展示所揭示DBDL设计中的参数。
图4展示比较的NLDMOS BVDSS数据，包含来自具有含有MIOD的所揭示DBDL设计的所揭示多指NLDMOS装置(例如图2B中所展示)及具有含有固定条带保险尺寸的常规DBDL的控制跑道NLDMOS装置的数据。
具体实施方式
各图未必按比例绘制。在本发明中，一些行为或事件可以不同次序发生及/或与其它行为或事件同时发生，且一些所图解说明行为或事件是任选的。
在实例性实施例中，多指横向高电压晶体管(MFLHVT)包含漏极延伸MOS(DEMOS)及横向扩散MOS(LDMOS)晶体管，其具有在指状件的源极指尖与漏极指尖之间的常规稀释埋入漂移层(在本文中称为指尖漂移区“FDR”)。在此些实施例中，FDR的稀释条带宽度(例如，在n沟道金属氧化物半导体(NMOS)的漏极端处)的固定保险设计尺寸(比例缩放例如200％)的使用可限制这些晶体管的漏极到源极击穿电压(BVDSS)。此经减小BVDSS是归因于FDR处(尤其在最高结曲率部分处)的显著曲率诱发的电场拥挤，所述电场拥挤已由检测且局部化特定集成电路(IC)故障的发射显微镜成像(EMMI)验证。举例来说，多指LDMOS的BVDSS可处于～700V，与具有～800V的BVDSS(其由于大端盖半径而为理想BVDSS)的其它等效跑道版本相比低大约100V。
而且，实例性实施例在MFLHVT的FDR中提供基于计算(公式)的稀释埋入漂移层(DBDL)设计，此针对沿着DBDL的至少一部分的稀释条带宽度提供单调地增加的保险设计尺寸(MIOD)，所述DBDL在与源极指尖及/或漏极指尖相关联的FDR内。稀释条带宽度对应于所植入埋入漂移层区。已发现所揭示DBDL设计通过减轻FDR的最高结曲率部分中的电场拥挤而改进此些晶体管的BVDSS。所揭示集成电路(IC)可组合p沟道MOS(PMOS)MFLHVT的n型稀释与NMOS MFLHVT的p型稀释两者。
实例性实施例包含在FDR中具有DBDL设计(具有MIOD)的MFLHVT，已发现DBDL设计通过减轻电场拥挤而改进BVDSS。所揭示MFLHVT还通过具有源极与漏极之间的多个电流沟道而为经减小区域提供高电压下的高电流。由于在接通所揭示晶体管时所揭示MFLHVT中的电流可流动穿过多个沟道，因此所揭示晶体管给经减小区域提供高电流。多个电流沟道特征显著减小包含LDMOS或DEMOS晶体管的MFLHVT所需要的区域，藉此显著降低成本。
在此说明中，术语“电流沟道”是指电流流动穿过的半导体衬底的区。一个电流沟道通过相反掺杂剂类型的扩散区与另一电流沟道隔离。在相反掺杂剂类型的扩散区的端处的一个电流沟道可短接到另一电流沟道，所述扩散区将两个电流沟道分开。
如图1A的横截面图中所展示，实例性IC 150具有含有p型BDL 132的n沟道MFLHVT(MFLHVT 100)，p型BDL 132在邻近于相互交叉源极指与漏极指之间的指尖的FDR中包含在接近共同漏极218的漏极端处的DBDL部分132a，其中多个水平电流沟道以虚线展示为上部电流沟道226及下部电流沟道228。指尖区对应于从指尖的线性(非弯曲)区延伸的指状件的弯曲远端。同一IC(例如IC 150或具有n型稀释的另一IC)上的p沟道MFLHVT可通过相对于MFLHVT 100的反调装置来实现。
图1B展示IC 150的俯视图。参考图1B，上部电流沟道226在半导体表面138(被掺杂成n型)中在顶部p型表面层174与BDL 132(其为p型)之间，而下部电流沟道228在n井102中在BDL 132与衬底105之间。衬底105被掺杂成第一掺杂剂类型(为p型)，且半导体表面138以第二掺杂剂类型掺杂(为n型)。MFLHVT的垂直层堆叠具有pnpnp结构，其提供4个经减小表面电场(RESURF)区。然而，由于顶部p型表面层174(图1A)为任选的，因此可移除(在过程中跳过)顶部p型表面层174以提供具有pnpn结构(其提供3个RESURF区)的所揭示MFLHVT。
衬底105可包含硅、硅锗或其它半导体材料。一个特定布置是硅衬底105上的外延硅/锗(SiGe)半导体表面。
对称S/D核心逻辑PMOS晶体管50具有n井146、源极/漏极扩散区224及晶体管栅极202。对称S/D核心逻辑NMOS晶体管60具有p型外延层130、源极/漏极扩散区214及晶体管栅极204。MFLHVT 100具有两个栅极电极206及208以及两者均在其共同漏极(漏极)218与共同源极(源极)216之间的上部电流沟道226及下部电流沟道228。如果期望，那么可提供两个以上水平电流路径。栅极电极206及208可包含多晶硅，或替代地金属。
当接通包含MFLHVT 100的栅极电极206的栅极时，电流流动穿过在顶部p型表面层174与BDL 132之间的上部电流沟道226。当接通包含MFLHVT 100的栅极电极208的栅极时，电流流动穿过上部电流沟道226及下部电流沟道228。然而，对于功率切换应用，栅极电极206及208可短接到一起以最大化晶体管接通状态电流。尽管在图1A中展示两个栅极，但单个栅极可支持上部电流沟道226及下部电流沟道228两者，使得所揭示MFLHVT仅需要一个栅极。
电介质隔离区162至少部分地在半导体表面中展示为可替代地为场氧化(FOX)的沟槽隔离(例如，浅沟槽隔离(STI))，其在IC 150的半导体表面138、p型外延层130及n井146上方包含有界定以下各项的在电介质中的间隙：在第一电介质间隙区(在下文为源极深沟)110中的第一作用区域，其中形成共同源极216；及在第二电介质间隙区(在下文为漏极深沟)115中的第二作用区域，其中形成漏极218。电流沟道226、228两者均展示为共用源极216及漏极218。电流沟道226、228为锥形的而且在共同漏极218附近更窄且更轻掺杂(与其在共同源极216附近的掺杂及宽度相比较)。
当关断包含栅极电极206及208的栅极两者且将高电压施加到共同漏极218时，扩展耗尽区形成于上部电流沟道226(其为n型)与p型表面层174及BDL 132之间，且扩展耗尽区形成于下部电流沟道228(其为n型)与BDL 132及衬底105之间，使得上部电流沟道226及下部电流沟道228停止提供从共同源极216到共同漏极218的连续电流路径。跨越这些耗尽区具有充足电压降，使得包含栅极电极206及208的晶体管栅极堆叠可使用作为逻辑晶体管50及60的相同低电压栅极电介质来切换高电压。
图2A描绘所揭示MFLHVT的部分200，其展示相互交叉指尖布置，包含在以下各项之间的具有源极指尖216a’的源极指216a：第一漏极指218a，其具有漏极指尖218a’；及第二漏极指218b，其具有漏极指尖218b’。MFLHVT将具有所展示的相互交叉指状件布置的多个重复。源极指尖216a’与在漏极深沟115的外边缘与源极深沟110外边缘之间(包含图1A的DBDL部分132a)的源极FDR 210相关联。类似地，在漏极深沟115的外边缘与源极深沟110的外边缘之间的相应漏极FDR 215与漏极指尖218a’及218b’(其还可包含所揭示DBDL部分，例如DBDL 132a(图1A))相关联。与在接近源极216的侧上的较小稀释程度(等同于图2A中的不可辨别稀释条带)相比较，稀释在接近漏极218的侧上是较重的(相当于图2A中具有较近间距的可辨别稀释条带)。
图2B是根据实例性实施例的源极FDR 210(图2A)的俯视图描绘250，其展示在具有对应于所植入区(其大小在其位置处随漂移长度(DL)单调地增加)的DBDL条带宽度的BDL植入之后的实例性DBDL部分132a。在源极指尖216a’的开始处的指尖中心经识别且展示为285，线性漂移区290经展示为在展示为295的水平虚线边界上面，且源极FDR 210经展示为在水平虚线295下面。
如本文中所使用，DL(其为在图2B中展示为L的常数)定义为线性漂移区中的漏极深沟115与源极深沟110之间的最小间距，所述最小间距为源极深沟110与漏极深沟115之间(从源极深沟边缘110’到漏极深沟边缘115’)的最短距离。在源极FDR 210中，DL定义为在源极FDR 210中的特定角度θ(参见展示θ的图3A及3B)下源极深沟边缘110’与漏极深沟边缘115’之间的距离。DBDL部分132a包含十五个(15)实例性稀释DBDL条带，包含与在BDL植入期间掩蔽的非所植入条带132a’1、132a’2及132a’3(其为非所植入区)交替的将为BDL所植入区的条带132a1、132a2及132a3。
参数Lf(图2B)为稀释条带的保险设计尺寸，其中Lf为判定源极FDR 210的总体大小的常规固定布局设计的固定参数(常数)，且Lθ为设定条带宽度的FDR中的变量(参见下文所描述的图3B中所展示的Lθ)。针对图2B中所展示的特定布局，Lf为固定参数，而Lθ随介于从0度到90度或180度的范围内的θ而变。参数L(图2B)为从源极深沟110的边缘到指状件的中心的距离(参见下文所描述的图3B中所展示的L)。如实例中所描述，对于具有DBDL部分设计(例如图2B中所展示)的n沟道MFLHVT，已发现多指布局与跑道(单指)布局之间的BVDSS差从大约100V减小到小于40V。
当MFLHVT包含NMOS装置时，针对距指尖中心285的恒定距离，DBDL 132a的相应条带宽度在图2B中经展示为随相对于源极FDR 210与线性漂移区290的水平虚线边界295的角度θ的增加而增加，从而在90度下具有最大宽度。然而，随θ而变的条带宽度改变针对与漏极指尖相关联的FDR(例如，图2A中所展示的漏极FDR 215)为相反的，其中DBDL的相应条带宽度将替代地随角度θ的增加而减小。此不对称性反映例如NMOS MFLHVT的线性区中的所揭示稀释概念，其中使p型DBDL 132a在接近漏极218的漏极侧上稀释更多，而使p型DBDL 132a在接近源极216的源极侧上稀释更少，如图1A中所展示，如上文所描述。
而且，对于固定θ，随着距指尖中心285的距离增加，图2B中所展示的DBDL 132a的宽度减小，此(如同随θ而变的条带宽度改变)针对与漏极指尖相关联的FDR为相反的。然而，一些邻近稀释条带可由于过程限制而为相同条带宽度，例如在线性漂移区中靠近于漏极的条带。类似地，稀释条带间隔可由于过程限制而针对一些邻近条带为相同的，例如在线性漂移区中靠近于源极的稀释条带间隔。当MFLHVT包含PMOS装置时，稀释将由n型埋入层提供，且(类似于上文所描述的NMOS装置)针对PMOS源极侧将存在较少n型埋入层稀释且针对PMOS漏极侧将存在较多相对n型埋入层稀释。
虽然上文一般描述NMOS MFLHVT，但此信息通过用p掺杂代替经n掺杂区且反之亦然而对于PMOS MFLHVT也是有用的。如本文中所使用，如果经扩散区称为以特定掺杂剂类型(例如，n型)掺杂，那么半导体表面中的此区为特定掺杂剂类型的掺杂浓度高于另一类型(例如，p型)的掺杂剂的掺杂浓度的地方。
制成包含LDMOS/DEMOS晶体管的MFLHVT的一般方面及用以形成LDMOS/DEMOS晶体管的处理可存在于各种参考文献中，包含斯瑞达(Sridhar)等人的标题为“用于LDMOS及DEMOS的厚栅极氧化物(thick gate oxide for LDMOS and DEMOS)”的第US 8,470,675号专利，所述专利以引用方式并入本文中。DEMOS晶体管通过在装置的漏极与沟道之间添加漏极漂移区从而将大多数电场捕获于此区而非沟道区中而具有经延伸漏极，且其(如本文中所使用)还包含称作双重扩散漏极MOS(DDDMOS)的变体。类似于DEMOS晶体管结构，LDMOS晶体管使用通过额外掺杂形成的漏极漂移区。
关于用以形成所揭示DBDL的处理，使用具有多个条带的DBDL层掩模，例如以印刷具有条带化的经暴露条带形区的光致抗蚀剂图案。接下来进行植入以形成稀释埋入漂移层条带，后续接着退火。形成包含与多个源极指互相交叉的多个漏极指的漏极，所述源极指及所述漏极指各自被掺杂成第二掺杂剂类型。至少第一栅极堆叠形成于半导体表面上在源极与漏极之间。
所揭示实施例的优点包含：减轻三重RESURF HV晶体管(其缺乏顶部表面层174)或四重RESURF HV晶体管(例如，图1A中所展示的MFLHVT 100)的场拥挤，而不会因电流传导路径的已知移除而有损于来自指尖区的电流贡献。另一优点为：所揭示DBDL设计为基于方程式的，从而使得能够使用自动设计而不需要任何人类布局活动。其它优点包含低实施成本，这是因为实施方案仅涉及掩模改变，且额外制作步骤是不必要的。
实例
所揭示实施例进一步由以下特定实例图解说明，所述实例不应解释为以任一方式限制本发明的范围或内容。
图3A展示源极或漏极指，其包含具有相关联线性漂移区290的线性指状件部分310及具有相关联源极FDR 210的指尖311，其中BDL条带320经展示于线性漂移区290中。在图3B中，为展示根据实例性实施例的所揭示DBDL设计中的参数，将指尖311(图3A)的二分之一展示为311a，且将源极FDR 210的二分之一展示为210a。图3A及3B展示θ，其为与FDR中的所关注位置的角度。图3B展示Lθ，其为从漏极深沟115的外边缘到指尖中心285的距离(长度)。图3A展示rθnl，其为源极FDR 210内的xnl的迹线，且xnl为线性漂移区290中的BDL条带320的一个边缘。rθnl在θ＝0时与xnl对齐。rs,d为指尖311半圆的半径，所述半径经描绘为从指尖中心285绘制的实线(如图3A中所展示)。
举例来说，FDR内的Lθ计算在θ<反正切(arctg)(Lf/L)时：
Lθ＝L/cosθ
且当π/2>θ>arctg(Lf/L)时：
实例性漂移长度比例缩放方程式为：
依据以上比例缩放方程式然后可对Lθ求解，且然后对rθ(展示为rθnl)求解，其中rθ定义如何绘制(布局)与源极或漏极指的指尖相关联的FDR(例如上文所描述的与源极指尖相关联的源极FDR 210)中的每一DBDL条带的边缘。随着Lθ增加，rθnl增加，此使DBDL条带的宽度增加。DBDL条带之间的非所植入区(间隙)的宽度也随Lθ增加。L＝DL+rs,d；DL＝L-rs,d为线性漂移区中的恒定漂移长度。FDR中的漂移区为Lθ＝DLθ+rs,d，DLθ＝Lθ-rs,d。
在展示NMOS装置的源极FDR 210的情形的图2B中，源极FDR 210内的展示为DBDL132a的十五个DBDL条带中的每一者具有随θ变化的宽度(具体来说，其宽度随θ的增加而增加，从而在90度下具有最大宽度)且其宽度图案相对于90度线对称。以上方程式产生此分配，这是因为Lθ随着θ增加而增加，此使rθnl增加从而增加DBDL条带的宽度。
图4展示比较的NLDMOS BVDSS数据，包含来自在例如图2B中所展示的FDR中具有含有可变条带宽度保险设计尺寸的所揭示DBDL的多指NLDMOS装置以及具有含有固定条带宽度保险设计尺寸的常规DBDL的控制跑道NLDMOS装置的BVDSS。多指与跑道(单指)NLDMOS装置布局之间的BVDSS差仅为～40V，这与针对具有具固定条带保险设计尺寸的DBDL设计的多指NLDMOS装置超过100V以上的减小形成对比。
可使用所揭示实施例来形成可集成到各种组装流程中以形成各种不同装置及相关产品的半导体裸片。半导体裸片可包含各种在其中的元件及/或在其上的层，包含势垒层、电介质层、装置结构、主动元件及被动元件，例如源极区、漏极区、位线、基极、射极、集电极、导电线及导电导通体。此外，半导体裸片可由包含双极绝缘栅极双极晶体管(IGBT)、CMOS、BiCMOS及MEMS的各种过程形成。
修改在所描述实施例中是可能的，且其它实施例在所附权利要求书的范围内也是可能的。

Claims (18)

1.一种多指横向高电压晶体管MFLHVT，其包括：
在被掺杂成第一掺杂剂类型的衬底上包含以下各项的堆叠：井，其被掺杂成第二掺杂剂类型；埋入漂移层BDL，其被掺杂成所述第一掺杂剂类型、具有包含多个稀释条带的稀释BDL部分DBDL；半导体表面，其在所述BDL上被掺杂成所述第二掺杂剂类型；
电介质隔离区，其至少部分地在所述半导体表面中、具有界定在第一电介质间隙区(第一深沟)中的第一作用区域及在第二电介质间隙区(第二深沟)中的第二作用区域的间隙；
漏极，其包含在所述第二深沟中具有漏极指尖的多个漏极指，所述漏极与源极互相交叉，所述源极包含在所述第一深沟中具有源极指尖的多个源极指，所述漏极指及所述源极指各自被掺杂成所述第二掺杂剂类型；
指尖漂移区FDR，其在所述第一深沟与所述第二深沟之间与所述漏极指尖(漏极FDR)及所述源极指尖(源极FDR)中的至少一者相关联，其内有所述DBDL；
在所述半导体表面中的上部电流沟道及在所述井中的下部电流沟道，所述上部电流沟道及所述下部电流沟道两者均在所述源极与所述漏极之间；及
至少第一栅极堆叠，其在所述半导体表面上位于所述源极与所述漏极之间；
其中所述多个稀释条带具有在其相应位置处随漂移长度单调地增加的相应条带宽度。
2.根据权利要求1所述的MFLHVT，其中所述源极FDR的所述相应条带宽度随相对于所述源极FDR与线性漂移区的边界的角度θ的增加单调地增加，从而在90度下具有最大宽度，且其中所述漏极FDR的所述相应条带宽度随相对于所述漏极FDR与线性漂移区的边界的角度θ的增加单调地减小，从而在90度下具有最小宽度。
3.根据权利要求1所述的MFLHVT，其中所述FDR包含所述源极FDR及所述漏极FDR。
4.根据权利要求1所述的MFLHVT，其进一步包括在所述半导体表面中被掺杂成所述第一掺杂剂类型的顶部表面层。
5.根据权利要求1所述的MFLHVT，其中所述第一栅极堆叠包含分裂栅极，所述分裂栅极包含第一栅极堆叠及横向于所述第一栅极堆叠的第二栅极堆叠。
6.根据权利要求1所述的MFLHVT，其中所述MFLHVT包含漏极延伸MOS DEMOS晶体管。
7.根据权利要求1所述的MFLHVT，其中所述MFLHVT包含横向扩散MOS LDMOS晶体管。
8.根据权利要求1所述的MFLHVT，其中所述衬底包含硅且所述第一栅极堆叠的栅极电极包含多晶硅。
9.一种集成电路IC，其包括：
衬底，其被掺杂成第一掺杂剂类型；
多指横向高电压晶体管MFLHVT，其包含：
在所述衬底上包含以下各项的堆叠：井，其被掺杂成第二掺杂剂类型；埋入漂移层BDL，其被掺杂成所述第一掺杂剂类型、具有包含多个稀释条带的稀释BDL部分DBDL；半导体表面，其在所述BDL上被掺杂成所述第二掺杂剂类型；
电介质隔离区，其至少部分地在所述半导体表面中、具有界定在第一电介质间隙区(第一深沟)中的第一作用区域及在第二电介质间隙区(第二深沟)中的第二作用区域的间隙；
漏极，其包含在所述第二深沟中具有漏极指尖的多个漏极指，所述漏极与源极互相交叉，所述源极包含在所述第一深沟中具有源极指尖的多个源极指，所述漏极指及所述源极指各自被掺杂成所述第二掺杂剂类型；
指尖漂移区FDR，其在所述第一深沟与所述第二深沟之间与所述漏极指尖(漏极FDR)及所述源极指尖(源极FDR)中的至少一者相关联，其内有所述DBDL；
在所述半导体表面中的上部电流沟道及在所述井中的下部电流沟道，所述上部电流沟道及所述下部电流沟道两者均在所述源极与所述漏极之间；
至少第一栅极堆叠，其在所述半导体表面上位于所述源极与所述漏极之间；
其中所述多个稀释条带具有在其相应位置处随漂移长度单调地增加的相应条带宽度，及
形成于所述衬底中的对称p沟道金属氧化物半导体PMOS晶体管及对称n沟道MOS NMOS晶体管。
10.根据权利要求9所述的IC，其中所述源极FDR的所述相应条带宽度随相对于所述源极FDR与线性漂移区的边界的角度θ的增加单调地增加，从而在90度下具有最大宽度，且其中所述漏极FDR的所述相应条带宽度随相对于所述漏极FDR与线性漂移区的边界的角度θ的增加单调地减小，从而在90度下具有最小宽度。
11.根据权利要求9所述的IC，其中所述FDR包含所述源极FDR及所述漏极FDR。
12.根据权利要求9所述的IC，其中所述MFLHVT进一步包含在所述半导体表面中被掺杂成所述第一掺杂剂类型的顶部表面层。
13.根据权利要求9所述的IC，其中所述第一栅极堆叠包含分裂栅极，所述分裂栅极包含第一栅极堆叠及横向于所述第一栅极堆叠的第二栅极堆叠。
14.一种形成横向功率MOS晶体管的方法，其包括
提供以第一掺杂剂类型掺杂的衬底，所述衬底上具有被掺杂成第二掺杂剂类型的井，在所述井上具有被掺杂成所述第二掺杂剂类型的半导体表面；
形成电介质隔离区，所述电介质隔离区至少部分地在所述半导体表面中、具有界定在第一电介质间隙区(第一深沟)中的第一作用区域及在第二电介质间隙区(第二深沟)中的第二作用区域的间隙；
形成具有包含多个稀释条带的稀释BDL部分DBDL的被掺杂成所述第一掺杂剂类型的埋入漂移层BDL，其包含：使用具有所述多个稀释条带的稀释BDL掩模形成掩蔽图案，所述多个稀释条带具有在其相应位置处随漂移长度单调地增加的相应条带宽度；及使用所述掩蔽图案进行植入；
形成包含在所述第二深沟中具有漏极指尖的多个漏极指的漏极，所述漏极与源极互相交叉，所述源极包含在所述第一深沟中具有源极指尖的多个源极指，所述漏极指及所述源极指各自被掺杂成所述第二掺杂剂类型；
其中所述DBDL位于在所述第一深沟与所述第二深沟之间与所述漏极指尖(漏极FDR)及所述源极指尖(源极FDR)中的至少一者相关联的指尖漂移区FDR内；及
在所述半导体表面上在所述源极与所述漏极之间形成至少第一栅极堆叠。
15.根据权利要求14所述的方法，其中所述相应条带宽度随相对于所述FDR的边界的角度θ的增加而增加，其中线性漂移区在90度下具有最大宽度。
16.根据权利要求14所述的方法，其中所述FDR包含所述源极FDR及所述漏极FDR。
17.根据权利要求14所述的方法，其进一步包括在所述半导体表面中形成被掺杂成所述第一掺杂剂类型的顶部表面层。
18.根据权利要求14所述的方法，其中所述第一栅极堆叠包含分裂栅极，所述分裂栅极包含第一栅极堆叠及横向于所述第一栅极堆叠的第二栅极堆叠。
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