CN107479617B - High-precision correction circuit for band-gap reference voltage source - Google Patents
High-precision correction circuit for band-gap reference voltage source Download PDFInfo
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- CN107479617B CN107479617B CN201710849249.3A CN201710849249A CN107479617B CN 107479617 B CN107479617 B CN 107479617B CN 201710849249 A CN201710849249 A CN 201710849249A CN 107479617 B CN107479617 B CN 107479617B
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- 238000009966 trimming Methods 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 2
- 238000000342 Monte Carlo simulation Methods 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/625—Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is ac or dc
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The present invention discloses a band gap baseA high-precision correction circuit of a quasi-voltage source. The circuit comprises an operational amplifier, a capacitor, a PMOS tube and a trimming circuit; reference voltage V generated by operational amplifier reverse phase end connection band gap reference source BG The same-phase end of the operational amplifier is connected with a first terminal V of the trimming circuit f The output end of the operational amplifier is connected with the first terminal of the capacitor and the grid electrode of the PMOS tube, the source electrode of the PMOS tube is connected with the power supply VDD, the drain electrode of the PMOS tube is connected with the second terminal of the capacitor and the second terminal V of the trimming circuit top The third terminal V of the trimming circuit is connected with each other 1.2 To correct the output voltage, the fourth terminal V of the trimming circuit bottom And (5) grounding. The invention combines the buffer circuit and the correction circuit in the band gap reference source into a whole, can correct errors of the reference voltage due to the influence of factors such as process angle, offset, temperature and the like, can eliminate the influence of fine tuning on the temperature characteristic of the reference voltage and can improve the load capacity of the output voltage. The invention adopts a digital trimming mode and has the advantages of flexible correction, high precision, low power consumption and small area.
Description
Technical Field
The invention relates to the technical field of power supplies, in particular to a high-precision correction circuit for a band-gap reference voltage source.
Background
With the continuous increase of the integration level of the system, almost all integrated circuits need a high-precision reference source to promote the system to achieve the best performance, and the bandgap reference source has the most excellent performance and is widely applied to the integrated circuits. In the integrated circuit manufacturing process, the precision of the bandgap reference source is affected by process deviation, mismatch, external load change, temperature change and the like, and in order to obtain a high-precision bandgap reference source, a few correction technologies are usually required. The traditional correction technology generally carries out trimming on elements in a core circuit of the band-gap reference source, and the introduction of the trimming technology can lead to the temperature characteristic of output reference voltage or reference current to be poor and influence the precision of the reference source. The traditional trimming technology generally adopts a laser trimming technology and a fuse trimming technology, so that the cost is high, the output standard can not be changed after trimming, and the influence caused by the change of the packaging pressure and the ambient temperature can not be dealt with.
Disclosure of Invention
Aiming at the problems existing in the prior art, the invention provides a trimming circuit for correcting a band-gap reference voltage source, and also provides a band-gap reference voltage source high-precision correction circuit based on the trimming circuit.
The trimming circuit comprises a register, a 4-16 line decoder, NMOS transistors MC1-MC16 and resistors R0-R16. The first input end of the 4-16 line decoder is connected with a first bit correction signal Trim <0> controlled by a register, the second input end of the 4-16 line decoder is connected with a second bit correction signal Trim <1> controlled by the register, the third input end of the 4-16 line decoder is connected with a third bit correction signal Trim <2> controlled by the register, and the fourth input end of the 4-16 line decoder is connected with a fourth bit correction signal Trim <3> controlled by the register.
The first output end of the 4-16 line decoder is connected with the grid of the MC1, the second output end of the 4-16 line decoder is connected with the grid of the MC2, the third output end of the 4-16 line decoder is connected with the grid of the MC3, the fourth output end of the 4-16 line decoder is connected with the grid of the MC4, the fifth output end of the 4-16 line decoder is connected with the grid of the MC5, the sixth output end of the 4-16 line decoder is connected with the grid of the MC6, the seventh output end of the 4-16 line decoder is connected with the grid of the MC7, the eighth output end of the 4-16 line decoder is connected with the grid of the MC8, the ninth output end of the 4-16 line decoder is connected with the grid of the MC9, the tenth output end of the 4-16 line decoder is connected with the grid of the MC10, the eleventh output end of the 4-16 line decoder is connected with the grid of the MC11, the twelfth output end of the 4-16 line decoder is connected with the grid of the MC12, the thirteenth output end of the 4-16 line decoder is connected with the grid of the MC13, the thirteenth end of the 4-16 line decoder is connected with the grid of the MC16, and the fifteenth end of the MC16 is connected with the grid of the MC 14.
The first terminal of R0 is the fourth terminal V of the trimming circuit bottom The second terminal of R0 is connected with the first terminal of R1, the second terminal of R1, the source of MC1 and the first terminal of R2 are connected with each other, the second terminal of R2, the source of MC2 and the first terminal of R3 are connected with each other, the second terminal of R3, the source of MC3 and the first terminal of R4 are connected with each other, the second terminal of R4, the source of MC4 and the first terminal of R5 are connected with each other, the second terminal of R5, the source of MC5 and the first terminal of R6 are connected with each other, the second terminal of R6, the source of MC6 and the first terminal of R7 are connected with each other, the second terminal of MC7 and the first terminal of R8 are connected with each other, the source of MC8 and the first terminal of R9 are connected with each other to form a third terminal V of a trimming circuit 1.2 The method comprises the steps of carrying out a first treatment on the surface of the The second terminal of R9, the source of MC9 and the first terminal of R10 are connected with each other, the second terminal of R10, the source of MC10 and the first terminal of R11 are connected with each other, the second terminal of R11, the source of MC11 and the first terminal of R12 are connected with each other, the second terminal of R12, the source of MC12 and the first terminal of R13 are connected with each other, the second terminal of R13, the source of MC13 and the first terminal of R14 are connected with each other, the second terminal of MC14 and the first terminal of R15 are connected with each other, the second terminal of R15, the source of MC15 and the first terminal of R16 are connected with each other, and the second terminal of R16 and the source of MC16 are connected with each other to form a second terminal V of a trimming circuit top 。
The drain of MC1, the drain of MC2, the drain of MC3, the drain of MC4, the drain of MC5, the drain of MC6, the drain of MC7, the drain of MC8, the drain of MC9, the drain of MC10, the drain of MC11, the drain of MC12, the drain of MC13, the drain of MC14, the drain of MC15, the drain of MC16 are connected with each other to form a first terminal V of a trimming circuit f 。
The high-precision correction circuit of the band-gap reference voltage source comprises an operational amplifier A1, a capacitor C1, a PMOS tube M1 and a trimming circuit. The inverting input end of the operational amplifier A1 is connected with a reference voltage V generated by a band-gap reference source BG The noninverting input end of the operational amplifier A1 and the first terminal V of the trimming circuit f The output end of the operational amplifier A1 is connected with the first terminal of the capacitor C1 and the grid electrode of the PMOS tube M1, the source electrode of the PMOS tube M1 is connected with the power supply VDD, the drain electrode of the PMOS tube M1 is connected with the second terminal of the capacitor C1 and the second terminal V of the trimming circuit top Third terminal V of the trimming circuit 1.2 To correct the output voltage, the fourth terminal V of the trimming circuit bottom Ground GND.
The invention combines the buffer circuit and the correction circuit in the band gap reference source into a whole, can correct errors of the reference voltage due to the influence of factors such as process angle, offset, temperature and the like, can eliminate the influence of fine tuning on the temperature characteristic of the reference voltage and can improve the load capacity of the output voltage. The invention adopts a digital trimming mode and has the advantages of flexible correction, high precision, low power consumption and small area.
Drawings
Fig. 1 is a schematic diagram of a conventional bandgap reference voltage source core circuit.
Fig. 2 is a trimming circuit in the present invention.
Fig. 3 is a circuit connection diagram of the present invention.
Detailed Description
The following detailed description of the technical solution of the present invention is provided in connection with the accompanying drawings and examples to facilitate a better understanding.
FIG. 1 shows a conventional bandgap reference voltage source core circuit for generating a reference voltage V BG Theoretical analysis can obtain the reference voltage V when the temperature coefficient is zero BG Approximately 1.25V, but the reference voltage value is subject to errors due to factors such as process angle, offset, temperature, etc., a correction circuit is required to be designed to correct the reference voltage to be near an ideal value in order to eliminate the errors caused by the reference voltage. Through reasonable design and Monte carlo simulation of the circuit, the simulation can obtain that the output reference voltage is between 1.1V and 1.3V, and the invention needs to generate a reference voltage of 1.2V, thus the invention needs to adoptThe trimming technique corrects the output voltage to 1.2V.
The conventional trimming technology is to trim the resistor, generally the resistor R1 in fig. 1, and the introduction of the trimming technology changes the temperature characteristic of the original output reference voltage, so that only a small part of the temperature characteristic of the output voltage is usually good, and a large part of the temperature characteristic is poor, so that the method for trimming the resistor R1 is not suitable for high-precision occasions. In order to improve the accuracy of the output reference voltage, the invention provides a novel correction circuit, which does not change the temperature characteristic of the output reference voltage, and the specific implementation circuit is shown in fig. 2 and 3. In order not to change the temperature characteristic of the output reference voltage, the resistor R1 in the core circuit is not trimmed, but the reference voltage V obtained by the core circuit BG As the input voltage of the whole correction circuit, the potential of the same-phase end and the opposite end of the operational amplifier A1 is equal through the action of the negative feedback circuit loop, and the potential of the same-phase end is equal to the reference voltage V generated by the core circuit BG 。
NMOS tubes MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, MC9, MC10, MC11, MC12, MC13, MC14, MC15, MC16 in the trimming circuit act as switches, the on and off of the switches are controlled by a register, the register has a 4-bit address, the 4-bit address is connected with the input end of a 4-16 line decoder, and the 16 output ends of the 4-16 line decoder are respectively connected with the grid electrodes of MC1-MC16, so that the on or off of MC1-MC16 can be controlled by setting 0 or 1 for each bit of the register. When Trim<0>～Trim<3>When 0000, only MC1 is turned on, and the others are turned off; when Trim<0>～Trim<3>When 0001, only MC2 is turned on, and the others are turned off; when Trim<0>～Trim<3>When 0010 is satisfied, only MC3 is turned on, and the others are turned off; when Trim<0>～Trim<3>When 0011 is adopted, only MC4 is turned on, and the others are turned off; when Trim<0>～Trim<3>When 0100, only MC5 is turned on, and the others are turned off; when Trim<0>～Trim<3>When 0101, only MC6 is turned on, and the others are turned off; when Trim<0>～Trim<3>When the voltage is 0110, only MC7 is turned on, and the other is turned off; when Trim<0>～Trim<3>In the case of 0111, only MC8 is on,other shut-off; when Trim<0>～Trim<3>When the value is 1000, only MC9 is turned on, and the others are turned off; when Trim<0>～Trim<3>If 1001 is adopted, only MC10 is turned on, and the others are turned off; when Trim<0>～Trim<3>When the voltage is 1010, only MC11 is turned on, and the others are turned off; when Trim<0>～Trim<3>When the value is 1011, only MC12 is turned on, and the others are turned off; when Trim<0>～Trim<3>When the voltage is 1100, only MC13 is turned on, and the others are turned off; when Trim<0>～Trim<3>If 1101, only MC14 is turned on, and the others are turned off; when Trim<0>～Trim<3>If 1110, only MC15 is turned on, and the others are turned off; when Trim<0>～Trim<3>When 1111 is found, only MC16 is turned on, and the others are turned off; only one NMOS tube is turned on at any time. When the reference voltage V generated by the core circuit BG At 1.1V, trim<0>～Trim<3>Set to 0000, the MC1 is conducted, V 1.2 Outputting a voltage of 1.2V; when the reference voltage V generated by the core circuit BG At 1.3V Trim<0>～Trim<3>Set to 1111, M16 is on, V 1.2 Outputting a voltage of 1.2V; when the reference voltage V generated by the core circuit BG At a certain value between 1.1V and 1.3V, a certain switch can be turned on by adjusting the value of a register, so that V 1.2 And outputting a high-precision reference voltage of 1.2V.
The correction circuit is similar to an in-phase proportional operational amplifier, so that the temperature characteristics of the output voltage and the input voltage are consistent, the temperature characteristics of the input voltage cannot be changed, and the influence of trimming on the temperature characteristics of the output reference voltage is eliminated. The invention can also eliminate the influence of the self offset voltage of the operational amplifier A1, and the offset voltage generated by the operational amplifier A1 can be used as the reference voltage V of the front-stage core circuit BG The generated errors can be eliminated by trimming the correction circuit. The invention adopts a voltage series negative feedback structure, and can improve the output voltage V 1.2 The load capacity of the circuit is improved, and a buffer circuit is not needed to be connected to the subsequent stage. The invention can be used to generate other fixed value reference voltages in addition to 1.2V fixed reference voltages.
Claims (2)
1. A be used for correcting band gap reference voltage sourceThe trimming circuit comprises a register, a 4-16 line decoder, NMOS transistors MC1-MC16 and resistors R0-R16; the first terminal of the resistor R0 is a fourth terminal V of the trimming circuit bottom The second terminal of the resistor R0 is connected with the first terminal of the resistor R1, the second terminal of the resistor R1, the source of the NMOS tube MC1 and the first terminal of the resistor R2 are connected with each other, the second terminal of the resistor R2, the source of the NMOS tube MC2 and the first terminal of the resistor R3 are connected with each other, the second terminal of the resistor R3, the source of the NMOS tube MC3 and the first terminal of the resistor R4 are connected with each other, the second terminal of the resistor R4, the source of the NMOS tube MC4 and the first terminal of the resistor R5 are connected with each other, the second terminal of the resistor R5, the source of the NMOS tube MC5 and the first terminal of the resistor R6 are connected with each other, the second terminal of the NMOS tube MC6, the source of the NMOS tube MC7 and the first terminal of the resistor R8 are connected with each other, and the second terminal of the source of the NMOS tube MC8 and the first terminal of the resistor R9 are connected with each other to form a third terminal V of a trimming circuit 1.2 The method comprises the steps of carrying out a first treatment on the surface of the The second terminal of the resistor R9, the source of the NMOS tube MC9 and the first terminal of the resistor R10 are connected with each other, the second terminal of the resistor R10, the source of the NMOS tube MC10 and the first terminal of the resistor R11 are connected with each other, the second terminal of the resistor R11, the source of the NMOS tube MC12 and the first terminal of the resistor R13 are connected with each other, the second terminal of the resistor R13, the source of the NMOS tube MC13 and the first terminal of the resistor R14 are connected with each other, the second terminal of the resistor R14, the source of the NMOS tube MC14 and the first terminal of the resistor R15 are connected with each other, the second terminal of the resistor R15, the source of the NMOS tube MC15 and the first terminal of the resistor R16 are connected with each other, and the second terminal of the source of the NMOS tube MC16 are connected with each other to form a second terminal V of a trimming circuit top The method comprises the steps of carrying out a first treatment on the surface of the The drains of NMOS tubes MC1-MC16 are connected to each other to form a first terminal V of the trimming circuit f The method comprises the steps of carrying out a first treatment on the surface of the The 4 input ends of the 4-16 line decoder are sequentially connected with the 4 correction signal output ends controlled by the register; the 16 output ends of the 4-16 line decoder are respectively connected with the grids of the NMOS transistors MC1-MC16 according to serial numbers.
2. A high-precision correction circuit for a bandgap reference voltage source, the correction circuit comprising an operational amplifier A1, a capacitor C1, a PMOS transistor M1 and the trimming circuit of claim 1; the inverting input end of the operational amplifier A1 is connected with a reference voltage V generated by a band-gap reference source BG The noninverting input end of the operational amplifier A1 and the first terminal V of the trimming circuit f The output end of the operational amplifier A1 is connected with the first terminal of the capacitor C1 and the grid electrode of the PMOS tube M1, the source electrode of the PMOS tube M1 is connected with the power supply VDD, the drain electrode of the PMOS tube M1 is connected with the second terminal of the capacitor C1 and the second terminal V of the trimming circuit top The third terminal V of the trimming circuit is connected with each other 1.2 To correct the output voltage, the fourth terminal V of the trimming circuit bottom Ground GND.
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| CN201710849249.3A CN107479617B (en) | 2017-09-20 | 2017-09-20 | High-precision correction circuit for band-gap reference voltage source |
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| CN201710849249.3A CN107479617B (en) | 2017-09-20 | 2017-09-20 | High-precision correction circuit for band-gap reference voltage source |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110083193B (en) * | 2019-03-29 | 2020-10-27 | 南京中感微电子有限公司 | Bandgap reference voltage generating circuit |
| CN110865676B (en) * | 2019-10-23 | 2022-01-25 | 晟合微电子(肇庆)有限公司 | Method for digitally controlling output voltage of low-voltage device |
| CN110933811A (en) * | 2019-12-26 | 2020-03-27 | 深圳市库莱特光电科技有限公司 | LED constant current drive circuit and LED lamp |
| CN112859997B (en) * | 2021-02-03 | 2022-08-23 | 北京中电华大电子设计有限责任公司 | Self-calibration circuit structure of band-gap reference voltage three-temperature TRIM |
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| KR20140029818A (en) * | 2012-08-30 | 2014-03-11 | 에스케이하이닉스 주식회사 | Circuit and method for trimming voltage of semiconductor apparatus |
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| JP2001285056A (en) * | 2000-03-29 | 2001-10-12 | Toshiba Microelectronics Corp | Automatic trimming circuit of oscillator |
| JP2010171369A (en) * | 2008-12-22 | 2010-08-05 | Elpida Memory Inc | Semiconductor device |
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