CN107479614A - A kind of biasing circuit with high PSRR - Google Patents

A kind of biasing circuit with high PSRR Download PDF

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Publication number
CN107479614A
CN107479614A CN201710699923.4A CN201710699923A CN107479614A CN 107479614 A CN107479614 A CN 107479614A CN 201710699923 A CN201710699923 A CN 201710699923A CN 107479614 A CN107479614 A CN 107479614A
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China
Prior art keywords
pmos
type triode
voltage
npn type
psrr
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CN201710699923.4A
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CN107479614B (en
Inventor
周泽坤
李颂
孙汉萍
张家豪
石跃
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

A kind of biasing circuit with high PSRR, belongs to analogue layout field.Two BE knot pressures drops, which are subtracted, using reference voltage produces the voltage with PTAT, the electric current with PTAT is produced by resistance R1 again, caused electric current influence by voltage is smaller, by the first PNP type triode QP1 and the 3rd NPN type triode QN3 cascade by the drain voltage clamper of the second PMOS in VCC VSG_MP1‑VEB_QP1, reduce dependences of the second PMOS MP2 to supply voltage, so that the biasing of output keeps relative stability；Stablize the second PMOS MP2 grid voltage and drain voltage also with two feedback loops, with reference to the interaction of two feedback loops, the power supply rejection ability of the bias current of output is lifted；Finally further strengthen the PSRR of integral biased circuit using automatic biasing structure.Bigoted circuit provided by the invention, there is high PSRR and good Serial regulation performance.

Description

A kind of biasing circuit with high PSRR
Technical field
The invention belongs to analogue layout field, and in particular to a kind of high PSRR biasing circuit is set Meter.
Background technology
With the fast development of integrated circuit technology, short channel device is degrading ditch and adjusts problem so that current offset is to leakage Source voltage has very big dependence.Traditional a solution is to use common-source common-gate current mirror, by the way that mirror image pipe is leaked The original 1/g of source electric potential change boil down tomrOTo realize higher mirror image precision, but this structure needs to consume extra electricity Discard degree.Another simple scheme is to increase the channel length of transistor, weakens channel-length modulation, but this needs Take sizable area.Therefore, traditional current mirror scheme can not alleviate because power rail shake change and caused by bias Change.
The content of the invention
For above-mentioned weak point, the present invention provides a kind of biasing circuit with high PSRR, with negative-feedback Technology, output biasing can be made to keep relative stability, there is high PSRR and good Serial regulation performance.
The technical scheme is that：
A kind of biasing circuit with high PSRR, including the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, the first NPN type triode QN1, second NPN type triode QN2, the 3rd NPN type triode QN3, the first PNP type triode QP1 and resistance R1,
First NPN type triode QN1 base stage and colelctor electrode interconnect and connect the second NPN type triode QN2 base stage and Resistance R1 one end, the first NPN type triode QN1 and the second NPN type triode QN2 grounded emitter；
Resistance R1 the first PNP type triode of another termination QP1 colelctor electrode and the 3rd NPN type triode QN3 transmitting Pole, the 3rd NPN type triode QN3 base stage connection reference voltage VREF, its colelctor electrode connect the first PNP type triode QP1 base Pole and the second PMOS MP2 drain electrode；
First PMOS MP1 base stage connection the second PMOS MP2 and the 3rd PMOS MP3 grid, the 4th PMOS MP4 drain electrode and the first PNP type triode QP1 emitter stage, its 4th PMOS MP4 of connection that drains source electrode；
5th PMOS MP5 grid leak interconnects and connects the 4th PMOS MP4 and the 6th PMOS MP6 grid and Two NPN type triode QN2 colelctor electrode, the 6th PMOS MP6 source electrode connect the 3rd PMOS MP3 drain electrode, and it, which drains, makees For the output end output bias current of the biasing circuit；
First PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3 and the 5th PMOS MP5 source electrode connect power supply Voltage VCC.
Specifically, the magnitude of voltage of the reference voltage V REF is twice of band gap voltage.
Beneficial effects of the present invention are：Two feedback loops in circuit of the present invention stabilize the second PMOS MP2's Grid voltage and drain voltage, reduce influence of fluctuations and the channel modulation effect of supply voltage；Other 4th PMOS MP4, The automatic biasing structure that 5th PMOS MP5, the first NPN type triode QN1 and the second NPN type triode QN2 are formed further adds The strong PSRR of integral biased circuit；Bigoted circuit provided by the invention, with high PSRR and well Serial regulation performance.
Brief description of the drawings
Fig. 1 proposes a kind of Organization Chart of the biasing circuit with high PSRR for the present invention.
Fig. 2 proposes a kind of practical circuit diagram of the biasing circuit with high PSRR for the present invention.
Fig. 3 is the analogous diagram that the bias current obtained in embodiment changes with power supply VCC.
Fig. 4 is the analogous diagram that traditional common-source common-gate current mirror biasing circuit changes with power supply VCC.
Fig. 5 is the simulation curve figure of the PSRR PSRR of biasing circuit in embodiment.
Embodiment
The invention will be further elaborated with specific embodiment below in conjunction with the accompanying drawings：
A kind of Organization Chart of the biasing circuit with high PSRR is proposed for the present invention as shown in Figure 1, Fig. 2 is actual Circuit diagram, the first NPN type triode QN1 and the second NPN type triode QN2 form current-mirror structure, the first PNP type triode QP1 and the 3rd NPN type triode QN3 forms clamp circuit, and the first PMOS MP1 and the 4th PMOS MP4 form cascade Structure, the 3rd PMOS MP3 and the 6th PMOS MP6 also form cascode structure, and the 5th PMOS MP5 is as offset 4th PMOS MP4 and the 6th PMOS MP6 provides grid potential.The 3rd NPN type triode QN3 grid connects in the present embodiment The reference voltage connect is provided by twice of band gap voltage, and this voltage is influenceed smaller by supply voltage.
Total operation principle of the present embodiment is：
Two times of band gap voltages subtract the 3rd NPN type triode QN3 and the first NPN type triode QN1 two BE knot pressures drop A PTAT voltage with PTAT is produced, the PTAT current with PTAT is produced by resistance R1, Caused electric current influence by voltage is smaller, after reference voltage V REF is established, by two VBEKnot produces electric current on resistance R1 Size is：
Due to the first NPN type triode QN1 and the second NPN type triode QN2 mirror images, flowed through on the 5th PMOS MP5 The big electric current with resistance R1 etc., the 4th PMOS MP4 and the 6th PMOS MP6 grid is carried out by the 5th PMOS MP5 inclined Put, the first PMOS MP1 and the second PMOS MP2 mirror images.Again due to the first PNP type triode QP1 and the 3rd NPN type triode QN3 is biased by the first PMOS MP1 and the second PMOS MP2 respectively, and the 3rd NPN type triode QN3 collector potential is VCC-VSG_MP1-VEB_QP1, then the second PMOS MP2 drain-source voltage is VSG_MP1+VEB_QP1, consider channel-length modulation, Then the second PMOS MP2 electric current is：
Wherein：μpFor the mobility in hole, COXFor unit area gate oxide capacitance, (W/L)MP2For the second PMOS MP2 Breadth length ratio, VTHPFor the second PMOS MP2 threshold voltage, λ is channel length modulation coefficient.
When supply voltage is shaken, by the first PNP type triode QP1, the first PMOS MP1, the second PMOS MP2 The feedback loop formed with the 4th PMOS MP4, the second PMOS MP2 grid voltage can be stablized；By the first positive-negative-positive three The feedback loop that pole pipe QP1 and the 3rd NPN type triode QN3 is formed, the second PMOS MP2 drain terminal voltage can be stablized, By the cascade of the first PNP type triode QP1 and the 3rd NPN type triode QN3 the two triodes by the second PMOS MP2's Drain voltage clamper is in VCC-VSG_MP1-VEB_QP1, reduce dependences of the second PMOS MP2 to supply voltage, so that output Biasing keep relative stability；With reference to the interaction of two feedback control loops, the power supply rejection ability of output current is carried Rise.
Two negative feedback structures make VSG(MP2)With VSD(MP2)Keep relative stability, reduce supply voltage influence of fluctuations and Channel modulation effect.From above formula, work as VSG(MP2)With VSD(MP2)When keeing relative stability, the second PMOS MP2 electric current is flowed through It is held essentially constant.
Finally, the NPN type triode QN1 of the 4th PMOS MP4, the 5th PMOS MP5, first and the second NPN type three are utilized The automatic biasing structure that pole pipe QN2 is formed, further strengthen the PSRR of integral biased circuit.
By the first PNP type triode QP1, the first PMOS MP1, the second PMOS MP2 and the 4th PMOS MP4 composition Feedback loop, the electric current for making to flow through on the second PMOS MP2 keep relative stability, and its loop gain is：
AV=AV1·AV2=(gm_MP2Rout1)·(gm_QP1Rout2)
Wherein：
Wherein：rπ_QP1For the first PNP type triode QP1 small-signal input resistance, gm_MP1For the first PMOS MP1's Mutual conductance, rO_MP2For the second PMOS MP2 output resistance, β is the first PNP type triode QP1 current gain.
The bias current that the present embodiment obtains is with supply voltage VCC variation relation as shown in figure 3, by that can be seen in figure Go out, when supply voltage changes to 8V by 4.6V, its output bias current changes to 3.2342uA by 3.2253uA, its linear tune Whole rate is：
Traditional cascade current source electric current is with supply voltage VCC variation relation as shown in figure 4, by that can be seen in figure Go out, when supply voltage changes to 8V by 4.6V, its output bias current changes to 3.3773uA by 3.2253uA, its linear tune Whole rate is：
The biasing circuit stable performance of the present embodiment it can be seen from Fig. 3 and Fig. 4 result, it exports biasing with power supply Voltage change is basically unchanged.
PSRR PSRR simulation curve is as shown in figure 5, as can be seen from Figure in the present embodiment, in low frequency its PSRR PSRR can reach -79.41dB, be 10 in frequency8During Hz, its PSRR PSRR can also reach- 26.35dB.In terms of performance indications, biasing circuit proposed by the present invention, there is high PSRR and good Serial regulation Energy.
One of ordinary skill in the art can make various do not depart from originally according to these technical inspirations disclosed by the invention The other various specific deformations and combination, these deformations and combination of invention essence are still within the scope of the present invention.

Claims (2)

1. a kind of biasing circuit with high PSRR, it is characterised in that including the first PMOS (MP1), the 2nd PMOS Manage (MP2), the 3rd PMOS (MP3), the 4th PMOS (MP4), the 5th PMOS (MP5), the 6th PMOS (MP6), first NPN type triode (QN1), the second NPN type triode (QN2), the 3rd NPN type triode (QN3), the first PNP type triode (QP1) and resistance (R1),
The base stage and colelctor electrode of first NPN type triode (QN1) interconnect and connect the second NPN type triode (QN2) base stage and One end of resistance (R1), the grounded emitter of the first NPN type triode (QN1) and the second NPN type triode (QN2)；
The colelctor electrode of the PNP type triode of another termination first (QP1) of resistance (R1) and the hair of the 3rd NPN type triode (QN3) Emitter-base bandgap grading, the base stage connection reference voltage (VREF) of the 3rd NPN type triode (QN3), its colelctor electrode connect the first PNP type triode (QP1) drain electrode of base stage and the second PMOS (MP2)；
The base stage of first PMOS (MP1) connects grid, the 4th PMOS of the second PMOS (MP2) and the 3rd PMOS (MP3) The drain electrode of (MP4) and the emitter stage of the first PNP type triode (QP1) are managed, the source of its 4th PMOS (MP4) of connection that drains Pole；
The grid leak of 5th PMOS (MP5) interconnect and connect the 4th PMOS (MP4) and the 6th PMOS (MP6) grid and The colelctor electrode of second NPN type triode (QN2), the source electrode of the 6th PMOS (MP6) connect the drain electrode of the 3rd PMOS (MP3), Its output end output bias current to drain as the biasing circuit；
First PMOS (MP1), the second PMOS (MP2), the source electrode of the 3rd PMOS (MP3) and the 5th PMOS (MP5) connect Supply voltage (VCC).
2. the biasing circuit according to claim 1 with high PSRR, it is characterised in that the reference voltage (VREF) magnitude of voltage is twice of band gap voltage.
CN201710699923.4A 2017-08-16 2017-08-16 A kind of biasing circuit with high PSRR Expired - Fee Related CN107479614B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108536208A (en) * 2018-05-10 2018-09-14 上海华虹宏力半导体制造有限公司 Bias current circuit
CN111552345A (en) * 2020-06-03 2020-08-18 南京微盟电子有限公司 Voltage stabilizing circuit for compensating band gap reference voltage shunt

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009017494A (en) * 2007-07-09 2009-01-22 Renesas Technology Corp Bias circuit, power amplification circuit, receiver, transmitter, and transceiver
CN102545780A (en) * 2010-12-23 2012-07-04 鼎亿数码科技(上海)有限公司 Biasing circuit of voltage-controlled oscillator
CN103092252A (en) * 2012-10-23 2013-05-08 深圳先进技术研究院 Power-independent biasing circuit
US20150133186A1 (en) * 2013-09-09 2015-05-14 Skyworks Solutions, Inc. Multimode power amplifier bias circuit with selectable bandwidth
CN106970674A (en) * 2017-05-07 2017-07-21 长沙方星腾电子科技有限公司 A kind of bias current generating circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009017494A (en) * 2007-07-09 2009-01-22 Renesas Technology Corp Bias circuit, power amplification circuit, receiver, transmitter, and transceiver
CN102545780A (en) * 2010-12-23 2012-07-04 鼎亿数码科技(上海)有限公司 Biasing circuit of voltage-controlled oscillator
CN103092252A (en) * 2012-10-23 2013-05-08 深圳先进技术研究院 Power-independent biasing circuit
US20150133186A1 (en) * 2013-09-09 2015-05-14 Skyworks Solutions, Inc. Multimode power amplifier bias circuit with selectable bandwidth
CN106970674A (en) * 2017-05-07 2017-07-21 长沙方星腾电子科技有限公司 A kind of bias current generating circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108536208A (en) * 2018-05-10 2018-09-14 上海华虹宏力半导体制造有限公司 Bias current circuit
CN111552345A (en) * 2020-06-03 2020-08-18 南京微盟电子有限公司 Voltage stabilizing circuit for compensating band gap reference voltage shunt
CN111552345B (en) * 2020-06-03 2022-01-18 南京微盟电子有限公司 Voltage stabilizing circuit for compensating band gap reference voltage shunt

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