CN107424990B - Semiconductor devices and its unit, circuit structure and its unit, circuit system - Google Patents
Semiconductor devices and its unit, circuit structure and its unit, circuit system Download PDFInfo
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- CN107424990B CN107424990B CN201710212966.5A CN201710212966A CN107424990B CN 107424990 B CN107424990 B CN 107424990B CN 201710212966 A CN201710212966 A CN 201710212966A CN 107424990 B CN107424990 B CN 107424990B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000002955 isolation Methods 0.000 claims abstract description 46
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 230000002441 reversible effect Effects 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 241000790917 Dioxys <bee> Species 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- 238000013461 design Methods 0.000 description 12
- 230000005611 electricity Effects 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 9
- 230000003068 static effect Effects 0.000 description 8
- 238000012423 maintenance Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to semiconductor device cell, semiconductor devices, circuit structure unit, circuit structure and circuit systems.Semiconductor device cell includes: substrate；First doped region of the first conduction type in the substrate；Second doped region of the second conduction type in the substrate；The third doped region of the second conduction type in the substrate；Isolation structure is used to be isolated first doped region and second doped region and first doped region and the third doped region；It is sequentially located at the 4th doped region of the first conduction type below the third doped region and the 5th doped region of the second conduction type in the substrate；And it is located at the trap of described first, second and the 5th the second conduction type below doped region in the substrate；And n diode being connected in series with second doped region, wherein n is the integer more than or equal to 0.
Description
Technical field
The present invention relates to semiconductor devices, circuit and technical field of integrated circuits more particularly to a kind of semiconductor devices lists
Member, semiconductor devices, circuit structure unit, circuit structure and circuit system.
Background technique
At present in advanced sub-micron complementary metal oxide semiconductor (Complementary Metal-Oxide-
Semiconductor, CMOS) in technique, system on chip (System on Chip, SoC) integrated circuit has been designed to
Module with multiple VDD and VSS power supply power supplies, such as the interface module of 3.3v, the analog module of 2.5v, 2.5v
Digital circuit blocks, the CPU module of 1.2v, the driver module etc. of 5v.The power supply line VDD and VSS of these modules are general
It needs to be mutually isolated out, prevents noise from interfering with each other.
However, the interface circuit for input/output communication between multiple power modules is vulnerable to electrostatic breakdown.Electrostatic
Pulse can be positive pulse and be also possible to negative pulse, and can enter from any one input and output port (IO) of SoC chip
Then chip interior is flowed out from any one I/O port.Certainly, electrostatic can also enter from vdd terminal mouth or the port VSS, also can
It is flowed out from vdd terminal mouth or the port VSS.In order to avoid electrostatic induced current injures internal core circuit, electrostatic protection scheme is proposed.
Typical prior art design is described in United States Patent (USP) US6144542, wherein using conventional diode as quiet
Electric protective unit.
Summary of the invention
It is an object of the present invention to provide a kind of semiconductor device cell for electrostatic protection, semiconductor devices, packets
Circuit structure unit, circuit structure and the circuit system for including such semiconductor device cell and semiconductor devices, wherein partly leading
Body device cell can substitute the static protective unit in the prior art based on diode, and solution is in the prior art to be based on two
The problem that the capacitor of the static protective unit of pole pipe is big, power consumption is high.
One aspect of the present invention provides a kind of semiconductor device cell comprising: substrate；In the substrate
First doped region of the first conduction type；Second doped region of the second conduction type in the substrate；Positioned at the lining
The third doped region of the second conduction type in bottom；Isolation structure is used to be isolated first doped region and described second and mixes
Miscellaneous area and first doped region and the third doped region；It is sequentially located at below the third doped region in the substrate
The first conduction type the 4th doped region and the second conduction type the 5th doped region；It is located at described the in the substrate
One, second and the 5th the second conduction type below doped region trap；And n two be connected in series with second doped region
Pole pipe, n are the integer more than or equal to 0.5th doped region and trap are identical conduction types, and the 5th doped region is also possible to trap
A part.
In some embodiments, the isolation structure is fleet plough groove isolation structure.
In some embodiments, the isolation structure is silica isolation structure or field oxidation isolation structure.
In some embodiments, the isolation structure is included between first doped region and the second doped region and described
Between first doped region and the third doped region, and the gate structure being formed on the substrate surface, the semiconductor device
Part unit further includes anode and cathode, and the gate structure and first doped region are electrically connected to the anode, and described second
Doped region is electrically connected to the cathode via the n diode, and the third doped region is electrically connected to the cathode.
In some embodiments, first conduction type is p-type, and second conduction type is N-shaped, the substrate tool
There is first conduction type.
In some embodiments, second doped region and third doped region share, and wherein the 4th doped region
Shared second/third doped region is fallen into described with first upright projection of the 5th doped region on the substrate surface
In the second upright projection on substrate surface, the area of first upright projection is less than the area of second upright projection；
And the bottom of a part and the 5th doped region of the bottom of the trap and shared second/third doped region
At least part contacts.
Another aspect provides a kind of semiconductor devices comprising: x above-mentioned semiconductor devices of series connection
Part unit and y the second semiconductor device cells.Second semiconductor device cell includes: substrate；In the substrate
The first conduction type the first doped region；Second doped region of the second conduction type in the substrate；Isolation structure,
It is used to be isolated first doped region and second doped region；It is sequentially located under second doped region in the substrate
The third doped region of first conduction type of side and the 4th doped region of the second conduction type；It is located at described the in the substrate
One, second and the 4th the second conduction type below doped region trap, and wherein x and y is the integer more than or equal to 1.
In some embodiments, x=2, y=1, and n=2.Alternatively, x=1, y=1, and n=2.Alternatively
Ground x=1, y=1, and n=1.
In some embodiments, the isolation structure of second semiconductor device cell is fleet plough groove isolation structure.
In some embodiments, the isolation structure of second semiconductor device cell be silica isolation structure or
Field oxidation isolation structure.
In some embodiments, the isolation structure of second semiconductor device cell be included in first doped region with
The gate structure being formed on the substrate surface between second doped region, second semiconductor device cell further includes anode
And cathode, the gate structure and first doped region are electrically connected to the anode, and second doped region is electrically connected
To the cathode.
In some embodiments, first conduction type of second semiconductor device cell be p-type, described second
Conduction type is N-shaped, and the substrate has first conduction type.
It is yet another aspect of the present invention to provide a kind of circuit structure unit, including input, output end, the first power supply line,
Second source line, and be separately positioned between input terminal and the first power supply line, between input terminal and second source line, output end
Above-mentioned semiconductor device unit between the first power supply line, between output end and second source line, and setting is in the first electricity
Above-mentioned semiconductor device between source line and second source line.
In some embodiments, foregoing circuit structural unit further include be separately positioned on input terminal and the first power supply line it
Between, the above-mentioned semiconductor device unit and above-mentioned semiconductor device of reverse parallel connection between input terminal and second source line.
Another aspect of the invention provides a kind of circuit structure, including multiple foregoing circuit structural units, and setting
The above-mentioned semiconductor device unit of reverse parallel connection between circuit structure unit.
The other aspect of the present invention provides a kind of circuit system, including multiple foregoing circuit structural units, a plurality of electrostatic
Shield bus and it is arranged between the first power supply line of circuit structure unit and corresponding electrostatic protection bus, circuit structure
Reverse parallel connection between the second source line of unit and corresponding electrostatic protection bus and between electrostatic protection bus it is above-mentioned
Semiconductor device cell or above-mentioned semiconductor device.
Above-mentioned semiconductor device unit or above-mentioned semiconductor device are under same design area, than the capacitor of conventional diode
Want small.Moreover, comparing with conventional diode, under same area, their transient state IV characteristic is comparable, thus is more suitable
Electrostatic protection.In addition one electric leakage important advantage is that in the state that the device cell is not turned on, when positive bias
Smaller than conventional diode, i.e. power consumption is lower.
Detailed description of the invention
Figure 1A shows the schematic cross section of the semiconductor device cell of an exemplary embodiment of the present invention；
Figure 1B shows IV curve graph of the semiconductor device cell shown in figure 1A compared with conventional diode；
Fig. 2 shows the schematic cross sections of the semiconductor device cell of an exemplary embodiment of the present invention；
Fig. 3 shows the schematic cross section of the semiconductor device cell of an exemplary embodiment of the present invention；
Fig. 4 A shows the schematic cross section of the semiconductor devices of an exemplary embodiment of the present invention；
Fig. 4 B shows IV curve graph of the example of semiconductor devices shown in Fig. 4 A compared with conventional diode；
Fig. 4 C shows IV curve graph of another example of semiconductor devices shown in Fig. 4 A compared with conventional diode；
Fig. 4 D shows IV curve graph of the another example of semiconductor devices shown in Fig. 4 A compared with conventional diode；
Fig. 5 shows the schematic cross section of the semiconductor devices of an exemplary embodiment of the present invention；
Fig. 6 shows the schematic circuit of the circuit structure unit of an exemplary embodiment of the present invention；
Fig. 7 shows the schematic circuit of the circuit structure of an exemplary embodiment of the present invention；
Fig. 8 shows the schematic circuit of the circuit system of an exemplary embodiment of the present invention.
Specific embodiment
A specific embodiment of the invention is described hereinafter with reference to attached drawing, in the accompanying drawings the same or similar component phase
As appended drawing reference indicate.It should be understood that attached drawing is schematical, and the scope of protection of the present invention is not limited, protection of the invention
Range is defined by the appended claims.
The semiconductor device cell of an exemplary embodiment of the present invention is described referring initially to Fig. 1.As shown in Figure 1, half
Conductor device unit includes the substrate 100 of the first conduction type, and first of the first conduction type in the substrate 100 is mixed
Miscellaneous area 110；Second doped region 120 of the second conduction type in the substrate 100；In the substrate 100
The third doped region 130 of two conduction types；Isolation structure 160 is used to be isolated first doped region 110 and described second and mixes
Miscellaneous area 120 and first doped region 110 and the third doped region 130；Described is sequentially located in the substrate 100
4th doped region 140 of the first conduction type of three doped regions, 130 lower section and the 5th doped region 150 of the second conduction type；?
It is located at the trap of the second conduction type of described first, second and 110,120,150 lower section of the 5th doped region in the substrate 100
170；And n diode being connected in series with second doped region 120, n are the integer more than or equal to 0.
First doped region 110 is electrically connected to anode A, and the second doped region 120 is electrically connected to cathode K via n diode, and
And third doped region 130 is electrically connected to cathode K.From figure 1 it will be seen that there are two shunt circuits from anode A to cathode K: by
Anode A, the first doped region 110, trap 170, the second doped region 120, n diode and cathode K in turn switch on two poles to be formed
Circuit (path 1, show in figure 1A with solid arrow) is connected in pipe, and by anode A, the first doped region 110, trap the 170, the 5th
Doped region 150, the 4th doped region 140, third doped region 130 and cathode K in turn switch on the thyristor to be formed (that is, silicon-controlled
Circuit (path 2, in figure 1A with dotted arrow is connected in rectifier (Silicon Controller Rectifier, abbreviation SCR)
It shows).First doped region 110, the second doped region 120, third doped region 130 are heavily doped region.5th doped region 150 and trap
170 be identical doping type, and the 5th doped region 150 is also possible to a part of trap 170.
The work of device cell shown in figure 1A is described referring now to IV curve graph shown in Figure 1B.As shown in Figure 1B, when
After anode A entrance, path 1 first can take the lead in static electricity discharge the electrostatic pulse of enough energy.It is produced when by 1 static electricity discharge of path
After raw overshoot voltage or Clamping voltages is more than the unlatching threshold value in path 2, path 2 can also start static electricity discharge.As n=0,
The cut-in voltage of this device architecture unit is identical with conventional diode in 0.7V or so, but its outstanding advantages are identical
It is smaller than the capacitor of conventional diode under design area, because the capacitor in path 2 is the half of 1 capacitor of path.As long as therefore to the greatest extent
Amount designs the area in big path 2, designs the area in small path 1 as far as possible, then the capacitor of entire device cell will be than tradition
Diode wants small.Moreover, being compared with conventional diode, under same area, when two paths of the device cell are all turned on
Afterwards, their transient state IV characteristic is comparable (as shown in Figure 1B).In addition one is important advantage is that work as the device cell
In 0.5V forward bias, that is, in the state of being not turned on, electric leakage when positive bias is smaller than conventional diode, because on road
There are reverse-biased PN junction potential barriers to block electric leakage on diameter 2.
Standard CMOS process can be used according to the semiconductor device cell of the present embodiment to make.As n=0, if
Above-mentioned semiconductor device unit is used in the electrostatic protection of I/O port, then its work passes under reverse-biased to substitute
System diode.In the case where same area and identical static electricity discharge ability, the capacitor of semiconductor device cell is smaller, thus
It is more suitable the electrostatic protection of high-frequency radio frequency (RF) circuit.Work as n > 0, such as when n=3, if above-mentioned semiconductor device unit work
Make at forward bias 1.2V, forward direction electric leakage is smaller than conventional diode string, that is to say, that in the semiconductor device cell in core
Piece is not turned on when working normally, and is temporarily just opened in electrostatic pulse, the power consumption of chip can be made smaller in this way.
Isolation structure 160 can use such as shallow trench isolation (Shallow Trench Isolation, STI), dioxy
(Oxide Isolation) structure or field oxidation isolation (Field Oxide Isolation) structure etc. is isolated in SiClx,
But be not restricted to that these examples lifted.
Fig. 2 shows the schematic cross-sections of semiconductor device cell in accordance with an alternative illustrative embodiment of the present invention
Figure.Semiconductor device cell shown in Fig. 2 and semiconductor device cell shown in figure 1A the difference is that, isolation structure packet
It includes between the first doped region 210 and the second doped region 220 between the first doped region 210 and third doped region 230 and is formed
Gate structure 260 on 200 surface of substrate.Gate structure 260 and the first doped region 210 are electrically connected to anode A, the second doping
Area 220 is electrically connected to cathode K via n diode, and third doped region 230 is electrically connected to cathode K.Doped region 250 and 270
It is identical doping type, 250th area are also possible to a part of trap 270.
The advantages of being isolated using gate structure 260 is isolated compared to STI, the opening speed of device cell faster, therefore more
Add suitable for the electrostatic impact for protecting chip from arriving Charged Device Model (Charged Device Model, CDM).CDM
The electrostatic of mode compared to manikin (human body model, HBM) and machine mould (Machine Model, MM) and
Speech, rising edge of a pulse is shorter, it requires that electrostatic protection device will have the opening speed more accelerated.
It should be pointed out that first conduction type is p-type although addressing in embodiment as described below upper, second is led
Electric type is N-shaped, but it is to be understood that in other examples, the first conduction type can be N-shaped, the second conduction type can be with
It is p-type.
Fig. 3 shows the schematic cross-section of semiconductor device cell in accordance with a further exemplary embodiment of the present invention
Figure.Compared to semiconductor device cell shown in Figure 1A, in semiconductor device cell shown in Fig. 3, the second doped region
320 and third doped region 330 share, and wherein the 4th doped region 340 and the 5th doped region 350 on 300 surface of substrate
First upright projection falls into shared second/third doped region 320/330 in the second upright projection on 300 surface of substrate,
Area of the area of first upright projection less than the second upright projection.Trap 370 and shared second/third doped region 320/330
Bottom a part and the 5th doped region 350 bottom at least part contact.Semiconductor devices list shown in Fig. 3
In member, n=0, i.e. the second doped region 320 are not connect with additional diode.
As seen from Figure 3, still there are two shunt circuits from anode A to cathode K: by anode A, the first doped region
310, trap 370, second/third doped region 320/330 and cathode K in turn switch on the diode current flow circuit to be formed (path 1,
Shown in Fig. 3 with solid arrow), and adulterated by anode A, the first doped region 310, trap 370, the 5th doped region the 350, the 4th
Area 340, third doped region 330 and cathode K in turn switch on the turn on thyristors circuit (path 2, with dotted line in Fig. 3 to be formed
Arrow is shown).Doped region 350 and 370 is identical doping type, and 350th area are also possible to a part of trap 370.
Compared to Figure 1A, the area of semiconductor device cell shown in Fig. 3 reduces, therefore the capacitor of the device cell subtracts
It is small, thus it is more suitable the electrostatic protection of high-frequency radio frequency (RF) circuit.
It should be pointed out that the isolation structure 360 in Fig. 3 can be fleet plough groove isolation structure, silica isolation structure,
Or field oxidation isolation structure, naturally it is also possible to including gate structure as shown in Figure 2.
Fig. 4 A shows the schematic cross section of the semiconductor devices of an exemplary embodiment of the present invention.Such as Fig. 4 A
Shown, semiconductor devices includes that the x that is connected in series semiconductor device cell cell1 and y as shown in Figure 1A the second half are led
Body device cell cell2.Second semiconductor device cell cell2 includes: substrate 4200；First in substrate 4200 is conductive
First doped region 4210 of type；Second doped region 4220 of the second conduction type in substrate 4200；Isolation structure
4260, it is used to be isolated the first doped region 4210 and the second doped region 4220；The second doped region is sequentially located in substrate 4200
The third doped region 4230 of first conduction type of 4220 lower sections and the 4th doped region 4240 of the second conduction type；In substrate
It is located at first, second and the 4th doped region 4210 in 4200, the trap 4270 of the second conduction type of 4220,4240 lower sections, and
Wherein x and y is the integer more than or equal to 1.
In semiconductor devices shown in Figure 4 A, x cell1 unit y cell2 unit of series connection will will form and be suitable for
Use the electrostatic protection component between multiple VDD and VSS.Cell1 is semiconductor device cell as shown in Figure 1A, cell2
It is vertical PNP N thyristor.The cut-in voltage of the thyristor of this vertical structure is between 3-5V, and hysteresis voltage is in 1.5V or so.
If the thyristor of this vertical structure is directly used between VDD (> 1.5V) and VSS as electrostatic protection component, can lead
The generation for causing valve lock effect, because hysteresis voltage cannot be below VDD.When x cell1 unit series connection y as shown in Figure 4 A
It, can be to avoid vertical PNP N thyristor when the semiconductor devices of cell2 unit is as electrostatic protection component between VDD and VSS
The problem of being easy to valve lock in VDD > 1.5V.Such semiconductor devices can form one by adjusting the numerical value of x, y and n
Serial electrostatic protection component, and there is no the case where valve lock in VDD > 1.5V.
Work as y=1, when x=2, n=2, as shown in Figure 4 B, the maximum trigger voltage of semiconductor devices is minimum in 8.6V or so
Hysteresis maintenance voltage is in 5.4V or so.Therefore, the semiconductor devices can be used the VDD and VSS of 5V and 3.3V voltage it
Between for the direct impulse electrostatic between VDD to VSS of releasing.
Work as y=1, when x=1, n=2, as shown in Figure 4 C, the maximum trigger voltage of semiconductor devices is minimum in 6.5V or so
Hysteresis maintenance voltage is in 3.4V or so.Therefore, which can be used the voltage VDD and VSS in 3.3V and 2.5V
Between for the direct impulse electrostatic between VDD to VSS of releasing.
Work as y=1, when x=1, n=1, as shown in Figure 4 B, the maximum trigger voltage of semiconductor devices is minimum in 5.3V or so
Hysteresis maintenance voltage is in 2.2V or so.Therefore, the semiconductor devices can be used 1.2V and 1.8V voltage VDD and VSS it
Between for the direct impulse electrostatic between VDD to VSS of releasing.
The semiconductor devices that x cell1 unit y cell2 unit of series connection as shown in Figure 4 A is formed is more in addition to being suitable for
Outside electrostatic protection between a VDD and VSS, another important advantage is electric leakage when being not turned on compared with the biography under same area
System diode wants small, because stopping to leak electricity there are reverse-biased PN junction potential barrier on entire static electricity discharge current path.It is such quiet
Power consumption of the electric guard assembly when being applied in chip is smaller.In addition, compared to the electrostatic detection circuit touching being widely used at present
Send out the scheme that leakage device is opened, such semiconductor devices, due to not needing design electrostatic detection circuit, so letting out identical
Under electrostatic discharge ability, chip area will be greatlyd save.
It should be pointed out that semiconductor device cell cell1 shown in Fig. 4 A is not limited to device cell shown in Figure 1A,
But can use any semiconductor device cell according to an embodiment of the present invention, such as Fig. 2, it is shown in Fig. 3 like that.
It should also be noted that the isolation structure 4260 of the second semiconductor device cell cell2 can be shallow trench isolation
Structure, silica isolation structure or field oxidation isolation structure.
Alternatively, as shown in figure 5, semiconductor device cell cell1 is semiconductor device cell as shown in Figure 2, and
And second semiconductor device cell cell2 isolation structure be included between the first doped region 4210 and the second doped region 4220,
And it is formed in the gate structure 4260 on 4200 surface of substrate.Gate structure 4260 and the first doped region 4210 are electrically connected to anode
A2, and the second doped region 4220 is electrically connected to cathode K2.In other embodiments, semiconductor device cell cell1 can also
To be the semiconductor device cell as described in Fig. 1 or Fig. 3, specific embodiment please refers to the specific implementation of Fig. 1 above and Fig. 3
The explanation of example.
Fig. 6 shows the schematic circuit of the circuit structure unit of an exemplary embodiment of the present invention.Such as Fig. 6 institute
Showing, circuit structure unit includes input terminal Input, output end Output, the first power supply line VDD, second source line VSS, and
Be separately positioned between input terminal Input and the first power supply line VDD, between input terminal Input and second source line VSS, output
It holds as described above any between Output and the first power supply line VDD, between output end Output and second source line VSS
Kind semiconductor device cell (is shown in Fig. 6 with circular dashed line frame, wherein arrow indicates electrostatic leakage direction), and setting exists
Any semiconductor devices as described above between first power supply line VDD and second source line VSS is (with square in Fig. 6
Shape dotted line frame is shown, and wherein arrow indicates electrostatic leakage direction).Core circuit CC is clipped between two-stage buffer.
Shown in fig. 6 is basic full chip electrostatic protectiving scheme mentality of designing.It needs to design in the periphery core circuit CC
Electrostatic discharge protection circuit.It is therein any all to generate between the two for input terminal Input, output end Output, VDD and VSS
Positive or negative pulse electrostatic induced current, therefore low-impedance path of releasing should be all designed between the two any, thus by electrostatic electricity
It flows and runs out, without allowing electrostatic induced current to enter in core circuit CC, and then destroy the gate oxide etc. of core circuit CC.?
In the case that chip works normally, electrostatic discharge protection circuit is not turned on, and its electric leakage generated is small, brought parasitism
The parameters such as capacitor are also small, and have lower impedance so as to bigger grade of releasing preferably under certain design area
Electrostatic induced current.
The first order Electrostatic Protection Design of the full chip of single supply can be completed by above-mentioned design, but the design can only be prevented
Only chip is hit from the electrostatic of HBM and MM mode, and the CDM mode electrostatic strike shorter for pulse, intensity is bigger, is needed
Design the faster second level electrostatic protection device of opening speed.In general, the device of usually prevention CDM mode electrostatic strike is set
Meter is at input port Input.Specifically, concatenated ballast is designed after first order electrostatic protection device (circular dashed line frame)
Resistance R and the fast opener part that bi-directional electrostatic electric current is released can be carried out to VDD and VSS.As shown in fig. 6, the electricity in Fig. 6
Line structure unit further include be separately positioned between input terminal Input and the first power supply line VDD, input terminal Input and second electricity
The semiconductor device cell as described above of reverse parallel connection between the line VSS of source and semiconductor devices as described above (
It is shown in Fig. 6 with oval dotted line frame, wherein arrow indicates electrostatic leakage direction).
It should be pointed out that the isolation junction of semiconductor device cell and semiconductor devices in the electrostatic protection device of the second level
Structure should include gate structure, that is to say, that semiconductor device cell in the electrostatic protection device of the second level in Fig. 6 and partly lead
Body device difference is as shown in Figure 2 and Figure 5.In operation, from input terminal Input to the positive pulse CDM mode of the first power supply line VDD
It electrostatic and can partly be led from as shown in Figure 2 A from second source line VSS to the positive pulse CDM mode electrostatic of input terminal Input
Body device cell is released (as to shown in upward arrow)；Negative pulse CDM mode from from input terminal Input to the first power supply line VDD is quiet
Electricity and can be from semiconductor as shown in Figure 5 from second source line VSS to the negative pulse CDM mode electrostatic of input terminal Input
Device is released (as shown by the downward arrows), is released assembling device to form two-way rapid electrostatic.
Fig. 7 shows the schematic circuit of the circuit structure of an exemplary embodiment of the present invention.As shown in fig. 7,
Circuit structure includes multiple foregoing circuit structural units 700, and the reverse parallel connection being arranged between circuit structure unit 700
Above-mentioned semiconductor device unit 710.It is substituted by using the semiconductor device cell that the embodiment of the present invention is proposed traditional
Diode can make electric leakage of the electrostatic protection device when being not turned on more as the electrostatic protection device between circuit structure unit
It is small, thus the power consumption of entire chip is lower.
Fig. 8 shows the schematic circuit of the circuit system of an exemplary embodiment of the present invention.As shown in figure 8,
Circuit system includes multiple foregoing circuit structural unit 801-80m, a plurality of electrostatic protection bus ESD BUS 1-3 and setting
Between the first power supply line VDDm and corresponding electrostatic protection bus ESD BUS of circuit structure unit, circuit structure unit
It is anti-between second source line VSSm and corresponding electrostatic protection bus ESD BUS and between electrostatic protection bus ESD BUS
To above-mentioned semiconductor device unit or above-mentioned semiconductor device in parallel.According to circuit system as shown in Figure 8, SoC chip
Any one pin can form Low ESR electrostatic leakage path with an any other pin, thus static electricity discharge electric current,
It avoids breaking internal core circuit.
Although describing the present invention referring to each of the above exemplary embodiments, the present invention is not only limited
In the structure and function of each of the above exemplary embodiments, it is intended that the scope of the present invention be defined by the claims appended hereto.It closes
In structure and details of the invention, the variations and modifications that can be expected using those skilled in the art.In addition, the present invention
A part or integral part and the structure that obtains including being appropriately combined each in the above exemplary embodiments.
Claims (16)
1. a kind of semiconductor device cell characterized by comprising
Substrate；
First doped region of the first conduction type in the substrate；
Second doped region of the second conduction type in the substrate；
The third doped region of the second conduction type in the substrate；
Isolation structure is used to be isolated first doped region and second doped region and first doped region and described
Third doped region；
The 4th doped region and second for being sequentially located at the first conduction type below the third doped region in the substrate is led
5th doped region of electric type；And
It is located at the trap of described first, second and the 5th the second conduction type below doped region in the substrate；And
N diode being connected in series with second doped region, wherein n is the integer more than or equal to 0；
First doped region, trap, the 5th doped region, the 4th doped region and third doped region in turn switch on the turn on thyristors to be formed
Circuit.
2. semiconductor device cell according to claim 1, which is characterized in that wherein the isolation structure be shallow trench every
From structure.
3. semiconductor device cell according to claim 1 or 2, which is characterized in that wherein the isolation structure is dioxy
SiClx isolation structure or field oxidation isolation structure.
4. semiconductor device cell according to claim 1, which is characterized in that wherein the isolation structure is included in described
Between first doped region and the third doped region and the lining is formed between first doped region and the second doped region
Gate structure on bottom surface, the semiconductor device cell further include anode and cathode, the gate structure and described first
Doped region is electrically connected to the anode, and second doped region is electrically connected to the cathode, and institute via the n diode
It states third doped region and is electrically connected to the cathode.
5. semiconductor device cell according to claim 1, which is characterized in that wherein, first conduction type is p
Type, second conduction type are N-shaped, and the substrate has first conduction type.
6. semiconductor device cell according to claim 1, which is characterized in that wherein second doped region and third are mixed
Miscellaneous area shares, and wherein the 4th doped region and first upright projection of the 5th doped region on the substrate surface are fallen into
Shared second/third doped region is in the second upright projection on the substrate surface, first upright projection
Area is less than the area of second upright projection；And
The bottom of a part and the 5th doped region of the bottom of the trap and shared second/third doped region
At least part contacts.
7. a kind of semiconductor devices characterized by comprising
X semiconductor device cell and y of any of claims 1-6 the second semiconductor devices lists of series connection
Member；
Wherein, second semiconductor device cell includes:
Substrate；
First doped region of the first conduction type in the substrate；
Second doped region of the second conduction type in the substrate；
Isolation structure is used to be isolated first doped region and second doped region；
The third doped region and second for being sequentially located at the first conduction type below second doped region in the substrate are led
4th doped region of electric type；And
It is located at the trap of described first, second and the 4th the second conduction type below doped region in the substrate；
Wherein, x and y is the integer more than or equal to 1.
8. semiconductor devices according to claim 7, which is characterized in that wherein x=2, y=1, and n=2；Or x=
1, y=1, and n=2；Or x=1, y=1, and n=1.
9. semiconductor devices according to claim 7, which is characterized in that wherein second semiconductor device cell every
It is fleet plough groove isolation structure from structure.
10. the semiconductor devices according to claim 7 or 9, which is characterized in that wherein second semiconductor device cell
Isolation structure be silica isolation structure or field oxidation isolation structure.
11. semiconductor devices according to claim 7, which is characterized in that the isolation of second semiconductor device cell
Structure includes the gate structure between first doped region and the second doped region and being formed on the substrate surface, institute
Stating the second semiconductor device cell further includes anode and cathode, the gate structure of second semiconductor device cell and its first
Doped region is electrically connected to the anode, and the second doped region of second semiconductor device cell is electrically connected to the yin
Pole.
12. semiconductor devices according to claim 7, which is characterized in that wherein, second semiconductor device cell
First conduction type is p-type, and second conduction type is N-shaped, and the substrate has first conduction type.
13. a kind of circuit structure unit, which is characterized in that including input, output end, the first power supply line, second source line, with
And be separately positioned between input terminal and the first power supply line, between input terminal and second source line, output end and the first power supply line
Between, the semiconductor device cell of any of claims 1-6 between output end and second source line, and setting
Semiconductor devices described in any one of claim 7-12 between the first power supply line and second source line.
14. circuit structure unit according to claim 13, which is characterized in that further include being separately positioned on input terminal and
The of any of claims 1-6 of reverse parallel connection between one power supply line, between input terminal and second source line is partly led
Semiconductor devices described in any one of body device cell and claim 7-12.
15. a kind of circuit structure, which is characterized in that including circuit structure unit described in multiple claims 13 or 14, and
The semiconductor device cell of any of claims 1-6 of reverse parallel connection between circuit structure unit is set.
16. a kind of circuit system, which is characterized in that including circuit structure unit described in multiple claims 13 or 14, a plurality of
Electrostatic protection bus and it is arranged between the first power supply line of circuit structure unit and corresponding electrostatic protection bus, circuit
Reverse parallel connection between the second source line of structural unit and corresponding electrostatic protection bus and between electrostatic protection bus
Semiconductor device described in any one of semiconductor device cell of any of claims 1-6 or claim 7-12
Part.
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