CN102082183A - Device and system for electrostatic discharge protection - Google Patents
Device and system for electrostatic discharge protection Download PDFInfo
- Publication number
- CN102082183A CN102082183A CN2010105174302A CN201010517430A CN102082183A CN 102082183 A CN102082183 A CN 102082183A CN 2010105174302 A CN2010105174302 A CN 2010105174302A CN 201010517430 A CN201010517430 A CN 201010517430A CN 102082183 A CN102082183 A CN 102082183A
- Authority
- CN
- China
- Prior art keywords
- silicon
- trap
- controlled device
- electrostatic discharge
- esd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 26
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 abstract description 8
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 230000014509 gene expression Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides a bidirectional silicon-controlled electrostatic discharge (ESD) protective device and a bidirectional silicon controlled EDS protective system, which are used for integrated circuit ESD protection. The ESD protective device is a silicon-controlled rectifier (SCR) device with two ports (A and K), has a five-layer (N1P2N3P4N5) structure which comprises one PNP triode, two NPN triodes and series parasitic resistors, and comprises two built-in N-channel metal oxide semiconductor (NMOS) tube devices for lowering the start voltage of the device. Compared with the traditional system using unidirectional electrostatic discharge protective devices, the novel electrostatic discharge protective system using the devices is only required to use a half number of the electrostatic discharge protective devices on every input/output (I/O) pin, and only two types of devices are arranged at an input end or an output end respectively, and are connected with a power end and a ground end respectively, so that full chip electrostatic protection is performed on a protected circuit.
Description
Technical field
The present invention relates to integrated circuit is provided the technology of static discharge (ESD, ElectroStatic Discharge) protection.
Background technology
Will produce the ESD phenomenon when two object collisions or separation, promptly static electric charge is transferred to another object from an object.The discharge capacity of ESD and discharge period are depended on the type of object and multiple factors such as environment on every side, when semiconductor device generation ESD and ESD produce sufficiently high energy in the integrated circuit, will cause the damage of semiconductor device.
Esd protection circuit is that to prevent in the chip design that ESD from produce damaging circuit to be protected used, usually esd protection circuit be subjected to its protective circuit in parallel.When the ESD phenomenon takes place; esd protection circuit will be opened; electrostatic induced current that ESD the emits overwhelming majority can be by this esd protection circuit ground of releasing, and just flows through protected circuit on a small quantity and can not damage protected circuit, thereby play the effect of effective protection circuit to be protected.Generally, ESD takes place in chip exterior, and the static of its generation flow to the pin of the integrated circuit (IC, Integrated Circuit) in the chip via the chip exterior pin, and the pin by IC discharges into ground again.
At present, be lower than the integrated circuit esd protection circuit design of 100nm characteristic size, particularly there are problems in the esd protection circuit design at radio circuit and analog to digital mixed signal circuit as current IC reliability design.At first, have a strong impact on because the body parameters (mainly being parasitic capacitance and noise parameter) that esd protection circuit is introduced can cause circuit performance, therefore need exploitation new have low ghost effect, a high performance electrostatic preventing structure.Secondly; Chang Yong electrostatic preventing structure more now; comprise metal-oxide-semiconductor device, diode, triode and silicon-controlled device (SCR; Silicon-Controlled Rectifier), silicon-controlled device has the I-V characteristic of its dark resilience (snapback), high protection efficient and advantages such as small size and low ghost effect.Yet the cut-in voltage of common silicon-controlled device very high (approximately 20V), can't be applied in the CMOS integrated circuit of low supply voltage now and go, there are some to use the cut-in voltage of the silicon-controlled device of external trigger circuit can reach 7.5V to 10V, still are higher than needed standard.Simultaneously, use traditional unidirectional esd protection device, at an I/O port, need nearly 4 identical esd protection devices, this introduces the influence of parasitic parameter to circuit performance with deterioration of device.Therefore, need a kind of esd protection device and system that can satisfy the low trigger voltage of advanced CMOS integrated circuit esd protection, low ghost effect and bidirectional opening, effective esd protection is provided.
Summary of the invention
The embodiment of the invention provides a kind of esd protection system that is used for the bidirectional triode thyristor device architecture of integrated circuit esd protection and comprises this device architecture, satisfies the esd protection device and the system of the low trigger voltage of advanced CMOS integrated circuit esd protection, low ghost effect and bidirectional opening.
The invention provides the bidirectional triode thyristor device architecture, comprise two P traps that separate by insulating barrier, a nmos device is respectively arranged in each P trap, have the bidirectional opening end.
Optionally, described device substrate is the P type.
Optionally, described device has N trap and the common isolation layer of setting up of the insulating barrier above the N trap by dark N trap and both sides.
Optionally, the grid in the middle of inner N+ source region of P trap and the N trap top N+ constitutes built-in nmos device together.
Optionally, in each P trap, N+ source region and P+ source region have common lead to lead to opening end.
The undergraduate course invention also provides a kind of esd protection system that is used for the full chip of integrated circuit, comprises silicon-controlled device described in 4 claims 1.
Optionally, in the described system, first silicon-controlled device is connected between input and the earth terminal, second silicon-controlled device is connected between output and the earth terminal, the 3rd silicon-controlled device is connected between input and the power voltage terminal, and the 4th silicon-controlled device is connected between output and the power voltage terminal.
Optionally, described 4 silicon-controlled devices and protected circuit module shared grounding end.
Description of drawings
Fig. 1 is the transversal sectional schematic diagram of bidirectional triode thyristor esd protection device in the embodiment of the invention;
Fig. 2 is the schematic equivalent circuit of bidirectional triode thyristor esd protection device in the embodiment of the invention;
Fig. 3 is the full chip electrostatic protection system schematic diagram that uses bidirectional triode thyristor esd protection device in the embodiment of the invention;
Embodiment
Fig. 1 is the transversal sectional schematic diagram that is used for the bidirectional triode thyristor esd protection device of integrated circuit esd protection in the embodiment of the invention.The transversal sectional schematic diagram of this device is totally with label 100 expressions.This device is to be based upon on the P type substrate (101), and is structured in by a dark N trap (102) and on every side in the N trap (112) and isolated space that insulating barrier (113) impales jointly of vertical direction.N+ source region (106) by a N trap (104) and N trap top in the middle of interior volume is two blocks of P traps (103) with space segmentation, in each P trap, each has again and is insulated P+ source region (107) and N+ source region (105) that layer (113) branch comes.P trap (103) interior N+ source region (105) and N trap (104) N+ source region (106), top and middle raceway groove and grid level have together constituted built-in nmos device (108 and 109).N+ source region (105) in the middle of each P trap (103) and P+ source region (107) are connected to form device by plain conductor an end A (110) or K (111).
Fig. 2 is the equivalent circuit diagram of bidirectional triode thyristor esd protection device in the embodiment of the invention.It is totally with label 200 expressions.The device equivalence is a circuit structure of holding (202) from A end (201) to K, wherein is divided into five layers of N+/Pwell/Nwell/Pwell/N+.Comprise a PNP triode Q1 (205), two NPN triode Q2 (206) and Q3 (207), four series resistance R1 (208), R2 (209), R3 (210), R4 (211), and two built-in NMOS pipe M1 (203) and M2 (204).
Hold (201) when one when the forward Electrostatic Discharge pulse of K end (202) occurs from A, it incites somebody to action the anti-collector electrode of Q1 (205) partially (dark N trap (102)/P trap (103)) until puncture, the avalanche current that causes after the puncture is held (202) through R2 (209) to K, promote the electromotive force of Q3 (207) base stage simultaneously, thereby open Q3 (207) and Q1 (205) simultaneously.Equally, when the pulse of a forward Electrostatic Discharge is held (201) from K end (202) to A, Q1 (205) and Q2 (206) will be unlocked discharge electrostatic charges.Can obtain the Electrostatic Discharge protection device of a bidirectional opening thus.In device, we have added the cut-in voltage Vt1 that two nmos device M1 (203) and M2 (204) further reduce silicon-controlled device.Different with traditional controllable silicon trigger mechanism, our bidirectional triode thyristor device uses the channel punchthrough effect further to reduce the cut-in voltage Vt1 of device.Press the breakdown potential of tying more than Nwell/Pwell to force down because the raceway groove of device passes energising, therefore can access a low-down puncture voltage; Simultaneously, can further reduce cut-in voltage by connecting A end (201) (or K end (202)) and the grid level of M2 (204) (or M1 (203)).
Figure 3 shows that full chip esd protection system on the sheet of bidirectional triode thyristor esd protection device of specific embodiment among the present invention, this overall system is with label 300 expressions.System comprises the input (301) and the output (302) of a signal, is respectively applied for to protected circuit module (307) transmission input and output data.4 bidirectional triode thyristor Electrostatic Discharge protection devices (303-306) connect the earth terminal and the power voltage terminal of protected circuit module (307) from input port (301)/output port (302) respectively, constitute full chip electro-static discharge (ESD) protection system that can both carry out the Electrostatic Discharge protection between any two ports.
Because the characteristic of bidirectional triode thyristor Electrostatic Discharge protection device bidirectional opening, the Electrostatic Discharge electric current can be from any direction by this device.Therefore when the Electrostatic Discharge pulse of a forward appears between any two ports, such as, appear at from input port (301) to the output port (302), can flow through bidirectional triode thyristor device (303) and (305) or (304) and (306) of Electrostatic Discharge electric current is released into output (302) from input (301); Equally, when the Electrostatic Discharge pulse of a forward appears at from output port (302) to the output port (301), also can flow through bidirectional triode thyristor device (303) and (305) or (304) and (306) of Electrostatic Discharge electric current is released into input (301) from output (302).Thereby finish full chip electro-static discharge (ESD) the protection design of entire chip.
The one of ordinary skilled in the art all can understand, and a kind of Electrostatic Discharge protection device of the present invention has the characteristic of low turn-on voltage Vt1, high electrostatic discharge (ESD) protective capability, low parasitic parameter (parasitic capacitance and noise factor) and bidirectional opening.Electrostatic Discharge protection system of the present invention has advantages such as the device of saving usage quantity, low parasitic parameter, can be used in the Electrostatic Discharge protection of high performance radio circuit of design and analog to digital hybrid circuit.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (8)
1. a silicon-controlled device structure that is used for the integrated circuit esd protection comprises two P traps that separated by insulating barrier, and a nmos device is respectively arranged in each P trap, it is characterized in that having the bidirectional opening end.
2. silicon-controlled device structure as claimed in claim 1 is characterized in that, described device substrate is the P type.
3. silicon-controlled device as claimed in claim 1 or 2 is characterized in that, described device has by the N trap on dark N trap and both sides and the common isolation layer of setting up of the insulating barrier above the N trap.
4. silicon-controlled device as claimed in claim 3 is characterized in that, the grid in the middle of inner N+ source region of P trap and the N trap top N+ constitutes built-in nmos device together.
5. silicon-controlled device as claimed in claim 4 is characterized in that, in each P trap, N+ source region and P+ source region have common lead to lead to opening end.
6. an esd protection system that is used for the full chip of integrated circuit is characterized in that, comprises silicon-controlled device described in 4 claims 1.
7. esd protection as claimed in claim 6 system; it is characterized in that; wherein first silicon-controlled device is connected between input and the earth terminal; second silicon-controlled device is connected between output and the earth terminal; the 3rd silicon-controlled device is connected between input and the power voltage terminal, and the 4th silicon-controlled device is connected between output and the power voltage terminal.
8. esd protection as claimed in claim 7 system is characterized in that described 4 silicon-controlled devices and protected circuit module shared grounding end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105174302A CN102082183A (en) | 2010-10-22 | 2010-10-22 | Device and system for electrostatic discharge protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105174302A CN102082183A (en) | 2010-10-22 | 2010-10-22 | Device and system for electrostatic discharge protection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102082183A true CN102082183A (en) | 2011-06-01 |
Family
ID=44088031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105174302A Pending CN102082183A (en) | 2010-10-22 | 2010-10-22 | Device and system for electrostatic discharge protection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102082183A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522404A (en) * | 2011-12-30 | 2012-06-27 | 无锡新硅微电子有限公司 | Bidirectional SCR ESD protective circuit for low triggered voltage |
| CN104752417A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Silicon controlled rectifier protection device and forming method thereof |
| CN106298902A (en) * | 2012-11-20 | 2017-01-04 | 美国亚德诺半导体公司 | Junction isolation blocking voltage device with integrated protection structure and forming method thereof |
| CN109103183A (en) * | 2018-08-24 | 2018-12-28 | 电子科技大学 | Two-way high maintenance electric current SCR device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101048867A (en) * | 2004-08-26 | 2007-10-03 | 德州仪器公司 | Bi-directional ESD protection circuit |
| US20090032838A1 (en) * | 2007-07-31 | 2009-02-05 | Tseng Tang-Kuei | Symmetric bidirectional silicon-controlled rectifier |
| US20090236631A1 (en) * | 2008-03-20 | 2009-09-24 | Wen-Yi Chen | Bidirectional PNPN silicon-controlled rectifier |
| CN101807598A (en) * | 2010-03-17 | 2010-08-18 | 浙江大学 | PNPNP type triac |
| CN101816069A (en) * | 2007-10-08 | 2010-08-25 | 英特赛尔美国股份有限公司 | Tunable voltage isolation ground to ground ESD clamp |
-
2010
- 2010-10-22 CN CN2010105174302A patent/CN102082183A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101048867A (en) * | 2004-08-26 | 2007-10-03 | 德州仪器公司 | Bi-directional ESD protection circuit |
| US20090032838A1 (en) * | 2007-07-31 | 2009-02-05 | Tseng Tang-Kuei | Symmetric bidirectional silicon-controlled rectifier |
| CN101816069A (en) * | 2007-10-08 | 2010-08-25 | 英特赛尔美国股份有限公司 | Tunable voltage isolation ground to ground ESD clamp |
| US20090236631A1 (en) * | 2008-03-20 | 2009-09-24 | Wen-Yi Chen | Bidirectional PNPN silicon-controlled rectifier |
| CN101807598A (en) * | 2010-03-17 | 2010-08-18 | 浙江大学 | PNPNP type triac |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102522404A (en) * | 2011-12-30 | 2012-06-27 | 无锡新硅微电子有限公司 | Bidirectional SCR ESD protective circuit for low triggered voltage |
| CN102522404B (en) * | 2011-12-30 | 2013-09-18 | 无锡新硅微电子有限公司 | Bidirectional SCR ESD protective circuit for low triggered voltage |
| CN106298902A (en) * | 2012-11-20 | 2017-01-04 | 美国亚德诺半导体公司 | Junction isolation blocking voltage device with integrated protection structure and forming method thereof |
| CN106298902B (en) * | 2012-11-20 | 2019-10-18 | 美国亚德诺半导体公司 | Junction isolation blocking voltage device with integrated protection structure and forming method thereof |
| CN104752417A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Silicon controlled rectifier protection device and forming method thereof |
| CN104752417B (en) * | 2013-12-30 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | Controllable silicon electrostatic protection device and forming method thereof |
| CN109103183A (en) * | 2018-08-24 | 2018-12-28 | 电子科技大学 | Two-way high maintenance electric current SCR device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6765771B2 (en) | SCR devices with deep-N-well structure for on-chip ESD protection circuits | |
| CN202549831U (en) | An electrostatic discharge protector and a system composed thereof | |
| US7869175B2 (en) | Device for protecting semiconductor IC | |
| CN104269399A (en) | Antistatic protection circuit | |
| CN102148499A (en) | CDM (Charged Device Model) ESD (Electro-Static Discharge) protection circuit | |
| CN106229962B (en) | A kind of power source reverse connection protection circuit | |
| CN102082183A (en) | Device and system for electrostatic discharge protection | |
| CN103165600A (en) | Electro-static discharge (ESD) protective circuit | |
| CN100470804C (en) | A protection circuit for constructing ESD release channel with the polycrystalline silicon | |
| CN109449156A (en) | A kind of port static release protection circuit | |
| CN111129006B (en) | Bidirectional low-trigger-voltage ESD protection structure for SOI (silicon on insulator) intelligent power integrated circuit | |
| CN101257018A (en) | Electrostatic protection circuit with discrete polycrystal gate structure | |
| CN103730458B (en) | Thyristor | |
| CN102270658B (en) | Low-trigger-voltage and low-parasitic-capacitance silicon controlled structure | |
| CN102544068B (en) | Bidirectional controllable silicon device based on assistant triggering of PNP-type triodes | |
| CN209045551U (en) | A kind of port static release protection circuit | |
| CN101814498B (en) | Structure with built-in NMOS auxiliary trigger controllable silicon | |
| CN101859766A (en) | Novel NMOS (N-channel Metal Oxide Semiconductor) clamping between power VDD (Voltage Drain Drain) and IO (Input/Output) pin and application method thereof | |
| CN111199971A (en) | Bidirectional-triggered ESD protection device | |
| CN102693980A (en) | Silicon controlled rectifier electro-static discharge protection structure with low trigger voltage | |
| CN205283121U (en) | Surge protection device | |
| CN101859767A (en) | High-voltage electrostatic protection device for full silicon metallizing process and corresponding production method thereof | |
| CN102244076B (en) | Electrostatic discharge protective device for radio frequency integrated circuit | |
| CN105097798A (en) | Esd protection device structure and system | |
| CN208848907U (en) | The diode triggered of Integrated circuit electrostatic protection is silicon-controlled |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20110601 |