CN111199971A - A Bidirectional Triggered ESD Protection Device - Google Patents
A Bidirectional Triggered ESD Protection Device Download PDFInfo
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- CN111199971A CN111199971A CN202010021515.5A CN202010021515A CN111199971A CN 111199971 A CN111199971 A CN 111199971A CN 202010021515 A CN202010021515 A CN 202010021515A CN 111199971 A CN111199971 A CN 111199971A
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- 230000002457 bidirectional effect Effects 0.000 title claims abstract description 70
- 230000001960 triggered effect Effects 0.000 title abstract description 13
- 239000003990 capacitor Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000002441 reversible effect Effects 0.000 claims abstract description 10
- 238000002513 implantation Methods 0.000 claims description 36
- 238000002955 isolation Methods 0.000 claims description 7
- 238000002347 injection Methods 0.000 description 23
- 239000007924 injection Substances 0.000 description 23
- 229910052710 silicon Inorganic materials 0.000 description 19
- 239000010703 silicon Substances 0.000 description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 230000000740 bleeding effect Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 150000003376 silicon Chemical class 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
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- 230000003071 parasitic effect Effects 0.000 description 1
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- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
- H10D89/713—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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Abstract
本发明涉及一种双向触发的ESD防护器件，包括：可控硅结构，包括：SOI衬底上设置的第一、第二PMOS管、以及双向三极管、第一、第二三极管；双向触发电路包括：串联的第一电阻、电容、第二电阻，以及第一、第二二极管；第一电阻的一端连接第一PMOS管的源极，另一端连接第一PMOS管的栅极，第二电阻的一端连接第二PMOS管的源极，另一端连接第二PMOS管的栅极；第一触发端通过反向的第一二极管连接双向三极管在第一方向上导通时的集电极，第一触发端还连接第一三极管的发射极；第二触发端通过反向的第二二极管连接双向三极管在第二方向上导通时的集电极，第二触发端连接第二三极管的发射极，在较低电压下触发双向SCR工作。
The invention relates to a bidirectionally triggered ESD protection device, comprising: a thyristor structure, including: first and second PMOS transistors, and bidirectional triodes, first and second triodes arranged on an SOI substrate; bidirectional triggering The circuit includes: a first resistor, a capacitor, a second resistor, and first and second diodes connected in series; one end of the first resistor is connected to the source of the first PMOS tube, and the other end is connected to the gate of the first PMOS tube, One end of the second resistor is connected to the source of the second PMOS transistor, and the other end is connected to the gate of the second PMOS transistor; The collector, the first trigger terminal is also connected to the emitter of the first triode; the second trigger terminal is connected to the collector of the bidirectional triode when the bidirectional transistor is conducting in the second direction through the reverse second diode, and the second trigger terminal Connect the emitter of the second triode to trigger the bidirectional SCR to work at a lower voltage.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to an ESD protection device for bidirectional triggering of an integrated circuit.
Background
Electrostatic Discharge (ESD) is a transient process in which a large amount of electrostatic charge is poured into an integrated circuit from the outside to the inside when a pin of the integrated circuit is floating, and the whole process takes about 1000 ns. High voltages of hundreds or even thousands of volts are generated during the electrostatic discharge of the integrated circuit, and the gate oxide of the input stage in the integrated circuit is broken down. With the progress of integrated circuit technology, the feature size of MOS transistors is smaller and smaller, and the thickness of gate oxide is thinner and thinner, and under this trend, it is very important to use a high performance ESD protection device to discharge electrostatic charges to protect the gate oxide.
The model of the ESD phenomenon is mainly four: a human body discharge model (HBM), a mechanical discharge model (MM), a device charging model (CDM), and an electric Field Induction Model (FIM). For general integrated circuit products, tests of a human body discharge model, a mechanical discharge model and a device charging model are generally performed. In order to be able to withstand such high esd voltages, integrated circuit products must typically use esd protection devices with high performance and high endurance.
With the rapid progress of SOI technology, ESD protection of SOI power integrated circuits has become a major reliability design issue. In SOI power integrated circuits, diodes, GGNMOS, SCRs, etc. may be used to act as ESD protection devices, with silicon controlled devices (SCRs) being one of the most efficient ESD protection devices.
Silicon Controlled Rectifier-SCR is widely used in power devices because it can switch between a high resistance state and a low resistance state and can be used as a power switch, but it is also a very effective ESD protection device, because its holding voltage is very low, it can withstand very high ESD current, therefore, SCR naturally has high ESD robustness. Compared with other ESD protection devices, the SCR device has the strongest ESD protection capability per unit area. Generally, the SCR device is a unidirectional ESD protection device (shown in fig. 1), and ESD protection in the other direction is performed by a parasitic diode or a diode connected in parallel. The layout area is increased by using an additional diode for ESD protection in the other direction. In some circuits with input ports needing to bear negative voltage, if the IO voltage is lower than-0.7V and the GND voltage is 0V, when the diode is used for reverse direction protection, the diode is conducted during normal operation, electric leakage is generated, and the protection performance is affected. Therefore, it has also been proposed to use a bi-directional SCR structure for protection.
However, the trigger voltage of the general SCR structure is too high, and the trigger voltage of a simple SCR is equivalent to the reverse breakdown voltage of a PN junction formed by an N-well P-well, and is between ten and several volts and several tens of volts, so that the high breakdown voltage forms effective ESD protection for internal circuit elements, because the internal circuit elements are damaged by the ESD pulse voltage before the SCR is turned on.
Therefore, how to effectively reduce the trigger voltage of the SCR device is a technical problem to be solved urgently.
Disclosure of Invention
In view of the above, the present invention has been developed to provide a dual triggered ESD protection device that overcomes, or at least partially solves, the above-mentioned problems.
The embodiment of the invention provides a bidirectional triggered ESD protective device, which comprises:
the silicon controlled rectifier comprises a silicon controlled rectifier structure and a bidirectional trigger circuit outside the silicon controlled rectifier structure;
the silicon controlled rectifier structure includes: the SOI substrate is provided with a first PMOS tube, a second PMOS tube, a bidirectional triode, a first triode and a second triode;
the bidirectional trigger circuit includes: the circuit comprises a first resistor, a capacitor, a second resistor, a first diode and a second diode;
the circuit comprises a first resistor, a capacitor and a second resistor, wherein the first resistor, the capacitor and the second resistor are sequentially connected in series, one end of the first resistor is connected with a source electrode of the first PMOS tube, the other end of the first resistor is connected with a grid electrode of the first PMOS tube, one end of the second resistor is connected with a source electrode of the second PMOS tube, and the other end of the second resistor is connected with a grid electrode of the second PMOS tube;
the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube and the base electrode of the bidirectional triode are connected, the base electrode of the first triode is connected with one end of the bidirectional triode when the bidirectional triode is conducted, and the base electrode of the second triode is connected with the other end of the bidirectional triode when the bidirectional triode is conducted;
the first trigger end is connected with a collector electrode of the bidirectional triode when the bidirectional triode is conducted in the first direction through the reversed first diode, and the first trigger end is also connected with an emitter electrode of the first triode;
and the second trigger end is connected with a collector electrode of the bidirectional triode when the bidirectional triode is conducted in the second direction through the reverse second diode, and is also connected with an emitting electrode of the second triode.
Further, the silicon controlled rectifier specifically includes:
arranging a first N well, a P well and a second N well which are sequentially arranged on the SOI substrate;
the first N well is sequentially provided with a first P + injection region, a second P + injection region, a first N + injection region and a third P + injection region at intervals, the P well is provided with a fourth P + injection region, and the second N well is sequentially provided with a fifth P + injection region, a second N + injection region, a sixth P + injection region and a seventh P + injection region at intervals;
the first P + injection region, the second P + injection region and the first N well form the second PMOS tube;
the sixth P + injection region, the seventh P + injection region and the second N well form the first PMOS tube;
the first N trap, the P trap and the second N trap form the bidirectional triode;
the third P + injection region, the first N well and the P well form the second triode, and the fifth P + injection region, the second N well and the P well form the first triode.
Further, the silicon controlled rectifier also includes:
a first deep trench isolation layer disposed outside the first N well;
and a second deep trench isolation layer disposed outside the second N well.
Further, the bidirectional triode is specifically an NPN-type triode, and the first triode and the second triode are both PNP-type triodes.
Further, if the electrostatic pulse is generated at the first trigger end, the first PMOS transistor is turned on, the triac is turned on in the first direction, and the first triac is turned on to form a first bleeding path.
Further, the first bleed-off path is specifically the fifth P + injection region, the second N well, the P well, the first N well, and the first N + injection region.
Further, if the second trigger end generates the electrostatic pulse, the second PMOS transistor is turned on, the triac is turned on in the second direction, and the second triac is turned on to form a second bleeding path.
Further, the second bleed-off path is specifically the third P + injection region, the first N well, the P well, the second N well, and the second N + injection region.
One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
the invention provides a bidirectional triggered ESD protective device, which comprises: outside bidirectional trigger circuit of silicon controlled rectifier structure and silicon controlled rectifier structure, this silicon controlled rectifier structure includes: first PMOS pipe, second PMOS pipe and bidirectional triode, first triode, the second triode that set up on the SOI substrate, this bidirectional trigger circuit includes: the circuit comprises a first resistor, a capacitor, a second resistor, a first diode and a second diode; the first resistor, the capacitor and the second resistor are sequentially connected in series, one end of the first resistor is connected with a source electrode of a first PMOS (P-channel metal oxide semiconductor) tube, the other end of the first resistor is connected with a grid electrode of the first PMOS tube, one end of the second resistor is connected with a source electrode of a second PMOS tube, the other end of the second resistor is connected with a grid electrode of the second PMOS tube, a drain electrode of the first PMOS tube, a drain electrode of the second PMOS tube and a base electrode of the bidirectional triode are connected, a base electrode of the first triode is connected with one end of the bidirectional triode when the bidirectional triode is conducted, and a base electrode of the second triode is connected with the; the first trigger end is connected with a collector electrode of the bidirectional triode when the bidirectional triode is conducted in the first direction through a reverse first diode, and the first trigger end is also connected with an emitting electrode of the first triode; the collector electrode when the second trigger end is connected with the bidirectional triode through the reverse second diode and conducted in the second direction, the emitter electrode of the second triode is further connected with the second trigger end, the symmetrical structure is adopted, bidirectional ESD protection is provided, extra diodes in parallel connection are not needed, the bidirectional SCR can be triggered to work under low voltage through the mode of adding the trigger circuit, ESD current is discharged, meanwhile, high voltage can be maintained, and the device is effectively prevented from entering a bolt-lock state.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a schematic structural diagram illustrating a conventional SCR device as a unidirectional ESD protection device;
fig. 2 shows a schematic structural diagram of a bidirectional trigger circuit of the bidirectional triggered ESD protection device in an embodiment of the present invention;
fig. 3 shows a schematic structural diagram of a bidirectional triggered ESD protection device in an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
An embodiment of the present invention provides a bidirectional triggered ESD protection device, as shown in fig. 2, including a Silicon Controlled Rectifier (SCR) structure and a bidirectional triggered circuit of the SCR.
This silicon controlled rectifier structure includes: the transistor comprises a first PMOS pipe MP1, a second PMOS pipe MP2, a bidirectional triode Q2, a first triode Q1 and a second triode Q3 which are arranged on an SOI substrate.
The bidirectional trigger circuit includes: the circuit comprises a first resistor R1, a capacitor C, a second resistor R2, a first diode D1 and a second diode D2.
The first resistor R1, the capacitor C and the second resistor R2 are sequentially connected in series, one end of the first resistor R1 is connected with the source electrode of the first PMOS tube MP1, the other end of the first resistor R1 is connected with the gate electrode of the first PMOS tube MP1, one end of the second resistor R2 is connected with the source electrode of the second PMOS tube MP2, and the other end of the second resistor R2 is connected with the gate electrode of the second PMOS tube MP 2.
The drain of the first PMOS transistor MP1, the drain of the second PMOS transistor M2, and the base of the triac Q2 are connected, the base of the first transistor Q1 is connected to one end of the triac Q2 when conducting, and the base of the second transistor Q3 is connected to the other end of the triac Q2 when conducting. Specifically, the base of the first transistor Q1 is connected to the emitter or collector of the triac Q2, e.g., the base of the second transistor Q3 is connected to the collector of the triac Q2 when the base of the first transistor Q1 is connected to the emitter of the triac Q2.
The first trigger terminal T1 is connected to the collector of the triac Q2 when conducting in the first direction through the inverted first diode D2, and the first trigger terminal T1 is also connected to the emitter of the first transistor Q1;
the second trigger terminal T2 is connected to the collector of the triac Q2 when conducting in the second direction through an inverted second diode D2, which is also connected to the emitter of the second transistor Q3.
Thereby obtaining the ESD protection device with the double-trigger circuit.
The resistance of the first resistor R1 and the second resistor R2 is 10K, and the capacitance of the capacitor C is 400 f.
In a specific embodiment, as shown in fig. 3, the SOI substrate includes: a silicon substrate 2011, a buried oxide layer 2012 and a top silicon layer 2013 from bottom to top.
Specifically, a first N well 301, a P well 302, and a second N well 303 are sequentially disposed on the SOI substrate, a first P + implantation region 3011, a second P + implantation region 3012, a first N + implantation region 3013, and a third P + implantation region 3014 are sequentially disposed at intervals in the first N well 301, a fourth P + implantation region 3021 is disposed in the P well 302, and a fifth P + implantation region 3031, a second N + implantation region 3032, a sixth P + implantation region 3033, and a seventh P + implantation region 3034 are sequentially disposed at intervals in the second N well 303.
The first P + implantation region 3011, the second P + implantation region 3012, and the first N well 301 form a second PMOS transistor MP 2; the sixth P + implantation region 3033, the seventh P + implantation region 3034, and the second N well 303 constitute a first PMOS transistor MP 1. The first N well 301, the P well 302, and the second N well 303 form the triac Q2, the third P + injection region 3014, the first N well 301, and the P well 302 form the second transistor Q3, and the fifth P + injection region 3031, the second N well 303, and the P well 302 form the first transistor Q1.
Therefore, the formation of a Silicon Controlled Rectifier (SCR) structure is realized, so that the electrostatic pulse is discharged, and a device is protected.
In a preferred embodiment, the thyristor further comprises: a first deep trench isolation TR disposed outside the first N-well 301, and a second deep trench isolation TR disposed outside the second N-well 303. The device can be isolated from other devices by all media by adopting the deep channel isolation layer, so that the electric leakage is greatly reduced.
In a specific embodiment, the triac Q2 is an NPN type transistor, and the first transistor Q1 and the second transistor Q3 are PNP type transistors.
The specific electrostatic pulse discharge principle is as follows:
if an electrostatic pulse is generated at the first trigger terminal T1, the first PMOS transistor MP1 is turned on, and the triac Q2 and the first transistor Q1 are turned on, thereby forming a first leakage path.
Specifically, when the electrostatic pulse is generated at the first trigger terminal T1, the source voltage of the first PMOS transistor MP1 is higher than the gate voltage, and the bidirectional trigger circuitThe time constant of the RC circuit (the first resistor R1 and the capacitor C) is 4ns, the voltage between two ends of the capacitor C can not change suddenly in the time, and V is in a short timeG1When the voltage is low, that is, the gate of the corresponding first PMOS transistor MP1 is low, at this time, the first PMOS transistor MP1 is turned on, and a current flows out from the first PMOS transistor MP1 and is injected into the fourth P + injection region 3021 in the P-well 302, and the current flows through the second N-well 303, so that a voltage drop is generated between the P-well 302 and the second N-well 303, that is, the BE junction voltage of the first transistor Q1 is greater than 0.7V, the first transistor Q1 is turned on, and the triac Q2 is also turned on, that is, the second N-well 303 is turned on to the first N-well 301 in the first direction, so that the electrostatic pulse at the first trigger terminal T1 is discharged through the first discharging path.
The first bleeding path L1 is specifically a fifth P + implantation region 3031, a second N-well 303, a P-well 302, a first N-well 301, and a first N + implantation region 3013.
The bleeding path of the first trigger terminal T1 is bled from the second trigger terminal T2 through the first diode D1 via the first bleeding path, and the current direction output is prevented by the first diode D1.
If the second trigger terminal T2 generates an electrostatic pulse, the second PMOS transistor is turned on, the triac is turned on in the second direction, and the second triac is turned on to form a second bleeding path.
Specifically, if the electrostatic pulse is generated at the second trigger terminal T2, the source voltage of the second PMOS transistor MP2 is higher than the gate voltage, the RC circuit time constant in the bidirectional trigger circuit is 4ns, the voltage across the capacitor cannot change abruptly in a time period, and V is short timeG2At a low voltage, that is, the gate of the corresponding second PMOS transistor MP2 is at a low voltage, at this time, the second PMOS transistor MP2 is turned on, and a current flows out from the second PMOS transistor MP2 and is injected into the fourth P + injection region 3021 in the P-well 302, and the current flows through the first N-well 301, so that a voltage drop is generated between the P-well 302 and the first N-well 301, and the BE junction voltage of the second transistor Q3 is greater than 0.7V, that is, the second transistor Q1 is turned on, and at the same time, the triac Q2 is also turned on, that is, the conduction is performed in the second direction from the first N-well 301 to the second N-well 303, and the electrostatic pulse at the second trigger terminal T2 is discharged through the second discharging path.
The second bleeding path L2 is specifically a third P + implantation region 3013, a first N-well 301, a P-well 302, a second N-well 303, and a second N + implantation region 3032.
The bleeding path of the second trigger terminal T2 is bled from the first trigger terminal T1 via the second diode D2 via the second bleeding path, and with the second diode D2, current direction output is avoided.
Thereby forming a bidirectional discharge path and realizing a bidirectional protection structure. After the external bidirectional trigger circuit is added, the turn-on voltage of the SCR is no longer the avalanche breakdown voltage between the first N-well 301 or the second N-well 303 and the P-well, but is reduced to the turn-on voltage of the first PMOS transistor MP1 or the second PMOS transistor MP2, and the ESD protection device structure is suitable for protection of a low operating voltage circuit.
One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
the invention provides a bidirectional triggered ESD protective device, which comprises: outside bidirectional trigger circuit of silicon controlled rectifier structure and silicon controlled rectifier structure, this silicon controlled rectifier structure includes: first PMOS pipe, second PMOS pipe and bidirectional triode, first triode, the second triode that set up on the SOI substrate, this bidirectional trigger circuit includes: the circuit comprises a first resistor, a capacitor, a second resistor, a first diode and a second diode; the first resistor, the capacitor and the second resistor are sequentially connected in series, one end of the first resistor is connected with a source electrode of a first PMOS (P-channel metal oxide semiconductor) tube, the other end of the first resistor is connected with a grid electrode of the first PMOS tube, one end of the second resistor is connected with a source electrode of a second PMOS tube, the other end of the second resistor is connected with a grid electrode of the second PMOS tube, a drain electrode of the first PMOS tube, a drain electrode of the second PMOS tube and a base electrode of the bidirectional triode are connected, a base electrode of the first triode is connected with one end of the bidirectional triode when the bidirectional triode is conducted, and a base electrode of the second triode is connected with the; the first trigger end is connected with a collector electrode of the bidirectional triode when the bidirectional triode is conducted in the first direction through a reverse first diode, and the first trigger end is also connected with an emitting electrode of the first triode; the collector electrode when the second trigger end is connected with the bidirectional triode through the reverse second diode and conducted in the second direction, the emitter electrode of the second triode is further connected with the second trigger end, the symmetrical structure is adopted, bidirectional ESD protection is provided, extra diodes in parallel connection are not needed, the bidirectional SCR can be triggered to work under low voltage through the mode of adding the trigger circuit, ESD current is discharged, meanwhile, high voltage can be maintained, and the device is effectively prevented from entering a bolt-lock state.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112510034A (en) * | 2021-02-07 | 2021-03-16 | 微龛(广州)半导体有限公司 | Bidirectional ESD protection device and circuit |
| CN113571513A (en) * | 2021-09-23 | 2021-10-29 | 四川上特科技有限公司 | A low-trigger high-robust SCR device and protection circuit for transient suppressor |
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| US20040207021A1 (en) * | 2003-04-16 | 2004-10-21 | Russ Cornelius Christian | Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies |
| CN104037748A (en) * | 2014-06-18 | 2014-09-10 | 电子科技大学 | Anti-latch-up trigger circuit for ESD (Electronic Static Discharge) |
| CN106505066A (en) * | 2015-09-03 | 2017-03-15 | 联咏科技股份有限公司 | Electrostatic discharge protection circuit |
| CN105633074A (en) * | 2016-03-10 | 2016-06-01 | 湖南静芯微电子技术有限公司 | Bidirectional silicon controlled rectifier triggered by reverse-biased diode |
| CN107658295A (en) * | 2017-11-10 | 2018-02-02 | 江南大学 | A kind of bi-directional ESD of holohedral symmetry double-gated diode triggered SCR structure protects anti-latch devices |
| KR20190133349A (en) * | 2018-05-23 | 2019-12-03 | 삼성전자주식회사 | Esd protection semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112510034A (en) * | 2021-02-07 | 2021-03-16 | 微龛(广州)半导体有限公司 | Bidirectional ESD protection device and circuit |
| CN113571513A (en) * | 2021-09-23 | 2021-10-29 | 四川上特科技有限公司 | A low-trigger high-robust SCR device and protection circuit for transient suppressor |
| CN113571513B (en) * | 2021-09-23 | 2022-01-04 | 四川上特科技有限公司 | A low-trigger high-robust SCR device and protection circuit for transient suppressor |
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