CN104037748A

CN104037748A - Anti-latch-up trigger circuit for ESD (Electronic Static Discharge)

Info

Publication number: CN104037748A
Application number: CN201410271197.2A
Authority: CN
Inventors: 乔明; 齐钊; 马金荣; 薛腾飞; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2014-06-18
Filing date: 2014-06-18
Publication date: 2014-09-10
Anticipated expiration: 2034-06-18
Also published as: CN104037748B

Abstract

The invention relates to the electronic circuit technology, in particular to an anti-latch-up trigger circuit for ESD. The circuit comprises a detection circuit 1, an output stage circuit 2 and an SCR (Silicon Controlled Rectifier) which are connected in sequence; the detection circuit is composed of a capacitor C11 and a resistor R12, and a power supply VVD is connected with the ground GND after sequentially passing through the capacitor C11 and the resistor R12; the output stage circuit is composed of a diode D21, a diode D22, a diode D23, the positive electrode of the diode D21 is connected with the power supply VDD after passing through the C11, the negative electrode of the diode D21 is connected with the positive electrode of the diode D23, the negative electrode of the diode D23 is connected with the positive electrode of the diode D22, and the negative electrode of the diode D22 is connected with the positive electrode of the diode D21; the gate pole of the SCR is connected with the negative electrode of the diode D21. The anti-latch-up trigger circuit for ESD has the advantages of having significant effects on maximizing the current capability of the SCR and reducing the trigger voltage of the SCR and being capable of capturing the falling edge of the ESD pulse and outputting negative voltage to turn off the SCR structure. The anti-latch-up trigger circuit is particularly suitable for ESD.

Description

A kind of anti-breech lock circuits for triggering for ESD

Technical field

The present invention relates to electronic circuit technology, be mainly used in electrostatic leakage (Electro Static Discharge, referred to as ESD) guard technology, a kind ofly specifically can identify and export shutdown signal to the trailing edge of esd pulse clamps is turn-offed, prevent the circuits for triggering of latch-up (Latch-up).

Background technology

ESD is electrostatic leakage, is the ubiquitous phenomenon of nature.ESD is present in each corner of people's daily life.And be exactly habitual like this electrical phenomena be fatal threat for accurate integrated circuit.

Along with the raising of integrated circuit fabrication process, its minimum feature has dropped to the even rank of nanometer of sub-micron, and in bringing chip performance to improve, its anti-ESD striking capabilities also significantly reduces, and therefore static damage is more serious.And the contradiction of the anti-ESD ability of technological development and chip becomes the problem that integrated circuit (IC) design person must consider.

Fig. 1 has provided and used LVTSCR device is the ESD protection circuit that low-voltage triggers silicon controlled rectifier; its principle is to trigger the protection device of SCR conducting by GGNMOS structure parasitic in LVTSCR, protected device is not destroyed with the NPN transistor of parasitism in SCR and the PNP transistor ESD electric current of releasing by esd pulse.And this structure has a fatal shortcoming, that is exactly that LVTSCR, after unlatching, (snapback) phenomenon of turning back by force can occur, and the voltage that maintains after turning back approximately maintains 1-2V.If the VDD of protected circuit is 5V or higher, once this LVTSCR triggers and will can certainly not turn-off so, thereby latch-up occurs.

Result of study shows, after common SCR device is opened, it is lower that it maintains voltage, and ESD current drain ability is stronger.So just produce a contradiction, if want ESD current drain very capable, cannot take into account the problem of latch-up.Take into account latch-up if want, general way is to improve the voltage that maintains of SCR, but so can not make SCR structure current drain ability maximize.

Summary of the invention

To be solved by this invention, be exactly for the problems referred to above, a kind of circuits for triggering of anti-breech lock are proposed, this circuit can assist the triggering of SCR device to open fast, after esd pulse disappears, can assist SCR to turn-off, in the time there is no esd pulse, this circuit is not worked simultaneously.

The present invention solves the problems of the technologies described above adopted technical scheme: a kind of anti-breech lock circuits for triggering for ESD, it is characterized in that, and comprise the testing circuit 1, output-stage circuit 2 and the SCR device that connect successively; Wherein, testing circuit is made up of capacitor C 11 and resistance R 12; Power supply VVD is successively by capacitor C 11 and resistance R 12 ground connection GND; Output-stage circuit is made up of diode D21, D22, D23; The positive pole of diode D21 meets power vd D after by C11, and its negative pole connects the positive pole of diode D23; The negative pole of diode D23 connects the positive pole of diode D22; The negative pole of diode D22 connects the positive pole of diode D21; The gate pole of SCR device connects the negative pole of diode D21.

Concrete, described testing circuit 1 also comprises diode D13; The negative pole of diode D13 meets power vd D by capacitor C 11, its plus earth GND.

Concrete, described testing circuit 1 also comprises diode D13; The positive pole of diode D13 meets power vd D by capacitor C 11, its minus earth GND.

Beneficial effect of the present invention is, maximizes for realizing SCR current capacity, and reducing SCR trigger voltage has remarkable result, and this circuit can catch the trailing edge of esd pulse simultaneously, and exports negative voltage and turn-off SCR structure.

Brief description of the drawings

Fig. 1 is traditional LVTSCR protective circuit;

Fig. 2 is the electrical block diagram of embodiment 1;

Fig. 3 is the electrical block diagram of embodiment 2;

Fig. 4 is the electrical block diagram of embodiment 3;

Fig. 5 is the capacitor charging path schematic diagram of the present invention in the time that esd pulse rising edge arrives;

Fig. 6 is the capacitor discharge path schematic diagram of the present invention in the time that esd pulse trailing edge arrives;

Fig. 7 is the normal upper electric pulse simulation result schematic diagram of embodiment 1 structure;

Fig. 8 is the simulation result schematic diagram of embodiment 1 structure under esd pulse;

Fig. 9 is the normal upper electric pulse simulation result schematic diagram of embodiment 2 structures;

Figure 10 is the simulation result schematic diagrames of embodiment 2 structures under esd pulse;

Figure 11 is the normal upper electric pulse simulation result schematic diagram of embodiment 3 structures;

Figure 12 is the simulation result schematic diagrames of embodiment 3 structures under esd pulse.

Embodiment

Below in conjunction with drawings and Examples, describe technical scheme of the present invention in detail:

Embodiment 1:

As shown in Figure 3, this example comprises the testing circuit 1, output-stage circuit 2 and the SCR device that connect successively; Wherein, testing circuit is made up of capacitor C 11 and resistance R 12; Power supply VVD is successively by capacitor C 11 and resistance R 12 ground connection GND; Output-stage circuit is made up of diode D21, D22, D23; The positive pole of diode D21 meets power vd D after by C11, and its negative pole connects the positive pole of diode D23; The negative pole of diode D23 connects the positive pole of diode D22; The negative pole of diode D22 connects the positive pole of diode D21; The gate pole of SCR device connects the negative pole of diode D21.

This routine operation principle is:

In the time that the rising edge of esd pulse appears on VDD, this pulse meeting is to the top crown charging of electric capacity 11.Charging current path now as shown in Figure 5.In the time of this electric current process resistance 12, produce pressure drop in resistance upper end, when finishing after-current, charging disappears, and on resistance 12, terminal voltage drops to 0 current potential gradually.

In the time that the trailing edge of esd pulse appears at VDD, due to the upper voltage collapse of VDD, electric capacity will be discharged to power supply.Now, the discharge loop of electric capacity as shown in Figure 6.At this moment, will there is negative voltage in the upper end of resistance 12.

If the voltage on VDD is normal upper piezoelectric voltage, because the rising of this voltage is very slow, the electric current therefore forming in capacitor charging process is very little, so the pressure drop on resistance 12 is very low, thus circuit output electronegative potential, circuit is closed.

In order better to explain that this example, in the effect suppressing in latch-up and auxiliary triggering, is now analyzed with simulation result.In emulation, capacitance is got 5pF, and resistance value is got 5K Ω.

ESD circuits for triggering and ESD device all need to keep off state in the time that chip normally powers on, thereby do not affect the normal operation of circuit.This routine circuit is carried out to emulation, in emulation, utilize a rising edge for 1ms the voltage in the time that rising keeps the voltage source of 5V to carry out analog chip powering on afterwards.Simulation result as shown in Figure 7, from then on can find out by result, and circuit output low level under normal circumstances, therefore meets ESD basic requirements of design.

Rise at esd pulse, keep constant emulation when the fast-descending as shown in Figure 8.The voltage that rises to 10V with 10ns from 0V in emulation imitates esd pulse rising edge, and the voltage declining at the same rate imitates trailing edge.Can find out from output curve, in the time that esd pulse rises, circuit can provide for SCR device the trigger impulse of a forward really.If emulation shows to increase the value of resistance 12 and electric capacity 11, the holding time prolongation of this pulse.Can see that at the trailing edge of esd pulse this circuit can be assisted its shutoff for the gate pole of rear class SCR device provides the voltage of a negative sense after esd pulse disappears equally.

The important role of diode 21, diode 22 and diode 23 in circuit.After diode 21 is opened SCR, ESD electric current can not flow into GND through resistance 12.23 of diode 22 and diodes have ensured the reliable triggering of SCR in for reverse extraction current supplying path, if there is no diode 22 and diode 23, the trigger current of being launched by circuits for triggering output so will have part and flow into GND through resistance 12, like this since triggering signal the trigger action of SCR will be weakened or disappear.Even if diode 22 and the dead band voltage of the approximately 1.4V of diode 23 have ensured SCR, this road that is triggered also can not be opened.

Can find out from simulation result, this circuit can make SCR have self-switching-off capability in the situation that not changing SCR structure completely.Owing to only having esd pulse can trigger this circuit structure, this circuit can be identified voltage, avoids to greatest extent opening by mistake and opens, and reliability is higher.

Embodiment 2:

As shown in Figure 3, as different from Example 1, this example is at the side of resistance 12 diode 13 in parallel, and the positive pole of this diode is connected with the bottom crown of electric capacity 11, and its negative pole meets GND, and other structures in circuit are constant.

Its operation principle is substantially the same manner as Example 1, and difference is, electric current when this example has been used diode 13 to carry out conducting electric capacity 11 is charged.Because the anode of this diode 13 induces high potential to trigger SCR when electric capacity 11 quick charge.Therefore the breadth length ratio of this diode 13 is preferably less than 1.

The analogous diagram when analogous diagram of embodiment 2 in the time normally powering on and ESD is shown in Fig. 9 and Figure 10.

Embodiment 3:

As shown in Figure 4, as different from Example 2, main need to be by 13 reversal connections of the diode in embodiment 2.Be the bottom crown that the negative electrode of diode 13 connects electric capacity 11, anode meets GND, and in circuit, other structures are constant.

Its operation principle and specific embodiment 2 are basic identical, and difference is, this example is to have used diode 13 that the current path in electric capacity positive charge moment is provided, and embodiment three is just contrary with it.The current path in electric current forward moment is provided by resistance 12, and 13 of diodes provide capacitor discharge path.During due to capacitor discharge, need the higher negative potential of circuit output, therefore the breadth length ratio of this diode 13 is equally preferably less than 1.

The analogous diagram when analogous diagram of embodiment 3 in the time normally powering on and ESD is shown in Figure 11 and Figure 12.

In sum, the present invention proposes the anti-breech lock circuits for triggering of a kind of ESD.This circuit is differentiated ESD signal and normal signal by the charging and discharging currents size of electric capacity, finishes, and export negative potential simultaneously thereby tell esd event by the trailing edge that the back discharge electric current in capacitor discharge moment is identified esd pulse.Because thereby this negative potential can extract the shutoff that the electric current in SCR structure is assisted SCR.So SCR structure time does not need to consider the problem of latch-up in design, thereby the large current drain ability of SCR can be performed to ultimate attainmently, preferably resolve the contradiction between ESD ability and the anti-breech lock ability of silicon controlled rectifier.

Claims

1. for anti-breech lock circuits for triggering of ESD, it is characterized in that, comprise the testing circuit (1), output-stage circuit (2) and the SCR device that connect successively; Wherein, testing circuit is made up of capacitor C 11 and resistance R 12; Power supply VVD is successively by capacitor C 11 and resistance R 12 ground connection GND; Output-stage circuit is made up of diode D21, D22, D23; The positive pole of diode D21 meets power vd D after by C11, and its negative pole connects the positive pole of diode D23; The negative pole of diode D23 connects the positive pole of diode D22; The negative pole of diode D22 connects the positive pole of diode D21; The gate pole of SCR device connects the negative pole of diode D21.

2. a kind of anti-breech lock circuits for triggering for ESD according to claim 1, is characterized in that, described testing circuit (1) also comprises diode D13; The negative pole of diode D13 meets power vd D by capacitor C 11, its plus earth GND.

3. a kind of anti-breech lock circuits for triggering for ESD according to claim 1, is characterized in that, described testing circuit (1) also comprises diode D13; The positive pole of diode D13 meets power vd D by capacitor C 11, its minus earth GND.