CN113037254A - Latch-up prevention circuit and integrated circuit - Google Patents
Latch-up prevention circuit and integrated circuit Download PDFInfo
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- CN113037254A CN113037254A CN202110562064.0A CN202110562064A CN113037254A CN 113037254 A CN113037254 A CN 113037254A CN 202110562064 A CN202110562064 A CN 202110562064A CN 113037254 A CN113037254 A CN 113037254A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
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Abstract
The application relates to an anti-latch-up circuit and an integrated circuit. The latch-up prevention circuit comprises a latch-up event monitoring circuit and an ESD event monitoring circuit; the latch-up event monitoring circuit is connected with the ESD event monitoring circuit and is used for connecting the IO circuit; the IO circuit comprises an IO interface, a first driving circuit used for connecting a working power supply, a second driving circuit used for connecting a common ground, a first ESD protection circuit used for connecting the working power supply and a second ESD protection circuit used for connecting the common ground; the latch event monitoring circuit controls the opening of a first driving circuit, a second driving circuit, a first ESD protection circuit and a second ESD protection circuit of the IO circuit to discharge the positive and negative trigger current of the latch. When an ESD event occurs, switch tube channels in the first driving circuit, the second driving circuit, the first ESD protection circuit and the second ESD protection circuit are in a closed state, and the ESD protection capability of an IO interface is improved.
Description
Technical Field
The present disclosure relates to integrated circuits, and more particularly to an anti-latch circuit and an integrated circuit.
Background
With the development of the integrated circuit technology following moore's law, the feature size of the device is continuously reduced, the chip integration level is higher and higher, and the chip area is smaller and smaller, so that the chip is more prone to latch-up. In order to reduce the chip area as much as possible, the layout design rule of the latch-up is necessarily reduced following the process node, but the latch-up distance is necessarily reduced, so that the latch-up prevention effect of the chip is greatly reduced, and the immunity of the chip to the latch-up effect becomes a difficult problem in the industry.
In the implementation process, the inventor finds that at least the following problems exist in the conventional technology: the traditional latch-up prevention circuit has the problems of complex process flow and high cost.
Disclosure of Invention
In view of the above, it is desirable to provide an anti-latch-up circuit and an integrated circuit with low cost and capable of reducing the complexity of the process flow.
In order to achieve the above object, in one aspect, an embodiment of the present invention provides an anti-latch-up circuit, including a latch-up event monitoring circuit and an ESD event monitoring circuit; the latch-up event monitoring circuit is connected with the ESD event monitoring circuit and is used for connecting the IO circuit; the IO circuit comprises an IO interface, a first driving circuit used for connecting a working power supply, a second driving circuit used for connecting a common ground, a first ESD protection circuit used for connecting the working power supply and a second ESD protection circuit used for connecting the common ground;
under the condition that the latch event monitoring circuit detects the inrush current of the IO interface, the latch event monitoring circuit indicates that the first driving circuit and the first ESD protection circuit are both disconnected from the IO interface and the working power supply, and indicates that the second driving circuit and the second ESD protection circuit are both connected with the IO interface and the common ground; under the condition that the latch event monitoring circuit detects that the IO interface draws current, the first driving circuit and the first ESD protection circuit are indicated to be connected with the IO interface and a working power supply, and the second driving circuit and the second ESD protection circuit are indicated to be disconnected with the IO interface and a common ground;
the ESD event monitoring circuit transmits an electric signal to the latch-up event monitoring circuit when detecting that the IO interface has an electrostatic attack event; the latch event monitoring circuit receiving the electric signal indicates that the first driving circuit and the first ESD protection circuit are both disconnected from the IO interface and the working power supply, and indicates that the second driving circuit and the second ESD protection circuit are both disconnected from the IO interface and the common ground.
In one embodiment, the ESD event monitoring circuit comprises an RC circuit, a first-stage inverter and a second-stage inverter;
the first end of the RC circuit is connected with a working power supply, the second end of the RC circuit is grounded, and the third end of the RC circuit is connected with the input end of the first-stage inverter; the output end of the first-stage inverter is respectively connected with the second-stage inverter and the latch event monitoring circuit; the output end of the second stage inverter is connected with the latch event monitoring circuit.
In one embodiment, the first stage inverter comprises a switch tube MN2 and a switch tube MP 2; the second stage inverter comprises a switch tube MP1 and a switch tube MN 1;
the source electrode of the switching tube MP1 is connected with a working power supply, the drain electrodes are respectively connected with the latch event monitoring circuit and the drain electrode of the switching tube MN1, and the grid electrodes are respectively connected with the drain electrode of the switching tube MP2, the drain electrode of the switching tube MN2, the grid electrode of the switching tube MN1 and the latch event monitoring circuit;
the source electrode of the switch tube MP2 is connected with a working power supply, and the grid electrode of the switch tube MP2 is respectively connected with the third end of the RC circuit and the grid electrode of the switch tube MN 2; the source electrode of the switching tube MN2 is connected with the common ground; the source of the switching tube NM1 is connected to a common ground.
In one embodiment, the RC circuit includes a resistor R1 and a capacitor C1;
one end of the resistor R1 is connected with a working power supply, and the other end of the resistor R1 is respectively connected with one end of the capacitor C1 and the grid of the switch tube MP 2; the other end of the capacitor C1 is connected to a common ground.
In one embodiment, the latch-up event monitoring circuit comprises a first control circuit, a second control circuit, a current draw monitoring circuit, a current inrush monitoring circuit, a first level shift circuit and a second level shift circuit;
one end of the current extraction monitoring circuit is connected with the IO interface, and the other end of the current extraction monitoring circuit is connected with the input end of the first level transfer circuit; the electric signal output by the output end of the first level shift circuit is used for indicating the actions of the first driving circuit and the first ESD protection circuit; the first control circuit is used for adjusting the potential of the input end of the first level shifter circuit according to the electric signal;
one end of the current inrush monitoring circuit is connected with the IO interface, and the other end of the current inrush monitoring circuit is connected with the input end of the second level transfer circuit; the electric signal output by the second level shift circuit is used for indicating the actions of the second driving circuit and the second ESD protection circuit; the second control circuit is used for adjusting the potential of the input end of the second level shift circuit according to the electric signal.
In one embodiment, the current draw monitoring circuit comprises a resistor R2, a resistor R3 and a switch tube MN 6; the first control circuit comprises a switching tube MP 4; the first level shift circuit comprises a resistor R4, a resistor R5, a switch tube MP5 and a switch tube MN 3; the current inrush monitoring circuit comprises a switching tube MP6, a resistor R6 and a resistor R7; the second control circuit comprises a switch tube MN 4; the second level shift circuit comprises a resistor R8, a resistor R9, a switch tube MN5 and a switch tube MP 3;
the gate of the switching tube MP4 is connected to the ESD event monitoring circuit, the source is connected to the first end of the resistor R2, and the drain is connected to the second end of the resistor R2; the first end of the resistor R2 is connected with the source electrode of the switch tube MP5, and the second end is connected with the grid electrode of the switch tube MP5 and one end of the resistor R3; the other end of the resistor R3 is connected with the drain electrode of the switching tube MN 6; the grid electrode of the switching tube MN6 is connected with the common ground, and the source electrode is connected with the IO interface; the source electrode of the switch tube MP5 is connected with a working power supply, the drain electrode of the switch tube MP 3578 is connected with the grid electrode of the switch tube MN3 and one end of a resistor R4, and the other end of the resistor R4 is connected with an IO interface; one end of the resistor R5 is connected with a working power supply, and the other end of the resistor R5 is connected with the drain electrode of the switch tube MN3, the control end of the first drive circuit and the control end of the first ESD protection circuit; the source electrode of the switching tube MN3 is connected with the IO interface;
the grid electrode of the switching tube MN4 is connected with the ESD event monitoring circuit, the source electrode is connected with the first end of the resistor R6, and the drain electrode is connected with the second end of the resistor R6; the first end of the resistor R6 is connected with the common ground, and the second end is respectively connected with one end of the resistor R7 and the grid of the switching tube MN 5; the other end of the resistor R7 is connected with the drain electrode of the switch tube MP 6; the grid electrode of the switching tube MP6 is connected with a working power supply, and the source electrode is connected with an IO interface; the source electrode of the switch tube MN5 is connected with the common ground, and the drain electrode is respectively connected with one end of the resistor R8 and the grid electrode of the switch tube MP 3; the other end of the resistor R8 is connected with an IO interface; the source electrode of the switching tube MP3 is connected with the IO interface, and the drain electrode is respectively connected with one end of the resistor R9, the control end of the second driving circuit and the control end of the second ESD protection circuit; the other end of the resistor R9 is connected to a common ground.
In another aspect, an embodiment of the present invention further provides an integrated circuit including an IO circuit and an anti-latch-up circuit as described in any one of the above embodiments.
In one embodiment, the IO circuit comprises an IO interface, a first driving circuit used for connecting an operating power supply, a second driving circuit used for connecting a common ground, a first ESD protection circuit used for connecting the operating power supply and a second ESD protection circuit used for connecting the common ground;
the first driving circuit comprises an AND gate circuit and a switching tube MP 7; the second driving circuit comprises an OR gate circuit and a switch tube MN 7;
the first input end of the AND gate circuit is used for connecting a digital circuit, the second input end of the AND gate circuit is connected with the latch event monitoring circuit, and the output end of the AND gate circuit is connected with the grid of the switching tube MP 7; the source electrode of the MP7 is connected with a working power supply, and the drain electrode is connected with an IO interface;
the first input end of the OR gate circuit is used for connecting a digital circuit, the second input end of the OR gate circuit is connected with the latch event monitoring circuit, and the output end of the OR gate circuit is connected with the grid electrode of the switching tube MN 7; the source of MN7 is connected to common ground and the drain is connected to the IO interface.
In one embodiment, the latch event monitoring circuit includes a first output and a second output;
the first output end of the latch event monitoring circuit is connected with the second input end of the AND circuit, and the second output end is connected with the second input end of the OR gate circuit.
In one embodiment, the first ESD protection circuit comprises a switch tube mpdesd; the second ESD protection circuit comprises a switching tube MNESD;
the grid electrode of the switching tube MPESD is connected with the first output end of the latch-up event monitoring circuit, the source electrode of the switching tube MPESD is connected with a working power supply, and the drain electrode of the switching tube MPESD is connected with an IO interface; the grid electrode of the switching tube MNESD is connected with the second output end of the latch-up event monitoring circuit, the source electrode of the switching tube MNESD is connected with the common ground, and the drain electrode of the switching tube MNESD is connected with the IO interface.
One of the above technical solutions has the following advantages and beneficial effects:
the latch-up prevention circuit can control the opening of the first driving circuit, the second driving circuit, the first ESD protection circuit and the second ESD protection circuit of the IO circuit through the latch-up event monitoring circuit to discharge the positive and negative trigger current of the latch-up. Meanwhile, when an ESD event occurs, switch tube channels in the first driving circuit, the second driving circuit, the first ESD protection circuit and the second ESD protection circuit are in a closed state, and the ESD protection capability of an IO interface is improved. In addition, the area of the layout of the IO port is increased traditionally through enlarging the physical distance between the P-type pipe and the N-type pipe and increasing the form of the isolation ring, and the area of the IO layout can be saved through the latch-up prevention circuit, so that the cost of the chip is reduced.
Drawings
The foregoing and other objects, features and advantages of the application will be apparent from the following more particular description of preferred embodiments of the application, as illustrated in the accompanying drawings. Like reference numerals refer to like parts throughout the drawings, and the drawings are not intended to be drawn to scale in actual dimensions, emphasis instead being placed upon illustrating the subject matter of the present application.
FIG. 1 is a first schematic block diagram of an anti-latch-up circuit in one embodiment;
FIG. 2 is a first schematic block diagram of an ESD event monitoring circuit according to one embodiment;
FIG. 3 is a second schematic block diagram of an ESD event monitoring circuit according to one embodiment;
FIG. 4 is a first schematic block diagram of a latch event monitoring circuit in one embodiment;
FIG. 5 is a second schematic block diagram of a latch event monitoring circuit in accordance with one embodiment;
FIG. 6 is a block diagram of an integrated circuit in one embodiment.
Detailed Description
To facilitate an understanding of the present application, the present application will now be described more fully with reference to the accompanying drawings. Embodiments of the present application are set forth in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that, as used herein, the terms "first," "second," and the like may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. The first resistance and the second resistance are both resistances, but they are not the same resistance.
It is to be understood that "connection" in the following embodiments is to be understood as "electrical connection", "communication connection", and the like if the connected circuits, modules, units, and the like have communication of electrical signals or data with each other.
As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises/comprising," "includes" or "including," etc., specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.
In one embodiment, as shown in fig. 1, there is provided an anti-latch-up circuit comprising a latch-up event monitoring circuit and an ESD event monitoring circuit; the latch-up event monitoring circuit is connected with the ESD event monitoring circuit and is used for connecting the IO circuit; the IO circuit comprises an IO interface, a first driving circuit used for being connected with a working power supply VDD, a second driving circuit used for being connected with a common ground VSS, a first ESD protection circuit used for being connected with the working power supply VDD and a second ESD protection circuit used for being connected with the common ground VSS;
under the condition that the latch event monitoring circuit detects the inrush current of the IO interface, the latch event monitoring circuit indicates that the first driving circuit and the first ESD protection circuit are both disconnected from the IO interface and a working power supply VDD and indicates that the second driving circuit and the second ESD protection circuit are both connected with the IO interface and a common ground VSS; under the condition that the latch event monitoring circuit detects that the IO interface draws current, the first driving circuit and the first ESD protection circuit are indicated to be connected with the IO interface and a working power supply VDD, and the second driving circuit and the second ESD protection circuit are indicated to be disconnected with the IO interface and a common ground VSS;
the ESD event monitoring circuit transmits an electric signal to the latch-up event monitoring circuit when detecting that the IO interface has an electrostatic attack event; the latch event monitoring circuit receiving the electric signal indicates that the first driving circuit and the first ESD protection circuit are both disconnected from the IO interface and the working power supply VDD, and indicates that the second driving circuit and the second ESD protection circuit are both disconnected from the IO interface and the common ground VSS.
The latch event monitoring circuit is used for detecting whether current inrush or current extraction occurs at the IO port, and may be any circuit in the field that can implement the above functions. The ESD event monitoring circuit is configured to detect whether an electrostatic attack event occurs on the IO interface, and may specifically include a positive electrostatic attack from the IO interface to a common ground and a negative electrostatic attack from the IO interface to a working power supply, and may be any circuit in the field that can implement the above functions. The first driving circuit may include a first front-stage driving circuit and a first rear-stage driving circuit, and the second driving circuit may also include a second front-stage driving circuit and a second rear-stage driving circuit. The first ESD protection circuit and the second ESD protection circuit are used for performing electrostatic protection on the IO interface.
Specifically, in the conventional technology, the latch-up resistance of the IO interface is improved, the latch-up trigger current is discharged through the parasitic body diode of the upper IO circuit, and a large current is injected into the substrate due to the discharge of the parasitic body diode, so that the latch-up is easily triggered by the internal circuits of the IO circuit and the IO accessory. In order to improve the latch-up prevention capability, the process and the layout are generally improved, and the process develops a reverse well process, trench isolation, and the epitaxial layer and other process means are added on the heavily doped substrate to reduce the resistance of the substrate and inhibit latch-up. The layout mainly reduces the amplification gain of a parasitic path and the parasitic resistance of a substrate by enlarging the physical distance between the P-type pipe and the N-type pipe and adding the isolating ring, thereby playing the effect of inhibiting latch-up. The latch event monitoring circuit indicates that the first driving circuit and the first ESD protection circuit are connected with the working power supply in a disconnection mode under the condition that the IO interface inrush current is detected, indicates that the second driving circuit and the second ESD protection circuit are connected with the common ground in a conduction mode, and avoids the current flowing to parasitic body diodes in the first driving circuit and the first ESD protection circuit through the latch trigger current of the IO interface leakage of the second driving circuit and the second ESD protection circuit. Because the parasitic body diode and the substrate PSUB form a PNP, when a large current flows through the parasitic body diode in the first driving circuit and the first ESD protection circuit, the large current is injected into the substrate PSUB, and the parasitic latch circuit inside the IO interface or the IO circuit is easily triggered.
When the latch event monitoring circuit detects that the IO interface draws current, the first driving circuit and the first ESD protection circuit are indicated to be connected with the IO interface and the working power supply, and the second driving circuit and the second ESD protection circuit are indicated to be disconnected with the IO interface and the common ground. The latch trigger current extracted by the IO interface is discharged through the first driving circuit and the first ESD protection circuit, and most of the current is prevented from flowing to parasitic body diodes in the first driving circuit and the first ESD protection circuit. Because the parasitic body diode and the nearby N well region form an NPN, when a large current flows to the first driving circuit and the parasitic body diode of the first ESD protection circuit, the large current is injected into the N well region, and an IO interface or an internal parasitic latch circuit of the IO circuit is easily triggered. By introducing the latch-up event monitoring circuit, once the IO interface generates the pumping/sinking current, the driving circuit and the ESD protection circuit are started to discharge the current, and the large current is prevented from being injected into the substrate.
Under the condition that the ESD event monitoring circuit detects that an electrostatic attack event occurs on an IO interface, the electrostatic attack event comprises that IO receives positive electrostatic attack to a public ground VSS, IO receives negative electrostatic attack to a working power supply VDD, and the ESD event monitoring circuit transmits an electric signal to the latch event monitoring circuit, wherein the electric signal is specifically a high/low level signal. Through the level signal, the latch event monitoring circuit indicates that the first driving circuit and the first ESD protection circuit are both disconnected from the IO interface and the working power supply, and indicates that the second driving circuit and the second ESD protection circuit are both disconnected from the IO interface and the common ground. The positive ESD event is preferentially discharged to the common ground through the first driving circuit, the parasitic body diode of the first ESD protection circuit and the clamping circuit of the working power supply, so that the ESD protection effect is better. The latch-up prevention circuit may further include an ESD clamp circuit, and the ESD clamp circuit may turn on the connection between VDD and VSS according to an output signal of the ESD event monitoring circuit, and may discharge the connection through the ESD clamp circuit.
The latch-up prevention circuit can control the opening of the first driving circuit, the second driving circuit, the first ESD protection circuit and the second ESD protection circuit of the IO circuit through the latch-up event monitoring circuit to discharge the positive and negative trigger current of the latch-up. Meanwhile, when an ESD event occurs, switch tube channels in the first driving circuit, the second driving circuit, the first ESD protection circuit and the second ESD protection circuit are in a closed state, and the ESD protection capability of an IO interface is improved. In addition, the area of the layout of the IO port is increased traditionally through enlarging the physical distance between the P-type pipe and the N-type pipe and increasing the form of the isolation ring, and the area of the IO layout can be saved through the latch-up prevention circuit, so that the cost of the chip is reduced.
In one embodiment, as shown in FIG. 2, the ESD event monitoring circuit includes an RC circuit, a first stage inverter, and a second stage inverter;
the first end of the RC circuit is connected with a working power supply, the second end of the RC circuit is grounded, and the third end of the RC circuit is connected with the input end of the first-stage inverter; the output end of the first-stage inverter is respectively connected with the second-stage inverter and the latch event monitoring circuit; the output end of the second stage inverter is connected with the latch event monitoring circuit.
Specifically, when a positive ESD (Electro-Static discharge) event is detected relative to VSS, since the rising edge of the ESD signal is ns level and is much smaller than the RC delay time (RC is about 1 us), the third terminal of the RC circuit cannot follow up the VDD change, that is, the third terminal is low level, and outputs high level to the latch event monitoring circuit through the first level inverter and outputs low level through the second level inverter.
In one embodiment, as shown in fig. 3, the first stage inverter includes a switch transistor MN2 and a switch transistor MP 2; the second stage inverter comprises a switch tube MP1 and a switch tube MN 1; the source electrode of the switching tube MP1 is connected with a working power supply VDD, the drain electrodes are respectively connected with the latch event monitoring circuit and the drain electrode of the switching tube MN1, and the grid electrodes are respectively connected with the drain electrode of the switching tube MP2, the drain electrode of the switching tube MN2, the grid electrode of the switching tube MN1 and the latch event monitoring circuit; the source electrode of the switch tube MP2 is connected with a working power supply, and the grid electrode of the switch tube MP2 is respectively connected with the third end of the RC circuit and the grid electrode of the switch tube MN 2; the source electrode of the switching tube MN2 is connected with the common ground; the source of the switch NM1 is connected to the common ground VSS.
Specifically, when detecting that VDD has a positive ESD (electrostatic discharge) event with respect to VSS, the drain of the switch MP2 and the drain of the switch MN2 output a high level to the latch-up event monitoring circuit, and the drain of the switch MP1 and the drain of the switch MN1 output a low level to the latch-up event monitoring circuit.
In one embodiment, as shown in FIG. 3, the RC circuit includes a resistor R1 and a capacitor C1;
one end of the resistor R1 is connected with a working power supply, and the other end of the resistor R1 is respectively connected with one end of the capacitor C1 and the grid of the switch tube MP 2; the other end of the capacitor C1 is connected to a common ground.
Specifically, the connection end of the resistor R1 and the capacitor C1 is the third end of the RC circuit. The RC delay time is determined by the resistance value of the resistor R1 and the capacitance value of the capacitor C1.
In one embodiment, as shown in fig. 4, the latch-up event monitoring circuit includes a first control circuit, a second control circuit, a current draw monitoring circuit, a current inrush monitoring circuit, a first level shifter circuit, and a second level shifter circuit;
one end of the current extraction monitoring circuit is connected with the IO interface, and the other end of the current extraction monitoring circuit is connected with the input end of the first level transfer circuit; the electric signal output by the output end of the first level shift circuit is used for indicating the actions of the first driving circuit and the first ESD protection circuit; the first control circuit is used for adjusting the potential of the input end of the first level shifter circuit according to the electric signal;
one end of the current inrush monitoring circuit is connected with the IO interface, and the other end of the current inrush monitoring circuit is connected with the input end of the second level transfer circuit; the electric signal output by the second level shift circuit is used for indicating the actions of the second driving circuit and the second ESD protection circuit; the second control circuit is used for adjusting the potential of the input end of the second level shift circuit according to the electric signal.
Specifically, the first control circuit is configured to adjust a potential of an input terminal of the first level shift circuit, thereby controlling a potential of an output terminal of the first level shift circuit. The second control circuit is used for adjusting the potential of the input end of the second level shift circuit so as to control the potential of the output end of the second level shift circuit.
When the current extraction monitoring circuit detects the extracted current, the first level transfer circuit outputs a low level, so that the first driving circuit and the first ESD protection circuit are indicated to be connected with the IO interface and the working power supply, and the second level signal outputs a low level, so that the second driving circuit and the second ESD protection circuit are indicated to be disconnected with the IO interface and the common ground. When the current inrush monitoring circuit detects inrush current, the first level transfer circuit outputs high level to indicate that the first driving circuit and the first ESD protection circuit are both disconnected from the IO interface and the working power supply, and the second level transfer circuit outputs high level to indicate that the second driving circuit and the second ESD protection circuit are both connected with the IO interface and the common ground.
In one embodiment, as shown in fig. 5, the current draw monitoring circuit includes a resistor R2, a resistor R3, and a switch MN 6; the first control circuit comprises a switching tube MP 4; the first level shift circuit comprises a resistor R4, a resistor R5, a switch tube MP5 and a switch tube MN 3; the current inrush monitoring circuit comprises a switching tube MP6, a resistor R6 and a resistor R7; the second control circuit comprises a switch tube MN 4; the second level shift circuit comprises a resistor R8, a resistor R9, a switch tube MN5 and a switch tube MP 3;
the gate of the switching tube MP4 is connected to the ESD event monitoring circuit, the source is connected to the first end of the resistor R2, and the drain is connected to the second end of the resistor R2; the first end of the resistor R2 is connected with the source electrode of the switch tube MP5, and the second end is connected with the grid electrode of the switch tube MP5 and one end of the resistor R3; the other end of the resistor R3 is connected with the drain electrode of the switching tube MN 6; the grid electrode of the switching tube MN6 is connected with the common ground, and the source electrode is connected with the IO interface; the source electrode of the switch tube MP5 is connected with a working power supply, the drain electrode of the switch tube MP 3578 is connected with the grid electrode of the switch tube MN3 and one end of a resistor R4, and the other end of the resistor R4 is connected with an IO interface; one end of the resistor R5 is connected with a working power supply, and the other end of the resistor R5 is connected with the drain electrode of the switch tube MN3, the control end of the first drive circuit and the control end of the first ESD protection circuit; the source electrode of the switching tube MN3 is connected with the IO interface;
the grid electrode of the switching tube MN4 is connected with the ESD event monitoring circuit, the source electrode is connected with the first end of the resistor R6, and the drain electrode is connected with the second end of the resistor R6; the first end of the resistor R6 is connected with the common ground, and the second end is respectively connected with one end of the resistor R7 and the grid of the switching tube MN 5; the other end of the resistor R7 is connected with the drain electrode of the switch tube MP 6; the grid electrode of the switching tube MP6 is connected with a working power supply, and the source electrode is connected with an IO interface; the source electrode of the switch tube MN5 is connected with the common ground, and the drain electrode is respectively connected with one end of the resistor R8 and the grid electrode of the switch tube MP 3; the other end of the resistor R8 is connected with an IO interface; the source electrode of the switching tube MP3 is connected with the IO interface, and the drain electrode is respectively connected with one end of the resistor R9, the control end of the second driving circuit and the control end of the second ESD protection circuit; the other end of the resistor R9 is connected to a common ground.
Specifically, when the IO port draws current, MN6 is turned on, VDD is divided by R2 and R3, and the divided voltage to the gate of MP5 turns on MP5, so that the gate of MN3 is at a high level, MN3 is turned on, and the other end of resistor R5 and the drain terminal of switching tube MN3 (Ltgp point in the figure) are at a low level. That is, when the IO port draws current, the level output to the first driver circuit and the first ESD protection circuit is low. When the IO port draws current, MP6 is turned off, and when MP6 is turned off, MN5 is turned off so that MP3 is also turned off, and the drain of MP3 outputs a low level signal.
When the IO port is filled with current, MP6 is turned on, and upon the turn-on of MP6, MN5 is turned on so that MP3 is also turned on, and the drain of MP3 outputs a high level signal. When the IO port is filled with current, MN6 is turned off, so that MP5 is turned off, MN3 is turned off, and the other end of resistor R5 and the drain end of switching tube MN3 (Ltgp point in the figure) are at high level. That is, when the IO port injects current, the level output to the first driving circuit and the first ESD protection circuit is high level.
Further, MP4 and MN4 are primarily responsible for pulling the trgp1 and trgn1 nodes to VDD and VSS, respectively, when a positive ESD signal occurs from VDD to VSS, rendering the entire latch-up monitoring circuit inoperative.
In one embodiment, there is also provided an integrated circuit comprising an IO circuit and an anti-latch-up circuit as in any one of the above.
In one embodiment, as shown in fig. 6, the IO circuit includes an IO interface, a first driving circuit for connecting an operating power supply, a second driving circuit for connecting a common ground, a first ESD protection circuit for connecting the operating power supply, and a second ESD protection circuit for connecting the common ground;
the first driving circuit comprises an AND gate circuit and a switching tube MP 7; the second driving circuit comprises an OR gate circuit and a switch tube MN 7;
the first input end of the AND gate circuit is used for connecting the digital circuit 100, the second input end is connected with the latch event monitoring circuit, and the output end is connected with the grid of the switching tube MP 7; the source electrode of the MP7 is connected with a working power supply, and the drain electrode is connected with an IO interface;
the first input end of the OR gate circuit is used for connecting the digital circuit 100, the second input end is connected with the latch event monitoring circuit, and the output end is connected with the grid electrode of the switching tube MN 7; the source of MN7 is connected to common ground and the drain is connected to the IO interface.
The first ESD protection circuit and the second ESD protection circuit may be any ESD protection circuit in the art, and are not limited herein. The latch-up event monitoring circuit is also connected with an ESD event monitoring circuit. Digital circuit
Specifically, when the IO port draws current, the latch event monitoring circuit outputs low level signals to the first driving circuit, the second driving circuit, the first ESD protection circuit, and the second ESD protection circuit. The MP7 in the first driving circuit receiving the low level signal is turned on, the first ESD protection circuit receiving the low level signal is turned on, the MN7 in the second driving circuit receiving the low level signal is turned off, and the MNESD of the second ESD protection circuit receiving the low level signal is disconnected. The MP7 in the first driving circuit receiving the high level signal is turned off and disconnected from the first ESD protection circuit, the MN7 in the second driving circuit receiving the high level signal is turned on, and the MNESD of the second ESD protection circuit is turned on.
In one embodiment, the latch event monitoring circuit includes a first output and a second output;
the first output end of the latch event monitoring circuit is connected with the second input end of the AND circuit, and the second output end is connected with the second input end of the OR gate circuit.
In one embodiment, as shown in fig. 6, the first ESD protection circuit includes a switch tube mpdesd; the second ESD protection circuit comprises a switching tube MNESD;
the grid electrode of the switching tube MPESD is connected with the first output end of the latch-up event monitoring circuit, the source electrode of the switching tube MPESD is connected with a working power supply, and the drain electrode of the switching tube MPESD is connected with an IO interface; the grid electrode of the switching tube MNESD is connected with the second output end of the latch-up event monitoring circuit, the source electrode of the switching tube MNESD is connected with the common ground, and the drain electrode of the switching tube MNESD is connected with the IO interface.
Specifically, the MPESD receiving a high level is turned off, and the MPESD receiving a low level is turned on. The MNESD receiving high level is turned on, and the MNESD receiving low level is turned off.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus DRAM (RDRAM), and interface DRAM (DRDRAM).
In the description herein, references to the description of "some embodiments," "other embodiments," "desired embodiments," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. An anti-latch-up circuit, comprising a latch-up event monitoring circuit and an ESD event monitoring circuit; the latch-up event monitoring circuit is connected with the ESD event monitoring circuit and is used for connecting an IO circuit; the IO circuit comprises an IO interface, a first driving circuit used for being connected with a working power supply, a second driving circuit used for being connected with a common ground, a first ESD protection circuit used for being connected with the working power supply and a second ESD protection circuit used for being connected with the common ground;
when detecting the inrush current of the IO interface, the latch event monitoring circuit indicates that the first driving circuit and the first ESD protection circuit are both disconnected from the IO interface and the working power supply, and indicates that the second driving circuit and the second ESD protection circuit are both connected to the IO interface and the common ground; when the latch event monitoring circuit detects that the IO interface draws current, the first driving circuit and the first ESD protection circuit are indicated to be connected with the IO interface and the working power supply in a conducting mode, and the second driving circuit and the second ESD protection circuit are indicated to be disconnected with the IO interface and the common ground in a disconnecting mode;
the ESD event monitoring circuit transmits an electric signal to the latch-up event monitoring circuit when detecting that the IO interface has a static attack event; the latch-up event monitoring circuit receiving the electric signal indicates that the first driving circuit and the first ESD protection circuit are both disconnected from the IO interface and the working power supply, and indicates that the second driving circuit and the second ESD protection circuit are both disconnected from the IO interface and the common ground.
2. The latch-up prevention circuit of claim 1 wherein the ESD event monitoring circuit comprises an RC circuit, a first stage inverter and a second stage inverter;
the first end of the RC circuit is connected with the working power supply, the second end of the RC circuit is grounded, and the third end of the RC circuit is connected with the input end of the first-stage inverter; the output end of the first-stage inverter is respectively connected with the second-stage inverter and the latch event monitoring circuit; the output end of the second stage inverter is connected with the latch event monitoring circuit.
3. The latch-up prevention circuit of claim 2 wherein the first stage inverter comprises switch MN2 and switch MP 2; the second-stage inverter comprises a switch tube MP1 and a switch tube MN 1;
the source electrode of the switching tube MP1 is connected to the working power supply, the drain electrodes are respectively connected to the latch event monitoring circuit and the drain electrode of the switching tube MN1, and the gate electrodes are respectively connected to the drain electrode of the switching tube MP2, the drain electrode of the switching tube MN2, the gate electrode of the switching tube MN1 and the latch event monitoring circuit;
the source electrode of the switch tube MP2 is connected with the working power supply, and the grid electrodes are respectively connected with the third end of the RC circuit and the grid electrode of the switch tube MN 2; the source electrode of the switch tube MN2 is connected with the common ground; the source of the switching tube NM1 is connected to the common ground.
4. The latch prevention circuit of claim 3 wherein the RC circuit comprises a resistor R1 and a capacitor C1;
one end of the resistor R1 is connected with the working power supply, and the other end of the resistor R1 is respectively connected with one end of the capacitor C1 and the grid of the switch tube MP 2; the other end of the capacitor C1 is connected to the common ground.
5. The latch-up prevention circuit of claim 1 wherein the latch-up event monitoring circuit comprises a first control circuit, a second control circuit, a current draw monitoring circuit, a current inrush monitoring circuit, a first level shift circuit, and a second level shift circuit;
one end of the current extraction monitoring circuit is connected with the IO interface, and the other end of the current extraction monitoring circuit is connected with the input end of the first level shift circuit; the electric signal output by the output end of the first level shift circuit is used for indicating the actions of the first driving circuit and the first ESD protection circuit; the first control circuit is used for adjusting the potential of the input end of the first level shifter circuit according to the electric signal;
one end of the current inrush monitoring circuit is connected with the IO interface, and the other end of the current inrush monitoring circuit is connected with the input end of the second level transfer circuit; the electric signal output by the second level shift circuit is used for indicating the actions of the second driving circuit and the second ESD protection circuit; the second control circuit is used for adjusting the potential of the input end of the second level shift circuit according to the electric signal.
6. The latch-up prevention circuit of claim 5 wherein the current draw monitoring circuit comprises a resistor R2, a resistor R3, and a switch MN 6; the first control circuit comprises a switching tube MP 4; the first level shift circuit comprises a resistor R4, a resistor R5, a switch tube MP5 and a switch tube MN 3; the current inrush monitoring circuit comprises a switching tube MP6, a resistor R6 and a resistor R7; the second control circuit comprises a switch tube MN 4; the second level shift circuit comprises a resistor R8, a resistor R9, a switch tube MN5 and a switch tube MP 3;
the gate of the switch tube MP4 is connected to the ESD event monitoring circuit, the source is connected to the first end of the resistor R2, and the drain is connected to the second end of the resistor R2; the first end of the resistor R2 is connected with the source electrode of the switch tube MP5, and the second end is connected with the gate electrode of the switch tube MP5 and one end of the resistor R3; the other end of the resistor R3 is connected with the drain electrode of the switching tube MN 6; the grid electrode of the switching tube MN6 is connected with the common ground, and the source electrode is connected with the IO interface; the source electrode of the switch tube MP5 is connected with the working power supply, the drain electrode of the switch tube MP 3578 is connected with the grid electrode of the switch tube MN3 and one end of the resistor R4, and the other end of the resistor R4 is connected with the IO interface; one end of the resistor R5 is connected with the working power supply, and the other end of the resistor R5 is connected with the drain electrode of the switching tube MN3, the control end of the first driving circuit and the control end of the first ESD protection circuit; the source electrode of the switching tube MN3 is connected with the IO interface;
the grid electrode of the switch tube MN4 is connected with the ESD event monitoring circuit, the source electrode is connected with the first end of the resistor R6, and the drain electrode is connected with the second end of the resistor R6; the first end of the resistor R6 is connected with the common ground, and the second end is respectively connected with one end of the resistor R7 and the grid of the switch tube MN 5; the other end of the resistor R7 is connected with the drain electrode of the switch tube MP 6; the grid electrode of the switching tube MP6 is connected with the working power supply, and the source electrode is connected with the IO interface; the source electrode of the switch tube MN5 is connected with the common ground, and the drain electrode is respectively connected with one end of the resistor R8 and the grid electrode of the switch tube MP 3; the other end of the resistor R8 is connected with the IO interface; the source electrode of the switching tube MP3 is connected with the IO interface, and the drain electrode is respectively connected with one end of a resistor R9, the control end of the second driving circuit and the control end of the second ESD protection circuit; the other end of the resistor R9 is connected to the common ground.
7. An integrated circuit comprising an IO circuit and an anti-latch-up circuit as claimed in any one of claims 1 to 6.
8. The integrated circuit of claim 7, wherein the IO circuit comprises an IO interface, a first driving circuit for connecting to an operating power supply, a second driving circuit for connecting to a common ground, a first ESD protection circuit for connecting to the operating power supply, and a second ESD protection circuit for connecting to the common ground;
the first driving circuit comprises an AND gate circuit and a switching tube MP 7; the second driving circuit comprises an OR gate circuit and a switching tube MN 7;
the first input end of the AND gate circuit is used for connecting a digital circuit, the second input end of the AND gate circuit is connected with the latch event monitoring circuit, and the output end of the AND gate circuit is connected with the grid electrode of the switching tube MP 7; the source electrode of the MP7 is connected with the working power supply, and the drain electrode of the MP7 is connected with the IO interface;
the first input end of the OR gate circuit is used for being connected with the digital circuit, the second input end of the OR gate circuit is connected with the latch event monitoring circuit, and the output end of the OR gate circuit is connected with the grid electrode of the switching tube MN 7; the source of MN7 is connected to the common ground and the drain is connected to the IO interface.
9. The integrated circuit of claim 8, wherein the latch event monitoring circuit comprises a first output and a second output;
and the first output end of the latch event monitoring circuit is connected with the second input end of the AND gate circuit, and the second output end of the latch event monitoring circuit is connected with the second input end of the OR gate circuit.
10. The integrated circuit of claim 9, wherein the first ESD protection circuit comprises a switching tube mpdesd; the second ESD protection circuit comprises a switch tube MNESD;
the grid electrode of the switch tube MPESD is connected with the first output end of the latch-up event monitoring circuit, the source electrode of the switch tube MPESD is connected with the working power supply, and the drain electrode of the switch tube MPESD is connected with the IO interface; and the grid electrode of the switch tube MNESD is connected with the second output end of the latch-up event monitoring circuit, the source electrode of the switch tube MNESD is connected with the common ground, and the drain electrode of the switch tube MNESD is connected with the IO interface.
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| CN109686735A (en) * | 2018-12-27 | 2019-04-26 | 天津大学 | A kind of protection ring structure improving circuit latch-up immunity |
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| US20090180224A1 (en) * | 2008-01-15 | 2009-07-16 | Ming-Dou Ker | Esd protection design for low capacitance specification |
| CN104242275A (en) * | 2013-06-06 | 2014-12-24 | 普诚科技股份有限公司 | Electrostatic discharge protection circuit capable of bearing excess electric property stress and avoiding latching |
| CN105099419A (en) * | 2014-04-16 | 2015-11-25 | 钰太芯微电子科技（上海）有限公司 | Power chip with electrostatic discharge protection function |
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