CN105099419A - Power chip with electrostatic discharge protection function - Google Patents
Power chip with electrostatic discharge protection function Download PDFInfo
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- CN105099419A CN105099419A CN201410153710.8A CN201410153710A CN105099419A CN 105099419 A CN105099419 A CN 105099419A CN 201410153710 A CN201410153710 A CN 201410153710A CN 105099419 A CN105099419 A CN 105099419A
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Abstract
The invention discloses a power chip with an electrostatic discharge protection function, and relates to the field of electronics. The power chip is characterized in that a power supply of the chip provides power for a controller, a switching assembly and a first electrostatic discharge detection circuit; the controller and an input end of a low level control tube are connected to the power ground; the controller is connected with a control end of a high level control tube and a control end of the low level control tube, an output end of the high level control tube is connected with an output end of the low level control tube and acts as an output end of the power chip, an input end of the high level control tube is connected with the power supply, and an electrostatic signal input end of the first electrostatic discharge detection circuit is connected with the power supply; and an electrostatic signal output end of the first electrostatic discharge detection circuit is connected with the controller. According to the invention, rising edge signals of static electricity are detected through two discharge detection circuits, and on-off of the switching assembly is controlled by the electrostatic signal output ends of the discharge detection circuits, thereby releasing static electricity, and avoiding damages imposed on the power chip by the static electricity. The power chip disclosed by the invention has the advantages of easy control and convenient operation through adopting the discharge detection circuits.
Description
Technical field
The present invention relates to a kind of protective circuit, particularly relate to a kind of high-power chip with electrostatic discharge protection.
Background technology
Electrostatic (staticelectricity) is a kind of electric charge remained static.Electrostatic causes the redistribution of electric charge to be formed by friction, also has because attracting each other of electric charge causes the redistribution of electric charge to be formed, and is exactly because material is all made up of atom specifically, has electronegative electronics and positively charged atomic nucleus in atom.Generally nuclear positive charge is equal with the negative electrical charge of electronics, positive negative balance, so electrically not aobvious.If but electronics de-orbits by external force, cause uneven electron distributions, such as triboelectrification is exactly that one causes the unbalanced process of positive and negative charge in fact.When two different objects contact with each other and phase mutual friction time, the electro transfer of an object is to another object, with regard to the positively charged because lacking electronics, and another individuality obtains the object of some excess electrons and electronegative, electrostatic on object band.All likely electrostatic is produced in any time of daily life, any place.When the object contact with electrostatic is to the instantaneous high pressure electric discharge produced during metal pins (pin) of chip, the internal circuit of power chip can be damaged via metal pins, the i.e. infringement that causes of so-called static discharge (Electro-Staticdischarge, ESD).Generally protect mainly for power chip about ESD, because other ESD protection is all universal circuit.ESD circuit can flow through big current (2 amperes), and the electric current of manikin is probably 1.67 amperes, flows through the electric current of 1.67 amperes, can not burn for the general I/O with ESD circuit.But power chip due to volume large, impedance is low, and electrostatic current is out-of-date, usually can ignore ESD circuit and directly flow through power tube, thus causing damage to power chip.
The mode preventing power chip to be subject to static damage at present has two kinds: the mode one, by expanding power tube area resists the impact of ESD, and need working power chip again, cost is high; Two, by adding silicon controlled rectifier (SiliconControlledRectifier, SCR, the large power semiconductor device of a kind of four-layer structure (PNPN)) control electrostatic, silicon controlled rectifier has positive feedback, when there is the impact of ESD first can the impedance of oneself become very low, but silicon controlled rectifier exists unsteadiness, wayward.Will, the electricity of power chip to laying down, need just can be applied in power chip through great many of experiments, for a long time debugging, and cost be high if be triggered suddenly during normal work.
Summary of the invention
The present invention solves the existing power chip resisting ESD impact to there is cost high and there is unstable problem, thus provides the technical scheme of the power chip with electrostatic discharge protection.
Have the power chip of electrostatic discharge protection described in invention, comprising: controller, switch module and the first electrostatic discharge testing circuit, described switch module comprises high level control valve and low level control pipe;
Power power-supply is described controller, described switch module and described first electrostatic discharge testing circuit are powered; The input termination power ground of described controller and described low level control pipe; Described controller connects the control end of described high level control valve and the control end of described low level control pipe, the output of the output of described high level control valve described low level control pipe in parallel is as the output of described power chip, the input termination power power-supply of described high level control valve, the electrostatic signal input of described first electrostatic discharge testing circuit connects described power power-supply; The electrostatic signal output of described first electrostatic discharge testing circuit connects described controller.
Preferably, described high level control valve is PMOS, and the grid of described PMOS connects described controller, and the source electrode of described PMOS connects described power power-supply, and the drain electrode of described PMOS connects the output of described low level control pipe.
Preferably, described low level control pipe is NMOS tube, and the source electrode of described NMOS tube connects power supply ground, and the grid of described NMOS tube connects described controller, and the drain electrode of described NMOS tube connects the drain electrode of described PMOS.
Preferably, the source electrode of described PMOS and one first parasitic diode in parallel between drain electrode;
The positive pole of described first parasitic diode connects the drain electrode of described PMOS, and the negative pole of described first parasitic diode connects the source electrode of described PMOS.
Preferably, the source electrode of described NMOS tube and one second parasitic diode in parallel between drain electrode;
The positive pole of described second parasitic diode connects the source electrode of described NMOS tube, and the negative pole of described second parasitic diode connects the drain electrode of described NMOS tube.
Preferably, also comprise: the second electrostatic discharge testing circuit;
The electrostatic signal input of described second electrostatic discharge testing circuit connects the output of described power chip;
The electrostatic signal output of described second electrostatic discharge testing circuit connects described controller.
Preferably, described first electrostatic discharge testing circuit comprises: electric capacity, resistance and buffer;
One end of described electric capacity is as the electrostatic signal input of described first electrostatic discharge testing circuit;
The other end of described electric capacity connects one end of described resistance and described buffer input simultaneously;
Another termination power ground of described resistance;
The output of described buffer is as the electrostatic signal output of described first electrostatic discharge testing circuit.
Preferably, described second electrostatic discharge testing circuit comprises: electric capacity, resistance and buffer;
One end of described electric capacity is as the electrostatic signal input of described second electrostatic discharge testing circuit;
The other end of described electric capacity connects one end of described resistance and described buffer input simultaneously;
Another termination power ground of described resistance;
The output of described buffer is as the electrostatic signal output of described second electrostatic discharge testing circuit.
Preferably, described controller comprises control unit and driver element, described power power-supply is described control unit and described driver element, described control unit and described driver element connect power supply ground, described control unit connects described driver element, the electrostatic signal output of described first electrostatic discharge testing circuit connects described driver element, the electrostatic signal output of described second electrostatic discharge testing circuit connects described driver element, and driver element connects the control end of described high level control valve and the control end of described low level control pipe.
Beneficial effect of the present invention:
The present invention detects the rising edge signal of electrostatic by two discharge detection circuits, by the shutoff of the electrostatic signal output control switch assembly of discharge detection circuit, thus release electrostatic, avoid the infringement of electrostatic to power chip, the discharge detection circuit that the present invention adopts has easy control, the advantage of simple operation.
Accompanying drawing explanation
Fig. 1 is the power chip circuit diagram that the present invention adds the first electrostatic discharge testing circuit;
Fig. 2 is the power chip circuit diagram that the present invention adds the second electrostatic discharge testing circuit;
Fig. 3 is the schematic diagram of the first electrostatic discharge testing circuit of the present invention.
In accompanying drawing: 1. control unit; 2. driver element; 3. switch module; 31. high level control valves; 311.PMOS pipe; 312. first parasitic diodes; 32. low level control pipes; 321NMOS manages; 322. second parasitic diodes; 4 first electrostatic discharge testing circuits; 5. the second electrostatic discharge testing circuit; 6. controller.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described, but not as limiting to the invention.
In a preferred embodiment, as shown in Figure 1, the invention provides the power chip with electrostatic discharge protection, comprising: controller 6, switch module 3 and the first electrostatic discharge testing circuit 4, switch module 3 comprises high level control valve 31 and low level control pipe 32;
Power power-supply PVDD is controller 6, switch module 3 and the first electrostatic discharge testing circuit 4 are powered; The input termination power ground PGND of controller 6 and low level control pipe 32; Controller 6 connects the control end of high level control valve 31 and the control end of low level control pipe 32, the output of the output of high level control valve 31 low level control pipe 32 in parallel is as the output sw of power chip, the input termination power power-supply PVDD of high level control valve 31, the electrostatic signal input input of the first electrostatic discharge testing circuit 4 connects power power-supply PVDD; The electrostatic signal output vout connection control device 6 of the first electrostatic discharge testing circuit 4.
In the present embodiment, when the first electrostatic discharge testing circuit 4 detects rising edge signal, this control circui high level control valve 31 closes, thus reaches the object of release electrostatic.
In a preferred embodiment, high level control valve 31 is PMOS 311, the grid connection control device 6 of PMOS 311, and the source electrode of PMOS 311 connects power power-supply PVDD, and the drain electrode of PMOS 311 connects the output of low level control pipe 32.
In a preferred embodiment, low level control pipe 32 is NMOS tube 321, and the source electrode of NMOS tube 321 meets power supply ground PGND, the grid connection control device 6 of NMOS tube 321, and the drain electrode of NMOS tube 321 connects the drain electrode of PMOS 311.
In a preferred embodiment, the source electrode of PMOS 311 and one first parasitic diode 312 in parallel between drain electrode;
The positive pole of the first parasitic diode 312 connects the drain electrode of PMOS 311, and the negative pole of the first parasitic diode 312 connects the source electrode of PMOS 311.
In a preferred embodiment, the source electrode of NMOS tube 321 and one second parasitic diode 322 in parallel between drain electrode;
The positive pole of the second parasitic diode 322 connects the source electrode of NMOS tube 321, and the negative pole of the second parasitic diode 322 connects the drain electrode of NMOS tube 321.
In a preferred embodiment, also comprise as shown in Figure 2: the second electrostatic discharge testing circuit 5;
The electrostatic signal input input of the second electrostatic discharge testing circuit 5 connects the output sw of power chip;
The electrostatic signal output vout connection control device 6 of the second electrostatic discharge testing circuit 5.
In a preferred embodiment, the first electrostatic discharge testing circuit 4 comprises as shown in Figure 3: electric capacity C, resistance R and buffer buf;
One end of electric capacity C is as the electrostatic signal input input of the first electrostatic discharge testing circuit 4;
The other end of electric capacity C is one end of contact resistance R and buffer buf input simultaneously;
Another termination power ground PGND of resistance R;
The output of buffer buf is as the electrostatic signal output vout of the first electrostatic discharge testing circuit 4.
In a preferred embodiment, the circuit structure of the second electrostatic discharge testing circuit 5 is identical with the circuit structure of the first electrostatic discharge testing circuit 4.
In a preferred embodiment, controller 6 comprises control unit 1 and driver element 2, power power-supply PVDD is control unit 1 and driver element 2, control unit 1 and driver element 2 meet power supply ground PGND, control unit 1 connects driver element 2, the electrostatic signal output vout of the first electrostatic discharge testing circuit 4 connects driver element 2, the electrostatic signal output vout of the second electrostatic discharge testing circuit 5 connects driver element 2, and driver element 2 connects the control end of high level control valve 31 and the control end of low level control pipe 32.
Above-mentioned control unit 1 and driver element 2 all can adopt the device blocks in existing similar chip to realize, and are not therefore repeating in the present invention.
The first electrostatic discharge testing circuit 4 that present embodiment adopts has the low advantage of cost.
When there is electrostatic, power power-supply PVDD does not work, power power-supply PVDD is the equal of common I/O, when the electrostatic signal input input of the first electrostatic discharge testing circuit 4 detects rising edge signal, and the second electrostatic discharge testing circuit 5 also detects rising edge, illustrate that now pulse is between power power-supply SW and power supply ground PGND, therefore by the electrostatic signal output vout of this first electrostatic discharge testing circuit 4, signal is sent to driver element 2, because power supply does not work, therefore control unit 1 and driver element 2 also do not work, and (power chip is in off position, such as power chip is transported), so by electrostatic signal output vout control switch assembly low level control pipe 32 closed of the first electrostatic discharge testing circuit 4, thus release electrostatic.
When the electrostatic signal input of the first electrostatic discharge testing circuit 4 detects rising edge signal, and the second electrostatic discharge testing circuit 5 can't detect rising edge, illustrate that now pulse is between power power-supply PVDD and power supply ground PGND, signal is sent to driver element 2 by the electrostatic signal output of the second electrostatic discharge testing circuit 5, because driver element 2 does not work, therefore the electrostatic signal output of the second electrostatic discharge testing circuit 5 controls high level control valve 31 and low level control pipe 32 closes, thus reach the object of release electrostatic.
The first above-mentioned electrostatic discharge testing circuit 4 structure is the one topology of electrostatic detection circuit, and the electrostatic detection circuit in the present invention is not limited to foregoing, can be other forms of electrostatic detection circuit.
Power chip is in the present invention not limited to the circuit provided in above-described embodiment, can be other forms of circuit.
The foregoing is only preferred embodiment of the present invention; not thereby embodiments of the present invention and protection range is limited; to those skilled in the art; should recognize and all should be included in the scheme that equivalent replacement done by all utilizations specification of the present invention and diagramatic content and apparent change obtain in protection scope of the present invention.
Claims (9)
1. have the power chip of electrostatic discharge protection, it is characterized in that, comprising: controller, switch module and the first electrostatic discharge testing circuit, described switch module comprises high level control valve and low level control pipe;
Power power-supply is described controller, described switch module and described first electrostatic discharge testing circuit are powered; The input termination power ground of described controller and described low level control pipe; Described controller connects the control end of described high level control valve and the control end of described low level control pipe, the output of the output of described high level control valve described low level control pipe in parallel is as the output of described power chip, the input termination power power-supply of described high level control valve, the electrostatic signal input of described first electrostatic discharge testing circuit connects described power power-supply; The electrostatic signal output of described first electrostatic discharge testing circuit connects described controller.
2. there is the power chip of electrostatic discharge protection as claimed in claim 1; it is characterized in that; described high level control valve is PMOS; the grid of described PMOS connects described controller; the source electrode of described PMOS connects described power power-supply, and the drain electrode of described PMOS connects the output of described low level control pipe.
3. there is the power chip of electrostatic discharge protection as claimed in claim 2; it is characterized in that, described low level control pipe is NMOS tube, and the source electrode of described NMOS tube connects power supply ground; the grid of described NMOS tube connects described controller, and the drain electrode of described NMOS tube connects the drain electrode of described PMOS.
4. there is the power chip of electrostatic discharge protection as claimed in claim 2, it is characterized in that, source electrode and one first parasitic diode in parallel between drain electrode of described PMOS;
The positive pole of described first parasitic diode connects the drain electrode of described PMOS, and the negative pole of described first parasitic diode connects the source electrode of described PMOS.
5. there is the power chip of electrostatic discharge protection as claimed in claim 3, it is characterized in that, source electrode and one second parasitic diode in parallel between drain electrode of described NMOS tube;
The positive pole of described second parasitic diode connects the source electrode of described NMOS tube, and the negative pole of described second parasitic diode connects the drain electrode of described NMOS tube.
6. there is the power chip of electrostatic discharge protection as claimed in claim 1, it is characterized in that, also comprise: the second electrostatic discharge testing circuit;
The electrostatic signal input of described second electrostatic discharge testing circuit connects the output of described power chip;
The electrostatic signal output of described second electrostatic discharge testing circuit connects described controller.
7. have the power chip of electrostatic discharge protection as claimed in claim 1, it is characterized in that, described first electrostatic discharge testing circuit comprises: electric capacity, resistance and buffer;
One end of described electric capacity is as the electrostatic signal input of described first electrostatic discharge testing circuit;
The other end of described electric capacity connects one end of described resistance and described buffer input simultaneously;
Another termination power ground of described resistance;
The output of described buffer is as the electrostatic signal output of described first electrostatic discharge testing circuit.
8. have the power chip of electrostatic discharge protection as claimed in claim 6, it is characterized in that, described second electrostatic discharge testing circuit comprises: electric capacity, resistance and buffer;
One end of described electric capacity is as the electrostatic signal input of described second electrostatic discharge testing circuit;
The other end of described electric capacity connects one end of described resistance and described buffer input simultaneously;
Another termination power ground of described resistance;
The output of described buffer is as the electrostatic signal output of described second electrostatic discharge testing circuit.
9. there is the power chip of electrostatic discharge protection as claimed in claim 6, it is characterized in that, described controller comprises control unit and driver element, described power power-supply is described control unit and described driver element, described control unit and described driver element connect power supply ground, described control unit connects described driver element, the electrostatic signal output of described first electrostatic discharge testing circuit connects described driver element, the electrostatic signal output of described second electrostatic discharge testing circuit connects described driver element, driver element connects the control end of described high level control valve and the control end of described low level control pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410153710.8A CN105099419B (en) | 2014-04-16 | 2014-04-16 | Power chip with electrostatic discharge protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410153710.8A CN105099419B (en) | 2014-04-16 | 2014-04-16 | Power chip with electrostatic discharge protection |
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| Publication Number | Publication Date |
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| CN105099419A true CN105099419A (en) | 2015-11-25 |
| CN105099419B CN105099419B (en) | 2018-06-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410153710.8A Active CN105099419B (en) | 2014-04-16 | 2014-04-16 | Power chip with electrostatic discharge protection |
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| CN (1) | CN105099419B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI672905B (en) * | 2016-03-31 | 2019-09-21 | 美商高通公司 | Electrostatic discharge (esd) isolated input/output (i/o) circuits |
| CN113037254A (en) * | 2021-05-24 | 2021-06-25 | 珠海市杰理科技股份有限公司 | Latch-up prevention circuit and integrated circuit |
| CN113271089A (en) * | 2021-04-14 | 2021-08-17 | 杭州士兰微电子股份有限公司 | Grid driving circuit and intelligent power module thereof |
| CN114123147A (en) * | 2021-10-11 | 2022-03-01 | 杭州傲芯科技有限公司 | Electrostatic discharge protection module for chip and device thereof |
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| CN1212509A (en) * | 1997-07-28 | 1999-03-31 | 日本电气株式会社 | Electrostatic protection circuit |
| US20080068369A1 (en) * | 2006-09-15 | 2008-03-20 | Fuji Electric Device Technology Co., Ltd. | Display driving apparatus |
| CN101385214A (en) * | 2004-03-23 | 2009-03-11 | 沙诺夫公司 | Method and apparatus for protecting a gate oxide using source/bulk pumping |
| CN203883793U (en) * | 2014-04-16 | 2014-10-15 | 钰太芯微电子科技（上海）有限公司 | Power chip with electrostatic discharge protection function |
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2014
- 2014-04-16 CN CN201410153710.8A patent/CN105099419B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212509A (en) * | 1997-07-28 | 1999-03-31 | 日本电气株式会社 | Electrostatic protection circuit |
| CN101385214A (en) * | 2004-03-23 | 2009-03-11 | 沙诺夫公司 | Method and apparatus for protecting a gate oxide using source/bulk pumping |
| US20080068369A1 (en) * | 2006-09-15 | 2008-03-20 | Fuji Electric Device Technology Co., Ltd. | Display driving apparatus |
| CN203883793U (en) * | 2014-04-16 | 2014-10-15 | 钰太芯微电子科技（上海）有限公司 | Power chip with electrostatic discharge protection function |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI672905B (en) * | 2016-03-31 | 2019-09-21 | 美商高通公司 | Electrostatic discharge (esd) isolated input/output (i/o) circuits |
| CN113271089A (en) * | 2021-04-14 | 2021-08-17 | 杭州士兰微电子股份有限公司 | Grid driving circuit and intelligent power module thereof |
| CN113271089B (en) * | 2021-04-14 | 2023-04-11 | 杭州士兰微电子股份有限公司 | Grid driving circuit and intelligent power module thereof |
| CN113037254A (en) * | 2021-05-24 | 2021-06-25 | 珠海市杰理科技股份有限公司 | Latch-up prevention circuit and integrated circuit |
| CN114123147A (en) * | 2021-10-11 | 2022-03-01 | 杭州傲芯科技有限公司 | Electrostatic discharge protection module for chip and device thereof |
| CN114123147B (en) * | 2021-10-11 | 2022-08-09 | 杭州傲芯科技有限公司 | Electrostatic discharge protection module for chip and device thereof |
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| CN105099419B (en) | 2018-06-22 |
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