CN105099419B - Power chip with electrostatic discharge protection - Google Patents
Power chip with electrostatic discharge protection Download PDFInfo
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- CN105099419B CN105099419B CN201410153710.8A CN201410153710A CN105099419B CN 105099419 B CN105099419 B CN 105099419B CN 201410153710 A CN201410153710 A CN 201410153710A CN 105099419 B CN105099419 B CN 105099419B
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Abstract
The invention discloses the power chips with electrostatic discharge protection, are related to electronic field.Device, switch module and the power supply of the first electrostatic discharge testing circuit in order to control of the power power-supply of the chip；The input termination power of controller and low level control pipe；The control terminal of controller connection high level control pipe and the control terminal of low level control pipe, output terminal of the output terminal of the output terminal parallel connection low level control pipe of high level control pipe as power chip, the input termination power power-supply of high level control pipe, the electrostatic signal input terminal connection power power-supply of the first electrostatic discharge testing circuit；The electrostatic signal output terminal connection controller of first electrostatic discharge testing circuit.The present invention detects the rising edge signal of electrostatic by two discharge detection circuits, by the shutdown of the electrostatic signal output terminal control switch module of discharge detection circuit, so as to release electrostatic, avoid damage of the electrostatic to power chip, the present invention has the advantages of being easy to control, simple operation using discharge detection circuit.
Description
Technical field
The present invention relates to a kind of protection circuit more particularly to a kind of high-power chips with electrostatic discharge protection.
Background technology
Electrostatic（static electricity）, it is a kind of charge to remain static.Electrostatic is caused by friction
The redistribution of charge and formed, also have since attracting each other for charge causes the redistribution of charge to be formed, specifically
It is because substance is all made of atom, there is electronegative electronics and positively charged atomic nucleus in atom.Atom under normal circumstances
The positive charge of core is equal with the negative electrical charge of electronics, positive negative balance, so not aobvious electrical.But if electronics is detached from rail by external force
Uneven electronics is caused to be distributed, for example substantial triboelectrification is exactly that one kind causes the unbalanced process of positive and negative charge in road.When two
A different object contacts with each other and during phase mutual friction, and the electronics of an object is transferred to another object, just as lacking
Electronics and it is positively charged, and another individual obtains the objects of some excess electrons and negatively charged, electrostatic on object band.In daily life
Any time living, any place are likely to generate electrostatic.When the object with electrostatic touches the metal pins of chip
（pin）When the electric discharge of generated instantaneous high pressure, the internal circuit of power chip, i.e., so-called electrostatic can be damaged via metal pins
Electric discharge（Electro-Static discharge, ESD）Caused damage.ESD protection is generally related to primarily directed to power
Chip, because other ESD protections are all universal circuits.ESD circuit can flow through high current（2 amperes）, the electric current of manikin
About 1.67 amperes, 1.67 amperes of electric current is flowed through, the general I/O with ESD circuit will not be burnt up.However
For power chip since volume is big, impedance is low, and electrostatic current is out-of-date, it will usually ignore ESD circuit and directly flow through power tube, so as to right
Power chip damages.
At present prevent power chip by static damage mode there are two types of：First, by way of expanding power tube area
The impact of ESD is resisted, needs to re-work power chip, it is of high cost；2nd, by adding in silicon controlled rectifier (SCR) (Silicon
Controlled Rectifier, SCR are a kind of four-layer structures（PNPN）Large power semiconductor device) control electrostatic, controllably
Silicon rectifier has positive feedback, when there are the impedance of oneself can be become very low, but silicon controlled rectifier first during the impact of ESD
There are unstability for device, are difficult to control.If being triggered power chip will be supplied electricity to lay down suddenly during normal work, need
It just can apply in power chip, and of high cost by many experiments, prolonged debugging.
Invention content
The present invention to solve the problems, such as the existing power chip for resisting ESD impact there are of high cost and there are unstable, from
And provide the technical solution of the power chip with electrostatic discharge protection.
The invention power chip with electrostatic discharge protection, including：Controller, switch module and the first electrostatic
Discharge detection circuit, the switch module include high level control pipe and low level control pipe；
Power power-supply is the controller, the switch module and first electrostatic discharge testing circuit are powered；It is described
The input termination power of controller and the low level control pipe；The controller connects the control of the high level control pipe
End and the control terminal of the low level control pipe, the output terminal of the high level control pipe low level control pipe in parallel it is defeated
Output terminal of the outlet as the power chip, the input termination power power-supply of the high level control pipe, first electrostatic
The electrostatic signal input terminal of discharge detection circuit connects the power power-supply；The electrostatic letter of first electrostatic discharge testing circuit
Number output terminal connects the controller.
Preferably, the high level control pipe is PMOS tube, and the grid of the PMOS tube connects the controller, described
The source electrode of PMOS tube connects the power power-supply, and the drain electrode of the PMOS tube connects the output terminal of the low level control pipe.
Preferably, the low level control pipe be NMOS tube, the source electrode of the NMOS tube with connecing power supply, the NMOS tube
Grid connects the controller, and the drain electrode of the NMOS tube connects the drain electrode of the PMOS tube.
Preferably, one first parasitic diode in parallel between the source electrode of the PMOS tube and drain electrode；
The anode of first parasitic diode connects the drain electrode of the PMOS tube, the cathode of first parasitic diode
Connect the source electrode of the PMOS tube.
Preferably, one second parasitic diode in parallel between the source electrode of the NMOS tube and drain electrode；
The anode of second parasitic diode connects the source electrode of the NMOS tube, the cathode of second parasitic diode
Connect the drain electrode of the NMOS tube.
Preferably, it further includes：Second electrostatic discharge testing circuit；
The electrostatic signal input terminal of second electrostatic discharge testing circuit connects the output terminal of the power chip；
The electrostatic signal output terminal of second electrostatic discharge testing circuit connects the controller.
Preferably, first electrostatic discharge testing circuit includes：Capacitance, resistance and buffer；
Electrostatic signal input terminal of the one end of the capacitance as first electrostatic discharge testing circuit；
The other end of the capacitance connects one end of the resistance and the buffer input simultaneously；
Another termination power of the resistance；
Electrostatic signal output terminal of the output terminal of the buffer as first electrostatic discharge testing circuit.
Preferably, second electrostatic discharge testing circuit includes：Capacitance, resistance and buffer；
Electrostatic signal input terminal of the one end of the capacitance as second electrostatic discharge testing circuit；
The other end of the capacitance connects one end of the resistance and the buffer input simultaneously；
Another termination power of the resistance；
Electrostatic signal output terminal of the output terminal of the buffer as second electrostatic discharge testing circuit.
Preferably, the controller includes control unit and driving unit, the power power-supply for described control unit and
With connecing power supply, described control unit connects the driving unit for the driving unit, described control unit and the driving unit,
The electrostatic signal output terminal of first electrostatic discharge testing circuit connects the driving unit, the second static discharge detection
The electrostatic signal output terminal of circuit connects the driving unit, and driving unit connects control terminal and the institute of the high level control pipe
State the control terminal of low level control pipe.
Beneficial effects of the present invention：
The present invention detects the rising edge signal of electrostatic by two discharge detection circuits, is believed by the electrostatic of discharge detection circuit
The shutdown of number output terminal control switch module so as to release electrostatic, avoids damage of the electrostatic to power chip, and the present invention uses
Discharge detection circuit have and be easy to control, the advantages of simple operation.
Description of the drawings
Fig. 1 is the power chip circuit diagram that the present invention adds in the first electrostatic discharge testing circuit；
Fig. 2 is the power chip circuit diagram that the present invention adds in the second electrostatic discharge testing circuit；
Fig. 3 is the schematic diagram of the first electrostatic discharge testing circuit of the present invention.
In attached drawing：1. control unit；2. driving unit；3. switch module；31. high level control pipe；311.PMOS pipe；
312. first parasitic diodes；32. low level control pipe；321NMOS is managed；322. second parasitic diodes；4 first static discharges
Detection circuit；5. the second electrostatic discharge testing circuit；6. controller.
Specific embodiment
The invention will be further described in the following with reference to the drawings and specific embodiments, but not as limiting to the invention.
In a preferred embodiment, as shown in Figure 1, the present invention provides the power chip with electrostatic discharge protection,
Including：Controller 6,3 and first electrostatic discharge testing circuit 4 of switch module, switch module 3 include high level control pipe 31 and low
Level control pipe 32；
Power power-supply PVDD in order to control power by device 6,3 and first electrostatic discharge testing circuit 4 of switch module；6 He of controller
The input termination power of low level control pipe 32 ground PGND；Controller 6 connects the control terminal and low level of high level control pipe 31
The control terminal of control pipe 32, the output terminal of the output terminal parallel connection low level control pipe 32 of high level control pipe 31 is as power chip
Output terminal sw, high level control pipe 31 input termination power power-supply PVDD, the first electrostatic discharge testing circuit 4 electrostatic letter
Number input terminal input connection power power-supplies PVDD；The electrostatic signal output terminal vout connections control of first electrostatic discharge testing circuit 4
Device 6 processed.
In the present embodiment, when the first electrostatic discharge testing circuit 4 detects rising edge signal, which controls high level
Control pipe 31 is closed, so as to achieve the purpose that release electrostatic.
In a preferred embodiment, high level control pipe 31 is PMOS tube 311, and the grid of PMOS tube 311 connects controller
6, the source electrode connection power power-supply PVDD of PMOS tube 311, the output terminal of the drain electrode connection low level control pipe 32 of PMOS tube 311.
In a preferred embodiment, low level control pipe 32 is NMOS tube 321, and the source electrode of NMOS tube 321 is with connecing power supply
PGND, the grid connection controller 6 of NMOS tube 321, the drain electrode of the drain electrode connection PMOS tube 311 of NMOS tube 321.
In a preferred embodiment, one first parasitic diode 312 in parallel between the source electrode of PMOS tube 311 and drain electrode；
The drain electrode of the anode connection PMOS tube 311 of first parasitic diode 312, the cathode of the first parasitic diode 312 connect
Connect the source electrode of PMOS tube 311.
In a preferred embodiment, one second parasitic diode 322 in parallel between the source electrode of NMOS tube 321 and drain electrode；
The source electrode of the anode connection NMOS tube 321 of second parasitic diode 322, the cathode of the second parasitic diode 322 connect
Connect the drain electrode of NMOS tube 321.
In a preferred embodiment, it further includes as shown in Figure 2：Second electrostatic discharge testing circuit 5；
The output terminal sw of the electrostatic signal input terminal input connection power chips of second electrostatic discharge testing circuit 5；
The electrostatic signal output terminal vout connections controller 6 of second electrostatic discharge testing circuit 5.
In a preferred embodiment, the first electrostatic discharge testing circuit 4 as shown in Figure 3 includes：Capacitance C, resistance R and buffering
Device buf；
Electrostatic signal input terminal input of the one end of capacitance C as the first electrostatic discharge testing circuit 4；
The other end of capacitance C connects one end of resistance R and buffer buf input terminals simultaneously；
Another termination power of resistance R ground PGND；
Electrostatic signal output terminal vout of the output terminal of buffer buf as the first electrostatic discharge testing circuit 4.
In a preferred embodiment, the circuit structure of the second electrostatic discharge testing circuit 5 and the first static discharge detection electricity
The circuit structure on road 4 is identical.
In a preferred embodiment, controller 6 includes control unit 1 and driving unit 2, and power power-supply PVDD is single in order to control
PGND, control unit 1 connect driving unit 2 with connecing power supply for member 1 and driving unit 2, control unit 1 and driving unit 2, and first is quiet
The electrostatic signal output terminal vout connections driving unit 2 of discharge of electricity detection circuit 4, the electrostatic of the second electrostatic discharge testing circuit 5
Signal output end vout connections driving unit 2, driving unit 2 connect the control terminal of high level control pipe 31 and low level control pipe
32 control terminal.
Above-mentioned control unit 1 and driving unit 2 may be used device blocks in existing similar chip and realize, therefore
It is not being repeated in the present invention.
The first electrostatic discharge testing circuit 4 that present embodiment uses has the advantages that at low cost.
When there are during electrostatic, power power-supply PVDD does not work, and power power-supply PVDD is the equal of common I/O, when first
When the electrostatic signal input terminal input of electrostatic discharge testing circuit 4 detects rising edge signal, and the second static discharge detection electricity
Road 5 also detects that rising edge, illustrates that pulse at this time is in power power-supply SW and power supply between PGND, therefore first quiet by this
The electrostatic signal output terminal vout of discharge of electricity detection circuit 4 sends the signal to driving unit 2, since power supply does not work, therefore controls
Unit 1 and driving unit 2 processed also do not work（Power chip is in off position, such as power chip is transported）, so by
The closure of the electrostatic signal output terminal vout control switch module low level controls pipe 32 of first electrostatic discharge testing circuit 4, from
And release electrostatic.
When the electrostatic signal input terminal of the first electrostatic discharge testing circuit 4 detects rising edge signal, and the second electrostatic
Discharge detection circuit 5 can't detect rising edge, and it is in power power-supply PVDD and power supply between PGND second to illustrate pulse at this time
The electrostatic signal output terminal of electrostatic discharge testing circuit 5 sends the signal to driving unit 2, since driving unit 2 does not work, therefore
The electrostatic signal output terminal control high level control pipe 31 and low level control pipe 32 of second electrostatic discharge testing circuit 5 are closed,
So as to achieve the purpose that release electrostatic.
Above-mentioned 4 structure of the first electrostatic discharge testing circuit is a kind of topology of electrostatic detection circuit, in the present invention
Electrostatic detection circuit is not limited to the above, can be the electrostatic detection circuit of other forms.
Power chip in the present invention is not limited to the circuit provided in above-described embodiment, can be the electricity of other forms
Road.
The foregoing is merely preferred embodiments of the present invention, not thereby limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all include within the scope of the present invention.
Claims (8)
1. the power chip with electrostatic discharge protection, which is characterized in that including：Controller, switch module and first are quiet
Discharge of electricity detection circuit, the switch module include high level control pipe and low level control pipe；
Power power-supply is the controller, the switch module and first electrostatic discharge testing circuit are powered；The control
The input termination power of device and the low level control pipe；The controller connect the high level control pipe control terminal and
The control terminal of the low level control pipe, the output terminal of the output terminal low level control pipe in parallel of the high level control pipe
As the output terminal of the power chip, the input termination power power-supply of the high level control pipe, first static discharge
The electrostatic signal input terminal of detection circuit connects the power power-supply；The electrostatic signal of first electrostatic discharge testing circuit is defeated
Outlet connects the controller；
It further includes：Second electrostatic discharge testing circuit；
The electrostatic signal input terminal of second electrostatic discharge testing circuit connects the output terminal of the power chip；
The electrostatic signal output terminal of second electrostatic discharge testing circuit connects the controller；
First electrostatic discharge testing circuit and second electrostatic discharge testing circuit are used to detect rising edge signal, foundation
Testing result, the electrostatic signal output terminal of first electrostatic discharge testing circuit control the switching group by the controller
The closure of the low level control pipe of part, so as to release electrostatic；Or the electrostatic letter of second electrostatic discharge testing circuit
Number output terminal controls the high level control pipe and the closure of the low level control pipe by the controller, quiet so as to discharge
Electricity.
2. there is the power chip of electrostatic discharge protection as described in claim 1, which is characterized in that the high level control
It manages as PMOS tube, the grid connection controller of the PMOS tube, the source electrode connection power power-supply of the PMOS tube, institute
The drain electrode for stating PMOS tube connects the output terminal of the low level control pipe.
3. there is the power chip of electrostatic discharge protection as claimed in claim 2, which is characterized in that the low level control
It manages as NMOS tube, with connecing power supply, the grid of the NMOS tube connects the controller, the NMOS tube to the source electrode of the NMOS tube
Drain electrode connect the drain electrode of the PMOS tube.
4. there is the power chip of electrostatic discharge protection as claimed in claim 2, which is characterized in that the source of the PMOS tube
One first parasitic diode in parallel between pole and drain electrode；
The anode of first parasitic diode connects the drain electrode of the PMOS tube, the cathode connection of first parasitic diode
The source electrode of the PMOS tube.
5. there is the power chip of electrostatic discharge protection as claimed in claim 3, which is characterized in that the source of the NMOS tube
One second parasitic diode in parallel between pole and drain electrode；
The anode of second parasitic diode connects the source electrode of the NMOS tube, the cathode connection of second parasitic diode
The drain electrode of the NMOS tube.
6. there is the power chip of electrostatic discharge protection as described in claim 1, which is characterized in that first electrostatic is put
Power detection circuit includes：Capacitance, resistance and buffer；
Electrostatic signal input terminal of the one end of the capacitance as first electrostatic discharge testing circuit；
The other end of the capacitance connects one end of the resistance and the buffer input simultaneously；
Another termination power of the resistance；
Electrostatic signal output terminal of the output terminal of the buffer as first electrostatic discharge testing circuit.
7. there is the power chip of electrostatic discharge protection as described in claim 1, which is characterized in that second electrostatic is put
Power detection circuit includes：Capacitance, resistance and buffer；
Electrostatic signal input terminal of the one end of the capacitance as second electrostatic discharge testing circuit；
The other end of the capacitance connects one end of the resistance and the buffer input simultaneously；
Another termination power of the resistance；
Electrostatic signal output terminal of the output terminal of the buffer as second electrostatic discharge testing circuit.
8. there is the power chip of electrostatic discharge protection as described in claim 1, which is characterized in that the controller includes
Control unit and driving unit, the power power-supply are described control unit and the driving unit, described control unit and institute
State driving unit with connecing power supply, described control unit connects the driving unit, first electrostatic discharge testing circuit it is quiet
Electrical signal connects the driving unit, described in the electrostatic signal output terminal connection of second electrostatic discharge testing circuit
Driving unit, driving unit connect the control terminal of the high level control pipe and the control terminal of the low level control pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410153710.8A CN105099419B (en) | 2014-04-16 | 2014-04-16 | Power chip with electrostatic discharge protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410153710.8A CN105099419B (en) | 2014-04-16 | 2014-04-16 | Power chip with electrostatic discharge protection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105099419A CN105099419A (en) | 2015-11-25 |
| CN105099419B true CN105099419B (en) | 2018-06-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410153710.8A Active CN105099419B (en) | 2014-04-16 | 2014-04-16 | Power chip with electrostatic discharge protection |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10298010B2 (en) * | 2016-03-31 | 2019-05-21 | Qualcomm Incorporated | Electrostatic discharge (ESD) isolated input/output (I/O) circuits |
| CN113271089B (en) * | 2021-04-14 | 2023-04-11 | 杭州士兰微电子股份有限公司 | Grid driving circuit and intelligent power module thereof |
| CN113037254B (en) * | 2021-05-24 | 2021-08-20 | 珠海市杰理科技股份有限公司 | Latch-up prevention circuit and integrated circuit |
| CN114123147B (en) * | 2021-10-11 | 2022-08-09 | 杭州傲芯科技有限公司 | Electrostatic discharge protection module for chip and device thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212509A (en) * | 1997-07-28 | 1999-03-31 | 日本电气株式会社 | Electrostatic protection circuit |
| CN101385214A (en) * | 2004-03-23 | 2009-03-11 | 沙诺夫公司 | Method and apparatus for protecting a gate oxide using source/bulk pumping |
| CN203883793U (en) * | 2014-04-16 | 2014-10-15 | 钰太芯微电子科技（上海）有限公司 | Power chip with electrostatic discharge protection function |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4992359B2 (en) * | 2006-09-15 | 2012-08-08 | 富士電機株式会社 | Display drive device |
-
2014
- 2014-04-16 CN CN201410153710.8A patent/CN105099419B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212509A (en) * | 1997-07-28 | 1999-03-31 | 日本电气株式会社 | Electrostatic protection circuit |
| CN101385214A (en) * | 2004-03-23 | 2009-03-11 | 沙诺夫公司 | Method and apparatus for protecting a gate oxide using source/bulk pumping |
| CN203883793U (en) * | 2014-04-16 | 2014-10-15 | 钰太芯微电子科技（上海）有限公司 | Power chip with electrostatic discharge protection function |
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| CN105099419A (en) | 2015-11-25 |
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